OV - exec - Function ljForce._omp

	Function: ljForce._omp_fn.0	Module: exec	Source: ljForce.c:157-161 [...]	Coverage (incl. loops): 0.79% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 22 - 24

--------------------------------------------------------------------------------

22:    a[0] = 0.0;

23:    a[1] = 0.0;

24:    a[2] = 0.0;

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 157 - 161

--------------------------------------------------------------------------------

157:    #pragma omp parallel for

158:    for (int ii=0; ii<fSize; ++ii)

159:    {

160:       zeroReal3(s->atoms->f[ii]);

161:       s->atoms->U[ii] = 0.;

0x40cfc0 PUSH	%RBP

0x40cfc1 MOV	%RSP,%RBP

0x40cfc4 PUSH	%R12

0x40cfc6 MOV	%RDI,%R12

0x40cfc9 PUSH	%RBX

0x40cfca CALL	403060 <omp_get_num_threads@plt>

0x40cfcf MOV	%EAX,%EBX

0x40cfd1 CALL	403160 <omp_get_thread_num@plt>

0x40cfd6 MOV	%EAX,%ECX

0x40cfd8 MOV	0x8(%R12),%EAX

0x40cfdd CLTD

0x40cfde IDIV	%EBX

0x40cfe0 CMP	%EDX,%ECX

0x40cfe2 JL	40d2e0

0x40cfe8 IMUL	%EAX,%ECX

0x40cfeb LEA	(%RDX,%RCX,1),%R8D

0x40cfef LEA	(%RAX,%R8,1),%ESI

0x40cff3 CMP	%ESI,%R8D

0x40cff6 JGE	40d2d1

0x40cffc MOV	(%R12),%RDI

0x40d000 MOV	%EAX,%ESI

0x40d002 MOV	0x20(%RDI),%R9

0x40d006 MOV	$0x1,%EBX

0x40d00b MOV	0x28(%R9),%RDI

0x40d00f MOV	0x30(%R9),%R9

0x40d013 CMP	$0x1,%EAX

0x40d016 JE	40d2f0

0x40d01c MOVSXD	%ECX,%R11

0x40d01f MOVSXD	%EDX,%R10

0x40d022 LEA	(%R10,%R11,1),%R10

0x40d026 MOV	%EAX,%EBX

0x40d028 LEA	(%R10,%R10,2),%R12

0x40d02c LEA	(%RBX,%R10,1),%R11

0x40d030 LEA	(%RDI,%R12,8),%RDX

0x40d034 LEA	(%R11,%R11,2),%R12

0x40d038 LEA	(%R9,%R10,8),%RCX

0x40d03c LEA	(%RDI,%R12,8),%R12

0x40d040 CMP	%R12,%RCX

0x40d043 JAE	40d052

0x40d045 LEA	(%R9,%R11,8),%R11

0x40d049 CMP	%R11,%RDX

0x40d04c JB	40d2f0

0x40d052 LEA	-0x1(%RAX),%EBX

0x40d055 CMP	$0x2,%EBX

0x40d058 JBE	40d528

0x40d05e MOV	%EAX,%ESI

0x40d060 SHR	$0x2,%ESI

0x40d063 SAL	$0x5,%RSI

0x40d067 LEA	(%RCX,%RSI,1),%R12

0x40d06b SUB	$0x20,%RSI

0x40d06f SHR	$0x5,%RSI

0x40d073 INC	%RSI

0x40d076 VXORPD	%XMM0,%XMM0,%XMM0

0x40d07a AND	$0x7,%ESI

0x40d07d JE	40d15e

0x40d083 CMP	$0x1,%RSI

0x40d087 JE	40d13a

0x40d08d CMP	$0x2,%RSI

0x40d091 JE	40d11f

0x40d097 CMP	$0x3,%RSI

0x40d09b JE	40d104

0x40d09d CMP	$0x4,%RSI

0x40d0a1 JE	40d0e9

0x40d0a3 CMP	$0x5,%RSI

0x40d0a7 JE	40d0ce

0x40d0a9 CMP	$0x6,%RSI

0x40d0ad JNE	40d508

0x40d0b3 VMOVUPD	%YMM0,(%RDX)

0x40d0b7 VMOVUPD	%YMM0,0x20(%RDX)

0x40d0bc VMOVUPD	%YMM0,0x40(%RDX)

0x40d0c1 ADD	$0x20,%RCX

0x40d0c5 VMOVUPD	%YMM0,-0x20(%RCX)

0x40d0ca ADD	$0x60,%RDX

0x40d0ce VMOVUPD	%YMM0,(%RDX)

0x40d0d2 VMOVUPD	%YMM0,0x20(%RDX)

0x40d0d7 VMOVUPD	%YMM0,0x40(%RDX)

0x40d0dc ADD	$0x20,%RCX

0x40d0e0 VMOVUPD	%YMM0,-0x20(%RCX)

0x40d0e5 ADD	$0x60,%RDX

0x40d0e9 VMOVUPD	%YMM0,(%RDX)

0x40d0ed VMOVUPD	%YMM0,0x20(%RDX)

0x40d0f2 VMOVUPD	%YMM0,0x40(%RDX)

0x40d0f7 ADD	$0x20,%RCX

0x40d0fb VMOVUPD	%YMM0,-0x20(%RCX)

0x40d100 ADD	$0x60,%RDX

0x40d104 VMOVUPD	%YMM0,(%RDX)

0x40d108 VMOVUPD	%YMM0,0x20(%RDX)

0x40d10d VMOVUPD	%YMM0,0x40(%RDX)

0x40d112 ADD	$0x20,%RCX

0x40d116 VMOVUPD	%YMM0,-0x20(%RCX)

0x40d11b ADD	$0x60,%RDX

0x40d11f VMOVUPD	%YMM0,(%RDX)

0x40d123 VMOVUPD	%YMM0,0x20(%RDX)

0x40d128 VMOVUPD	%YMM0,0x40(%RDX)

0x40d12d ADD	$0x20,%RCX

0x40d131 VMOVUPD	%YMM0,-0x20(%RCX)

0x40d136 ADD	$0x60,%RDX

0x40d13a VMOVUPD	%YMM0,(%RDX)

0x40d13e VMOVUPD	%YMM0,0x20(%RDX)

0x40d143 VMOVUPD	%YMM0,0x40(%RDX)

0x40d148 ADD	$0x20,%RCX

0x40d14c VMOVUPD	%YMM0,-0x20(%RCX)

0x40d151 ADD	$0x60,%RDX

0x40d155 CMP	%R12,%RCX

0x40d158 JE	40d25c

(89) 0x40d15e VMOVUPD	%YMM0,(%RDX)

(89) 0x40d162 VMOVUPD	%YMM0,0x20(%RDX)

(89) 0x40d167 VMOVUPD	%YMM0,0x40(%RDX)

(89) 0x40d16c ADD	$0x100,%RCX

(89) 0x40d173 VMOVUPD	%YMM0,-0x100(%RCX)

(89) 0x40d17b VMOVUPD	%YMM0,0x60(%RDX)

(89) 0x40d180 VMOVUPD	%YMM0,0x80(%RDX)

(89) 0x40d188 VMOVUPD	%YMM0,0xa0(%RDX)

(89) 0x40d190 VMOVUPD	%YMM0,-0xe0(%RCX)

(89) 0x40d198 VMOVUPD	%YMM0,0xc0(%RDX)

(89) 0x40d1a0 VMOVUPD	%YMM0,0xe0(%RDX)

(89) 0x40d1a8 VMOVUPD	%YMM0,0x100(%RDX)

(89) 0x40d1b0 VMOVUPD	%YMM0,-0xc0(%RCX)

(89) 0x40d1b8 VMOVUPD	%YMM0,0x120(%RDX)

(89) 0x40d1c0 VMOVUPD	%YMM0,0x140(%RDX)

(89) 0x40d1c8 VMOVUPD	%YMM0,0x160(%RDX)

(89) 0x40d1d0 VMOVUPD	%YMM0,-0xa0(%RCX)

(89) 0x40d1d8 VMOVUPD	%YMM0,0x180(%RDX)

(89) 0x40d1e0 VMOVUPD	%YMM0,0x1a0(%RDX)

(89) 0x40d1e8 VMOVUPD	%YMM0,0x1c0(%RDX)

(89) 0x40d1f0 VMOVUPD	%YMM0,-0x80(%RCX)

(89) 0x40d1f5 VMOVUPD	%YMM0,0x1e0(%RDX)

(89) 0x40d1fd VMOVUPD	%YMM0,0x200(%RDX)

(89) 0x40d205 VMOVUPD	%YMM0,0x220(%RDX)

(89) 0x40d20d VMOVUPD	%YMM0,-0x60(%RCX)

(89) 0x40d212 VMOVUPD	%YMM0,0x240(%RDX)

(89) 0x40d21a VMOVUPD	%YMM0,0x260(%RDX)

(89) 0x40d222 VMOVUPD	%YMM0,0x280(%RDX)

(89) 0x40d22a VMOVUPD	%YMM0,-0x40(%RCX)

(89) 0x40d22f VMOVUPD	%YMM0,0x2a0(%RDX)

(89) 0x40d237 VMOVUPD	%YMM0,0x2c0(%RDX)

(89) 0x40d23f VMOVUPD	%YMM0,0x2e0(%RDX)

(89) 0x40d247 VMOVUPD	%YMM0,-0x20(%RCX)

(89) 0x40d24c ADD	$0x300,%RDX

(89) 0x40d253 CMP	%R12,%RCX

(89) 0x40d256 JNE	40d15e

0x40d25c MOV	%EAX,%ECX

0x40d25e AND	$-0x4,%ECX

0x40d261 ADD	%ECX,%R8D

0x40d264 CMP	%ECX,%EAX

0x40d266 JE	40d500

0x40d26c SUB	%ECX,%EAX

0x40d26e MOV	%EAX,%ESI

0x40d270 CMP	$0x1,%EAX

0x40d273 JE	40d52f

0x40d279 VZEROUPPER

0x40d27c ADD	%R10,%RCX

0x40d27f LEA	(%RCX,%RCX,2),%RAX

0x40d283 VXORPD	%XMM1,%XMM1,%XMM1

0x40d287 LEA	(%RDI,%RAX,8),%R10

0x40d28b VMOVUPD	%XMM1,(%R10)

0x40d290 VMOVUPD	%XMM1,0x10(%R10)

0x40d296 VMOVUPD	%XMM1,0x20(%R10)

0x40d29c VMOVUPD	%XMM1,(%R9,%RCX,8)

0x40d2a2 TEST	$0x1,%SIL

0x40d2a6 JE	40d2d1

0x40d2a8 AND	$-0x2,%ESI

0x40d2ab ADD	%ESI,%R8D

0x40d2ae MOVSXD	%R8D,%R8

0x40d2b1 LEA	(%R8,%R8,2),%RDX

0x40d2b5 LEA	(%RDI,%RDX,8),%RDI

0x40d2b9 VXORPD	%XMM2,%XMM2,%XMM2

0x40d2bd MOVQ	$0,0x10(%RDI)

0x40d2c5 VMOVUPD	%XMM2,(%RDI)

0x40d2c9 MOVQ	$0,(%R9,%R8,8)

0x40d2d1 POP	%RBX

0x40d2d2 POP	%R12

0x40d2d4 POP	%RBP

0x40d2d5 RET

0x40d2d6 NOPW	%CS:(%RAX,%RAX,1)

0x40d2e0 INC	%EAX

0x40d2e2 XOR	%EDX,%EDX

0x40d2e4 JMP	40cfe8

0x40d2e9 NOPL	(%RAX)

0x40d2f0 MOVSXD	%R8D,%R11

0x40d2f3 ADD	%R11,%RBX

0x40d2f6 LEA	(%R9,%R11,8),%R12

0x40d2fa LEA	(%R9,%RBX,8),%R9

0x40d2fe MOV	%R9,%RBX

0x40d301 SUB	%R12,%RBX

0x40d304 SUB	$0x8,%RBX

0x40d308 SHR	$0x3,%RBX

0x40d30c LEA	(%R11,%R11,2),%RCX

0x40d310 INC	%RBX

0x40d313 LEA	0x10(%RDI,%RCX,8),%RAX

0x40d318 VXORPD	%XMM3,%XMM3,%XMM3

0x40d31c AND	$0x7,%EBX

0x40d31f JE	40d429

0x40d325 CMP	$0x1,%RBX

0x40d329 JE	40d403

0x40d32f CMP	$0x2,%RBX

0x40d333 JE	40d3e6

0x40d339 CMP	$0x3,%RBX

0x40d33d JE	40d3c9

0x40d343 CMP	$0x4,%RBX

0x40d347 JE	40d3ac

0x40d349 CMP	$0x5,%RBX

0x40d34d JE	40d38f

0x40d34f CMP	$0x6,%RBX

0x40d353 JE	40d372

0x40d355 MOVQ	$0,(%RAX)

0x40d35c VMOVUPD	%XMM3,-0x10(%RAX)

0x40d361 ADD	$0x8,%R12

0x40d365 MOVQ	$0,-0x8(%R12)

0x40d36e ADD	$0x18,%RAX

0x40d372 MOVQ	$0,(%RAX)

0x40d379 VMOVUPD	%XMM3,-0x10(%RAX)

0x40d37e ADD	$0x8,%R12

0x40d382 MOVQ	$0,-0x8(%R12)

0x40d38b ADD	$0x18,%RAX

0x40d38f MOVQ	$0,(%RAX)

0x40d396 VMOVUPD	%XMM3,-0x10(%RAX)

0x40d39b ADD	$0x8,%R12

0x40d39f MOVQ	$0,-0x8(%R12)

0x40d3a8 ADD	$0x18,%RAX

0x40d3ac MOVQ	$0,(%RAX)

0x40d3b3 VMOVUPD	%XMM3,-0x10(%RAX)

0x40d3b8 ADD	$0x8,%R12

0x40d3bc MOVQ	$0,-0x8(%R12)

0x40d3c5 ADD	$0x18,%RAX

0x40d3c9 MOVQ	$0,(%RAX)

0x40d3d0 VMOVUPD	%XMM3,-0x10(%RAX)

0x40d3d5 ADD	$0x8,%R12

0x40d3d9 MOVQ	$0,-0x8(%R12)

0x40d3e2 ADD	$0x18,%RAX

0x40d3e6 MOVQ	$0,(%RAX)

0x40d3ed VMOVUPD	%XMM3,-0x10(%RAX)

0x40d3f2 ADD	$0x8,%R12

0x40d3f6 MOVQ	$0,-0x8(%R12)

0x40d3ff ADD	$0x18,%RAX

0x40d403 MOVQ	$0,(%RAX)

0x40d40a VMOVUPD	%XMM3,-0x10(%RAX)

0x40d40f ADD	$0x8,%R12

0x40d413 MOVQ	$0,-0x8(%R12)

0x40d41c ADD	$0x18,%RAX

0x40d420 CMP	%R9,%R12

0x40d423 JE	40d2d1

(88) 0x40d429 MOVQ	$0,(%RAX)

(88) 0x40d430 VMOVUPD	%XMM3,-0x10(%RAX)

(88) 0x40d435 ADD	$0x40,%R12

(88) 0x40d439 MOVQ	$0,-0x40(%R12)

(88) 0x40d442 MOVQ	$0,0x18(%RAX)

(88) 0x40d44a VMOVUPD	%XMM3,0x8(%RAX)

(88) 0x40d44f MOVQ	$0,-0x38(%R12)

(88) 0x40d458 MOVQ	$0,0x30(%RAX)

(88) 0x40d460 VMOVUPD	%XMM3,0x20(%RAX)

(88) 0x40d465 MOVQ	$0,-0x30(%R12)

(88) 0x40d46e MOVQ	$0,0x48(%RAX)

(88) 0x40d476 VMOVUPD	%XMM3,0x38(%RAX)

(88) 0x40d47b MOVQ	$0,-0x28(%R12)

(88) 0x40d484 MOVQ	$0,0x60(%RAX)

(88) 0x40d48c VMOVUPD	%XMM3,0x50(%RAX)

(88) 0x40d491 MOVQ	$0,-0x20(%R12)

(88) 0x40d49a MOVQ	$0,0x78(%RAX)

(88) 0x40d4a2 VMOVUPD	%XMM3,0x68(%RAX)

(88) 0x40d4a7 MOVQ	$0,-0x18(%R12)

(88) 0x40d4b0 MOVQ	$0,0x90(%RAX)

(88) 0x40d4bb VMOVUPD	%XMM3,0x80(%RAX)

(88) 0x40d4c3 MOVQ	$0,-0x10(%R12)

(88) 0x40d4cc MOVQ	$0,0xa8(%RAX)

(88) 0x40d4d7 VMOVUPD	%XMM3,0x98(%RAX)

(88) 0x40d4df MOVQ	$0,-0x8(%R12)

(88) 0x40d4e8 ADD	$0xc0,%RAX

(88) 0x40d4ee CMP	%R9,%R12

(88) 0x40d4f1 JNE	40d429

0x40d4f7 JMP	40d2d1

0x40d4fc NOPL	(%RAX)

0x40d500 VZEROUPPER

0x40d503 JMP	40d2d1

0x40d508 VMOVUPD	%YMM0,(%RDX)

0x40d50c VMOVUPD	%YMM0,0x20(%RDX)

0x40d511 VMOVUPD	%YMM0,0x40(%RDX)

0x40d516 ADD	$0x20,%RCX

0x40d51a VMOVUPD	%YMM0,-0x20(%RCX)

0x40d51f ADD	$0x60,%RDX

0x40d523 JMP	40d0b3

0x40d528 XOR	%ECX,%ECX

0x40d52a JMP	40d27c

0x40d52f VZEROUPPER

0x40d532 JMP	40d2ae

0x40d537 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.22	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►2.39+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	unknown kernel region	unknown kernel region	kernel

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	ljForce.c:157-161
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-161

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 38.33 to 20.00 cycles (1.92x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 25% of vector register length is used (average across all SSE/AVX instructions).

Details

53% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

71% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
22% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157
VZEROUPPER: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161

Vector unaligned load/store instructions

Detected 28 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 28 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 1216 bytes.

General properties

nb instructions	222
nb uops	230
loop length	948
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.33 cycles
front end	38.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.70	15.60	3.00	3.00	30.50	15.60	15.50	30.50	30.50	30.50	15.60	3.00
cycles	15.70	15.60	3.00	3.00	30.50	15.60	15.50	30.50	30.50	30.50	15.60	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	38.33
Dispatch	30.50
DIV/SQRT	6.00
Overall L1	38.33

Vectorization ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	53%
load	NA (no load vectorizable/vectorized instructions)
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	22%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	40%
load	NA (no load vectorizable/vectorized instructions)
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 38.33 cycles. At this rate:

0% of peak load performance is reached (0.94 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (31.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 38.33 to 30.50 cycles (1.26x speedup).

ASM code

In the binary file, the address of the function is: 40cfc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%R12),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %EBX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 40d2e0 <ljForce._omp_fn.0+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RDX,%RCX,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RAX,%R8,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ESI,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40d2d1 <ljForce._omp_fn.0+0x311>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x20(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x1,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x28(%R9),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%R9),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d2f0 <ljForce._omp_fn.0+0x330>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %ECX,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %EDX,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R10,%R11,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R10,2),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R10,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R11,%R11,2),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R10,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%R12,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R12,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 40d052 <ljForce._omp_fn.0+0x92>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R9,%R11,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 40d2f0 <ljForce._omp_fn.0+0x330>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 40d528 <ljForce._omp_fn.0+0x568>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x5,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RCX,%RSI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x20,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND $0x7,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 40d15e <ljForce._omp_fn.0+0x19e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d13a <ljForce._omp_fn.0+0x17a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d11f <ljForce._omp_fn.0+0x15f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d104 <ljForce._omp_fn.0+0x144>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d0e9 <ljForce._omp_fn.0+0x129>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d0ce <ljForce._omp_fn.0+0x10e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 40d508 <ljForce._omp_fn.0+0x548>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d25c <ljForce._omp_fn.0+0x29c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %ECX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d500 <ljForce._omp_fn.0+0x540>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d52f <ljForce._omp_fn.0+0x56f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
ADD %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RCX,%RCX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%RDI,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD %XMM1,(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM1,0x10(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM1,0x20(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM1,(%R9,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
TEST $0x1,%SIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 40d2d1 <ljForce._omp_fn.0+0x311>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $-0x2,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %ESI,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R8D,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R8,%R8,2),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM2,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ $0,(%R9,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40cfe8 <ljForce._omp_fn.0+0x28>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %R8D,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R11,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R9,%R11,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%RBX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R12,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%R11,%R11,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x10(%RDI,%RCX,8),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND $0x7,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 40d429 <ljForce._omp_fn.0+0x469>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d403 <ljForce._omp_fn.0+0x443>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d3e6 <ljForce._omp_fn.0+0x426>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d3c9 <ljForce._omp_fn.0+0x409>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d3ac <ljForce._omp_fn.0+0x3ec>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d38f <ljForce._omp_fn.0+0x3cf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d372 <ljForce._omp_fn.0+0x3b2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d2d1 <ljForce._omp_fn.0+0x311>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 40d2d1 <ljForce._omp_fn.0+0x311>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 40d2d1 <ljForce._omp_fn.0+0x311>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 40d0b3 <ljForce._omp_fn.0+0xf3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40d27c <ljForce._omp_fn.0+0x2bc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 40d2ae <ljForce._omp_fn.0+0x2ee>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	ljForce.c:157-161
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-161

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 25% of vector register length is used (average across all SSE/AVX instructions).

Details

53% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

71% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
22% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157
VZEROUPPER: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161

Vector unaligned load/store instructions

Detected 28 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 28 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 1216 bytes.

General properties

nb instructions	222
nb uops	230
loop length	948
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.33 cycles
front end	38.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.70	15.60	3.00	3.00	30.50	15.60	15.50	30.50	30.50	30.50	15.60	3.00
cycles	15.70	15.60	3.00	3.00	30.50	15.60	15.50	30.50	30.50	30.50	15.60	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	38.33
Dispatch	30.50
DIV/SQRT	6.00
Overall L1	38.33

Vectorization ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	53%
load	NA (no load vectorizable/vectorized instructions)
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	22%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	40%
load	NA (no load vectorizable/vectorized instructions)
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 38.33 cycles. At this rate:

0% of peak load performance is reached (0.94 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (31.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40cfc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%R12),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %EBX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 40d2e0 <ljForce._omp_fn.0+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RDX,%RCX,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%RAX,%R8,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ESI,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40d2d1 <ljForce._omp_fn.0+0x311>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x20(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x1,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x28(%R9),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%R9),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d2f0 <ljForce._omp_fn.0+0x330>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %ECX,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %EDX,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R10,%R11,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R10,2),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R10,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R11,%R11,2),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R10,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%R12,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R12,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 40d052 <ljForce._omp_fn.0+0x92>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R9,%R11,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 40d2f0 <ljForce._omp_fn.0+0x330>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP $0x2,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 40d528 <ljForce._omp_fn.0+0x568>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x5,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RCX,%RSI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x20,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND $0x7,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 40d15e <ljForce._omp_fn.0+0x19e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d13a <ljForce._omp_fn.0+0x17a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d11f <ljForce._omp_fn.0+0x15f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d104 <ljForce._omp_fn.0+0x144>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d0e9 <ljForce._omp_fn.0+0x129>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d0ce <ljForce._omp_fn.0+0x10e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 40d508 <ljForce._omp_fn.0+0x548>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d25c <ljForce._omp_fn.0+0x29c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %ECX,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d500 <ljForce._omp_fn.0+0x540>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d52f <ljForce._omp_fn.0+0x56f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
ADD %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RCX,%RCX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%RDI,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVUPD %XMM1,(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM1,0x10(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM1,0x20(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM1,(%R9,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
TEST $0x1,%SIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 40d2d1 <ljForce._omp_fn.0+0x311>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $-0x2,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %ESI,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R8D,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R8,%R8,2),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVQ $0,0x10(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM2,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOVQ $0,(%R9,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40cfe8 <ljForce._omp_fn.0+0x28>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %R8D,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R11,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R9,%R11,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%RBX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R12,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%R11,%R11,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x10(%RDI,%RCX,8),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND $0x7,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 40d429 <ljForce._omp_fn.0+0x469>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d403 <ljForce._omp_fn.0+0x443>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d3e6 <ljForce._omp_fn.0+0x426>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d3c9 <ljForce._omp_fn.0+0x409>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d3ac <ljForce._omp_fn.0+0x3ec>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d38f <ljForce._omp_fn.0+0x3cf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d372 <ljForce._omp_fn.0+0x3b2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVUPD %XMM3,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40d2d1 <ljForce._omp_fn.0+0x311>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 40d2d1 <ljForce._omp_fn.0+0x311>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 40d2d1 <ljForce._omp_fn.0+0x311>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVUPD %YMM0,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM0,0x40(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM0,-0x20(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 40d0b3 <ljForce._omp_fn.0+0xf3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40d27c <ljForce._omp_fn.0+0x2bc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 40d2ae <ljForce._omp_fn.0+0x2ee>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼ljForce._omp_fn.0–	0.79	0.04
○Loop 89 - ljForce.c:161-161 - exec	0.79	0.03
○Loop 88 - ljForce.c:161-161 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code