OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.55% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

366:    {

367:       if (iy == gridSize[1]) iy = gridSize[1] - 1;

368:    }

369:    else

370:       iy = gridSize[1];

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x40c9a0 PUSH	%RBP

0x40c9a1 MOV	%RSP,%RBP

0x40c9a4 PUSH	%R15

0x40c9a6 PUSH	%R14

0x40c9a8 PUSH	%R13

0x40c9aa PUSH	%R12

0x40c9ac PUSH	%RBX

0x40c9ad MOV	%RDI,%RBX

0x40c9b0 SUB	$0x28,%RSP

0x40c9b4 MOVSXD	0xc(%RDI),%R14

0x40c9b8 MOV	%RSI,-0x40(%RBP)

0x40c9bc CMP	0x14(%RDI),%R14D

0x40c9c0 JGE	40c9f5

0x40c9c2 MOV	0x78(%RDI),%RDX

0x40c9c6 NOPW	%CS:(%RAX,%RAX,1)

0x40c9d1 NOPW	%CS:(%RAX,%RAX,1)

0x40c9dc NOPL	(%RAX)

(86) 0x40c9e0 MOVL	$0,(%RDX,%R14,4)

(86) 0x40c9e8 INC	%R14

(86) 0x40c9eb CMP	%R14D,0x14(%RBX)

(86) 0x40c9ef JG	40c9e0

0x40c9f1 MOV	0xc(%RBX),%R14D

0x40c9f5 TEST	%R14D,%R14D

0x40c9f8 JLE	40cb6c

0x40c9fe MOV	0x78(%RBX),%R12

0x40ca02 XOR	%R13D,%R13D

0x40ca05 NOPL	(%RAX)

(83) 0x40ca08 MOV	%R13D,%R15D

(83) 0x40ca0b MOV	(%R12,%R13,4),%ECX

(83) 0x40ca0f SAL	$0x6,%R15D

(83) 0x40ca13 LEA	(,%R13,4),%RSI

(83) 0x40ca1b MOV	%R13D,-0x44(%RBP)

(83) 0x40ca1f MOV	%R15D,-0x48(%RBP)

(83) 0x40ca23 MOV	%RSI,-0x38(%RBP)

(83) 0x40ca27 TEST	%ECX,%ECX

(83) 0x40ca29 JLE	40cb60

(83) 0x40ca2f XOR	%R14D,%R14D

  (85) 0x40ca32 MOV	-0x40(%RBP),%RAX

  (85) 0x40ca36 MOV	(%RBX),%EDI

  (85) 0x40ca38 MOV	0x18(%RAX),%R10

  (85) 0x40ca3c MOV	0x4(%RBX),%ECX

  (85) 0x40ca3f MOV	0x8(%RBX),%ESI

  (84) 0x40ca42 MOVSXD	%R15D,%R8

  (84) 0x40ca45 LEA	(%R8,%R8,2),%R9

  (84) 0x40ca49 LEA	(%R10,%R9,8),%R11

  (84) 0x40ca4d VMOVSD	(%R11),%XMM2

  (84) 0x40ca52 VMOVSD	0x8(%R11),%XMM1

  (84) 0x40ca58 VCOMISD	0x30(%RBX),%XMM2

  (84) 0x40ca5d VMOVSD	0x10(%R11),%XMM0

  (84) 0x40ca63 MOV	%EDI,%EAX

  (84) 0x40ca65 JAE	40ca85

  (84) 0x40ca67 VSUBSD	0x18(%RBX),%XMM2,%XMM3

  (84) 0x40ca6c XOR	%EDX,%EDX

  (84) 0x40ca6e VMULSD	0x60(%RBX),%XMM3,%XMM4

  (84) 0x40ca73 VRNDSCALESD	$0x9,%XMM4,%XMM4,%XMM5

  (84) 0x40ca7a VCVTTSD2SI	%XMM5,%EAX

  (84) 0x40ca7e CMP	%EDI,%EAX

  (84) 0x40ca80 SETE	%DL

  (84) 0x40ca83 SUB	%EDX,%EAX

  (84) 0x40ca85 VCOMISD	0x38(%RBX),%XMM1

  (84) 0x40ca8a MOV	%ECX,%R8D

  (84) 0x40ca8d JAE	40cab2

  (84) 0x40ca8f VSUBSD	0x20(%RBX),%XMM1,%XMM6

  (84) 0x40ca94 XOR	%R9D,%R9D

  (84) 0x40ca97 VMULSD	0x68(%RBX),%XMM6,%XMM7

  (84) 0x40ca9c VRNDSCALESD	$0x9,%XMM7,%XMM7,%XMM8

  (84) 0x40caa3 VCVTTSD2SI	%XMM8,%R8D

  (84) 0x40caa8 CMP	%ECX,%R8D

  (84) 0x40caab SETE	%R9B

  (84) 0x40caaf SUB	%R9D,%R8D

  (84) 0x40cab2 VCOMISD	0x40(%RBX),%XMM0

  (84) 0x40cab7 JAE	40cba0

  (84) 0x40cabd VSUBSD	0x28(%RBX),%XMM0,%XMM9

  (84) 0x40cac2 XOR	%R9D,%R9D

  (84) 0x40cac5 VMULSD	0x70(%RBX),%XMM9,%XMM10

  (84) 0x40caca VRNDSCALESD	$0x9,%XMM10,%XMM10,%XMM11

  (84) 0x40cad1 VCVTTSD2SI	%XMM11,%EDX

  (84) 0x40cad6 CMP	%ESI,%EDX

  (84) 0x40cad8 SETE	%R9B

  (84) 0x40cadc SUB	%R9D,%EDX

  (84) 0x40cadf CMP	$-0x1,%EDX

  (84) 0x40cae2 JE	40cbe0

  (84) 0x40cae8 CMP	%ECX,%R8D

  (84) 0x40caeb JE	40cc18

  (84) 0x40caf1 CMP	$-0x1,%R8D

  (84) 0x40caf5 JE	40cc50

  (84) 0x40cafb CMP	%EDI,%EAX

  (84) 0x40cafd JE	40cc78

  (84) 0x40cb03 CMP	$-0x1,%EAX

  (84) 0x40cb06 JE	40cc98

  (84) 0x40cb0c IMUL	%EDI,%R8D

  (84) 0x40cb10 ADD	%EAX,%R8D

  (84) 0x40cb13 MOV	%ECX,%EAX

  (84) 0x40cb15 IMUL	%EDI,%EAX

  (84) 0x40cb18 IMUL	%EDX,%EAX

  (84) 0x40cb1b ADD	%EAX,%R8D

  (84) 0x40cb1e XCHG	%AX,%AX

  (84) 0x40cb20 TEST	%R8D,%R8D

  (84) 0x40cb23 JS	40cca6

  (84) 0x40cb29 CMP	0x14(%RBX),%R8D

  (84) 0x40cb2d JGE	40ccbf

  (84) 0x40cb33 CMP	%R13D,%R8D

  (84) 0x40cb36 JE	40cb80

  (85) 0x40cb38 MOV	-0x44(%RBP),%ECX

  (85) 0x40cb3b MOV	-0x40(%RBP),%RSI

  (85) 0x40cb3f MOV	%R14D,%EDX

  (85) 0x40cb42 MOV	%RBX,%RDI

  (85) 0x40cb45 CALL	40c7f0 <moveAtom>

  (85) 0x40cb4a MOV	0x78(%RBX),%R12

  (85) 0x40cb4e MOV	-0x38(%RBP),%R10

  (85) 0x40cb52 CMP	%R14D,(%R12,%R10,1)

  (85) 0x40cb56 JG	40ca32

(83) 0x40cb5c MOV	0xc(%RBX),%R14D

(83) 0x40cb60 INC	%R13

(83) 0x40cb63 CMP	%R13D,%R14D

(83) 0x40cb66 JG	40ca08

0x40cb6c ADD	$0x28,%RSP

0x40cb70 POP	%RBX

0x40cb71 POP	%R12

0x40cb73 POP	%R13

0x40cb75 POP	%R14

0x40cb77 POP	%R15

0x40cb79 POP	%RBP

0x40cb7a RET

0x40cb7b NOPL	(%RAX,%RAX,1)

  (84) 0x40cb80 MOV	-0x38(%RBP),%R15

  (84) 0x40cb84 INC	%R14D

  (84) 0x40cb87 CMP	%R14D,(%R12,%R15,1)

  (84) 0x40cb8b JLE	40cb5c

  (84) 0x40cb8d MOV	-0x48(%RBP),%EAX

  (84) 0x40cb90 LEA	(%RAX,%R14,1),%R15D

  (84) 0x40cb94 JMP	40ca42

0x40cb99 NOPL	(%RAX)

  (84) 0x40cba0 MOV	%ESI,%R11D

  (84) 0x40cba3 IMUL	%ECX,%R11D

  (84) 0x40cba7 MOV	0xc(%RBX),%EDX

  (84) 0x40cbaa LEA	0x2(%RDI),%R9D

  (84) 0x40cbae LEA	(%RDX,%R11,2),%EDX

  (84) 0x40cbb2 MOV	%R9D,%R11D

  (84) 0x40cbb5 IMUL	%ESI,%R11D

  (84) 0x40cbb9 INC	%R8D

  (84) 0x40cbbc IMUL	%R9D,%R8D

  (84) 0x40cbc0 LEA	(%RDX,%R11,2),%EDX

  (84) 0x40cbc4 LEA	0x2(%RCX),%R11D

  (84) 0x40cbc8 IMUL	%R9D,%R11D

  (84) 0x40cbcc ADD	%R11D,%EDX

  (84) 0x40cbcf ADD	%EDX,%R8D

  (84) 0x40cbd2 LEA	0x1(%R8,%RAX,1),%R8D

  (84) 0x40cbd7 JMP	40cb20

0x40cbdc NOPL	(%RAX)

  (84) 0x40cbe0 MOV	%ESI,%R11D

  (84) 0x40cbe3 IMUL	%ECX,%R11D

  (84) 0x40cbe7 MOV	0xc(%RBX),%EDX

  (84) 0x40cbea LEA	0x2(%RDI),%R9D

  (84) 0x40cbee LEA	(%RDX,%R11,2),%EDX

  (84) 0x40cbf2 MOV	%R9D,%R11D

  (84) 0x40cbf5 IMUL	%ESI,%R11D

  (84) 0x40cbf9 INC	%R8D

  (84) 0x40cbfc IMUL	%R9D,%R8D

  (84) 0x40cc00 LEA	(%RDX,%R11,2),%EDX

  (84) 0x40cc04 ADD	%EDX,%R8D

  (84) 0x40cc07 LEA	0x1(%R8,%RAX,1),%R8D

  (84) 0x40cc0c JMP	40cb20

0x40cc11 NOPL	(%RAX)

  (84) 0x40cc18 MOV	%ESI,%R11D

  (84) 0x40cc1b IMUL	%ECX,%R11D

  (84) 0x40cc1f MOV	0xc(%RBX),%R8D

  (84) 0x40cc23 LEA	0x2(%RDI),%R9D

  (84) 0x40cc27 LEA	(%R8,%R11,2),%R8D

  (84) 0x40cc2b MOV	%R9D,%R11D

  (84) 0x40cc2e IMUL	%ESI,%R11D

  (84) 0x40cc32 IMUL	%EDX,%R9D

  (84) 0x40cc36 ADD	%R11D,%R8D

  (84) 0x40cc39 LEA	(%R8,%R9,1),%EDX

  (84) 0x40cc3d LEA	0x1(%RDX,%RAX,1),%R8D

  (84) 0x40cc42 JMP	40cb20

0x40cc47 NOPW	(%RAX,%RAX,1)

  (84) 0x40cc50 MOV	%ESI,%R9D

  (84) 0x40cc53 IMUL	%ECX,%R9D

  (84) 0x40cc57 MOV	0xc(%RBX),%R8D

  (84) 0x40cc5b LEA	(%R8,%R9,2),%R11D

  (84) 0x40cc5f LEA	0x2(%RDI),%R9D

  (84) 0x40cc63 IMUL	%R9D,%EDX

  (84) 0x40cc67 ADD	%R11D,%EDX

  (84) 0x40cc6a LEA	0x1(%RDX,%RAX,1),%R8D

  (84) 0x40cc6f JMP	40cb20

0x40cc74 NOPL	(%RAX)

  (84) 0x40cc78 MOV	%ESI,%R11D

  (84) 0x40cc7b IMUL	%ECX,%R11D

  (84) 0x40cc7f IMUL	%ECX,%EDX

  (84) 0x40cc82 ADD	0xc(%RBX),%R11D

  (84) 0x40cc86 ADD	%R11D,%EDX

  (84) 0x40cc89 ADD	%EDX,%R8D

  (84) 0x40cc8c JMP	40cb20

0x40cc91 NOPL	(%RAX)

  (84) 0x40cc98 IMUL	%ECX,%EDX

  (84) 0x40cc9b ADD	0xc(%RBX),%EDX

  (84) 0x40cc9e ADD	%EDX,%R8D

  (84) 0x40cca1 JMP	40cb20

0x40cca6 MOV	$0x413000,%ECX

0x40ccab MOV	$0xf6,%EDX

0x40ccb0 MOV	$0x412ef0,%ESI

0x40ccb5 MOV	$0x412fbf,%EDI

0x40ccba CALL	4030c0 <__assert_fail@plt>

0x40ccbf MOV	$0x413000,%ECX

0x40ccc4 MOV	$0xf7,%EDX

0x40ccc9 MOV	$0x412ef0,%ESI

0x40ccce MOV	$0x412fc9,%EDI

0x40ccd3 CALL	4030c0 <__assert_fail@plt>

0x40ccd8 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►61.96+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
►36.20+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►1.75+	redistributeAtoms	timestep.c:148	exec
○	main	CoMD.c:207	exec
○	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,288-304,352-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.50 to 0.56 cycles (15.08x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	49
nb uops	51
loop length	203
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.70	2.60	4.00	4.00	4.50	2.60	2.50	4.50	4.50	4.50	2.60	4.00
cycles	2.70	2.60	4.00	4.00	4.50	2.60	2.50	4.50	4.50	4.50	2.60	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	4.50
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	8%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

1% of peak load performance is reached (3.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.94 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.50 to 4.50 cycles (1.89x speedup).

ASM code

In the binary file, the address of the function is: 40c9a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD 0xc(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP 0x14(%RDI),%R14D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JGE 40c9f5 <updateLinkCells+0x55>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc(%RBX),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40cb6c <updateLinkCells+0x1cc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x413000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf6,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x412ef0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x412fbf,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x413000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x412ef0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x412fc9,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,288-304,352-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	49
nb uops	51
loop length	203
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.70	2.60	4.00	4.00	4.50	2.60	2.50	4.50	4.50	4.50	2.60	4.00
cycles	2.70	2.60	4.00	4.00	4.50	2.60	2.50	4.50	4.50	4.50	2.60	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	4.50
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	8%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

1% of peak load performance is reached (3.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.94 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40c9a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD 0xc(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP 0x14(%RDI),%R14D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JGE 40c9f5 <updateLinkCells+0x55>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc(%RBX),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40cb6c <updateLinkCells+0x1cc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x413000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf6,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x412ef0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x412fbf,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x413000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x412ef0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x412fc9,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.55	0.03
▼Loop 83 - linkCells.c:211-373 - exec–	0.00	0.00
○Loop 84 - linkCells.c:211-373 - exec	0.55	0.89
○Loop 85 - linkCells.c:294-299 - exec	0.00	0.01
○Loop 86 - linkCells.c:384-385 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code