OV - exec - Function putAtomInBox

	Function: putAtomInBox	Module: exec	Source: linkCells.c:173-378 [...]	Coverage (incl. loops): 0.20% \| (excl. loops): 0.20%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 173 - 378

--------------------------------------------------------------------------------

173: {

174:    real_t xyz[3] = {x,y,z};

175:

176:    // Find correct box.

177:    int iBox = getBoxFromCoord(boxes, xyz);

178:    int iOff = iBox*MAXATOMS;

179:    iOff += boxes->nAtoms[iBox];

180:

181:    // assign values to array elements

182:    if (iBox < boxes->nLocalBoxes)

183:       atoms->nLocal++;

184:    boxes->nAtoms[iBox]++;

185:    atoms->gid[iOff] = gid;

186:    atoms->iSpecies[iOff] = iType;

187:

188:    atoms->r[iOff][0] = x;

189:    atoms->r[iOff][1] = y;

190:    atoms->r[iOff][2] = z;

191:

192:    atoms->p[iOff][0] = px;

193:    atoms->p[iOff][1] = py;

194:    atoms->p[iOff][2] = pz;

195: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

366:    {

367:       if (iy == gridSize[1]) iy = gridSize[1] - 1;

368:    }

369:    else

370:       iy = gridSize[1];

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

374:    }

375:    else

376:       iz = gridSize[2];

377:

378:    return getBoxFromTuple(boxes, ix, iy, iz);

0x40c6b0 PUSH	%RBP

0x40c6b1 VUNPCKLPD	%XMM4,%XMM3,%XMM3

0x40c6b5 VUNPCKLPD	%XMM1,%XMM0,%XMM4

0x40c6b9 MOV	%RSP,%RBP

0x40c6bc PUSH	%R15

0x40c6be MOV	%RSI,%R15

0x40c6c1 PUSH	%R14

0x40c6c3 MOV	%EDX,%R14D

0x40c6c6 PUSH	%R13

0x40c6c8 MOV	%ECX,%R13D

0x40c6cb PUSH	%R12

0x40c6cd VMOVQ	%XMM5,%R12

0x40c6d2 PUSH	%RBX

0x40c6d3 MOV	%RDI,%RBX

0x40c6d6 SUB	$0x38,%RSP

0x40c6da VCOMISD	0x30(%RDI),%XMM0

0x40c6df MOV	(%RDI),%ESI

0x40c6e1 JAE	40c702

0x40c6e3 VSUBSD	0x18(%RDI),%XMM0,%XMM0

0x40c6e8 LEA	-0x1(%RSI),%EDX

0x40c6eb VMULSD	0x60(%RDI),%XMM0,%XMM5

0x40c6f0 VRNDSCALESD	$0x9,%XMM5,%XMM5,%XMM6

0x40c6f7 VCVTTSD2SI	%XMM6,%EAX

0x40c6fb CMP	%ESI,%EAX

0x40c6fd CMOVE	%EDX,%EAX

0x40c700 MOV	%EAX,%ESI

0x40c702 VCOMISD	0x38(%RBX),%XMM1

0x40c707 MOV	0x4(%RBX),%EDX

0x40c70a JAE	40c72c

0x40c70c VSUBSD	0x20(%RBX),%XMM1,%XMM1

0x40c711 LEA	-0x1(%RDX),%ECX

0x40c714 VMULSD	0x68(%RBX),%XMM1,%XMM7

0x40c719 VRNDSCALESD	$0x9,%XMM7,%XMM7,%XMM8

0x40c720 VCVTTSD2SI	%XMM8,%EDI

0x40c725 CMP	%EDX,%EDI

0x40c727 CMOVE	%ECX,%EDI

0x40c72a MOV	%EDI,%EDX

0x40c72c VCOMISD	0x40(%RBX),%XMM2

0x40c731 MOV	0x8(%RBX),%ECX

0x40c734 JAE	40c75a

0x40c736 VSUBSD	0x28(%RBX),%XMM2,%XMM9

0x40c73b LEA	-0x1(%RCX),%R9D

0x40c73f VMULSD	0x70(%RBX),%XMM9,%XMM10

0x40c744 VRNDSCALESD	$0x9,%XMM10,%XMM10,%XMM11

0x40c74b VCVTTSD2SI	%XMM11,%R8D

0x40c750 CMP	%R8D,%ECX

0x40c753 CMOVE	%R9D,%R8D

0x40c757 MOV	%R8D,%ECX

0x40c75a MOV	%RBX,%RDI

0x40c75d VMOVSD	%XMM2,-0x58(%RBP)

0x40c762 VMOVAPD	%XMM3,-0x50(%RBP)

0x40c767 VMOVAPD	%XMM4,-0x40(%RBP)

0x40c76c CALL	40c550 <getBoxFromTuple>

0x40c771 MOV	0x78(%RBX),%R11

0x40c775 MOVSXD	%EAX,%RSI

0x40c778 LEA	(%R11,%RSI,4),%RDX

0x40c77c MOV	(%RDX),%EDI

0x40c77e MOV	%EAX,%R10D

0x40c781 SAL	$0x6,%R10D

0x40c785 ADD	%EDI,%R10D

0x40c788 CMP	%EAX,0xc(%RBX)

0x40c78b VMOVAPD	-0x40(%RBP),%XMM12

0x40c790 VMOVAPD	-0x50(%RBP),%XMM13

0x40c795 VMOVSD	-0x58(%RBP),%XMM2

0x40c79a JLE	40c7a1

0x40c79c INCL	(%R15)

0x40c79f MOV	(%RDX),%EDI

0x40c7a1 MOV	0x8(%R15),%RAX

0x40c7a5 MOVSXD	%R10D,%RBX

0x40c7a8 INC	%EDI

0x40c7aa MOV	%EDI,(%RDX)

0x40c7ac MOV	%R14D,(%RAX,%RBX,4)

0x40c7b0 MOV	0x10(%R15),%R14

0x40c7b4 MOV	0x18(%R15),%RCX

0x40c7b8 MOV	%R13D,(%R14,%RBX,4)

0x40c7bc LEA	(%RBX,%RBX,2),%R13

0x40c7c0 SAL	$0x3,%R13

0x40c7c4 ADD	%R13,%RCX

0x40c7c7 ADD	0x20(%R15),%R13

0x40c7cb VMOVUPD	%XMM12,(%RCX)

0x40c7cf VMOVSD	%XMM2,0x10(%RCX)

0x40c7d4 MOV	%R12,0x10(%R13)

0x40c7d8 VMOVUPD	%XMM13,(%R13)

0x40c7de ADD	$0x38,%RSP

0x40c7e2 POP	%RBX

0x40c7e3 POP	%R12

0x40c7e5 POP	%R13

0x40c7e7 POP	%R14

0x40c7e9 POP	%R15

0x40c7eb POP	%RBP

0x40c7ec RET

0x40c7ed NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►17.19+	unloadAtomsBuffer	haloExchange.c:417	exec
○	haloExchange	haloExchange.c:303	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►14.58+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►13.80+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:303	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►13.02+	unloadAtomsBuffer	haloExchange.c:417	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►12.50+	unloadAtomsBuffer	haloExchange.c:417	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►7.29+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:303	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►7.29+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►6.25+	unloadAtomsBuffer	haloExchange.c:417	exec
○	haloExchange	haloExchange.c:303	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►1.30+	createFccLattice	initAtoms.c:100	exec
○	main	CoMD.c:199	exec
○	__libc_start_call_main		libc.so.6
►1.30+	main	CoMD.c:199	exec
○	__libc_start_call_main		libc.so.6
►1.04+	createFccLattice	initAtoms.c:96	exec
○	main	CoMD.c:199	exec
○	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.20% of application time for run gcc_3

Source file and lines	linkCells.c:173-378
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:173-195,352-378.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This function has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.33 to 10.00 cycles (1.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 17.33 to 1.54 cycles (11.24x speedup).

Details

15% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

14% of SSE/AVX loads are used in vector version.
36% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

getBoxFromTuple: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:378

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:183
VCOMISD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:359
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:365
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
VCVTTSD2SI: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VRNDSCALESD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary function is loading 180 bytes (22 double precision FP elements). The binary function is storing 104 bytes (13 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	92
nb uops	104
loop length	320
used x86 registers	16
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.33 cycles
front end	17.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	10.00	10.33	10.33	9.00	9.00	10.00	9.00	9.00	9.00	9.00	10.33
cycles	10.00	10.00	10.33	10.33	9.00	9.00	10.00	9.00	9.00	9.00	9.00	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.33
Dispatch	10.33
Overall L1	17.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	23%
load	16%
store	66%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	15%
load	14%
store	36%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	15%
load	14%
store	20%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	13%
store	14%
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.33 cycles. At this rate:

5% of peak load performance is reached (10.38 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.33 to 10.33 cycles (1.68x speedup).

ASM code

In the binary file, the address of the function is: 40c6b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
VUNPCKLPD %XMM4,%XMM3,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VUNPCKLPD %XMM1,%XMM0,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %ECX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
VMOVQ %XMM5,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCOMISD 0x30(%RDI),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 40c702 <putAtomInBox+0x52>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VSUBSD 0x18(%RDI),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
LEA -0x1(%RSI),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMULSD 0x60(%RDI),%XMM0,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM5,%XMM5,%XMM6	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM6,%EAX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVE %EDX,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCOMISD 0x38(%RBX),%XMM1	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
MOV 0x4(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 40c72c <putAtomInBox+0x7c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VSUBSD 0x20(%RBX),%XMM1,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
LEA -0x1(%RDX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMULSD 0x68(%RBX),%XMM1,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM7,%XMM7,%XMM8	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM8,%EDI	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVE %ECX,%EDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %EDI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCOMISD 0x40(%RBX),%XMM2	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
MOV 0x8(%RBX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 40c75a <putAtomInBox+0xaa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VSUBSD 0x28(%RBX),%XMM2,%XMM9	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
LEA -0x1(%RCX),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMULSD 0x70(%RBX),%XMM9,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM10,%XMM10,%XMM11	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM11,%R8D	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %R8D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVE %R9D,%R8D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
MOV %R8D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM2,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM3,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPD %XMM4,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
CALL 40c550 <getBoxFromTuple>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x78(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EAX,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R11,%RSI,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%R10D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
ADD %EDI,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %EAX,0xc(%RBX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
VMOVAPD -0x40(%RBP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVAPD -0x50(%RBP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD -0x58(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JLE 40c7a1 <putAtomInBox+0xf1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INCL (%R15)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (6.3%)
MOV (%RDX),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R15),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %R10D,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R14D,(%RAX,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%R15),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R15),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13D,(%R14,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RBX,%RBX,2),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD 0x20(%R15),%R13	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VMOVUPD %XMM12,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM2,0x10(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x10(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM13,(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.20% of application time for run gcc_3

Source file and lines	linkCells.c:173-378
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:173-195,352-378.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

15% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

14% of SSE/AVX loads are used in vector version.
36% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

getBoxFromTuple: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:378

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:183
VCOMISD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:359
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:365
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
VCVTTSD2SI: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VRNDSCALESD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary function is loading 180 bytes (22 double precision FP elements). The binary function is storing 104 bytes (13 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	92
nb uops	104
loop length	320
used x86 registers	16
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.33 cycles
front end	17.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	10.00	10.33	10.33	9.00	9.00	10.00	9.00	9.00	9.00	9.00	10.33
cycles	10.00	10.00	10.33	10.33	9.00	9.00	10.00	9.00	9.00	9.00	9.00	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.33
Dispatch	10.33
Overall L1	17.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	23%
load	16%
store	66%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	15%
load	14%
store	36%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	15%
load	14%
store	20%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	13%
store	14%
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.33 cycles. At this rate:

5% of peak load performance is reached (10.38 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40c6b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
VUNPCKLPD %XMM4,%XMM3,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VUNPCKLPD %XMM1,%XMM0,%XMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %ECX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
VMOVQ %XMM5,%R12	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCOMISD 0x30(%RDI),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 40c702 <putAtomInBox+0x52>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VSUBSD 0x18(%RDI),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
LEA -0x1(%RSI),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMULSD 0x60(%RDI),%XMM0,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM5,%XMM5,%XMM6	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM6,%EAX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVE %EDX,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCOMISD 0x38(%RBX),%XMM1	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
MOV 0x4(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 40c72c <putAtomInBox+0x7c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VSUBSD 0x20(%RBX),%XMM1,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
LEA -0x1(%RDX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMULSD 0x68(%RBX),%XMM1,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM7,%XMM7,%XMM8	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM8,%EDI	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVE %ECX,%EDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %EDI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCOMISD 0x40(%RBX),%XMM2	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
MOV 0x8(%RBX),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 40c75a <putAtomInBox+0xaa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VSUBSD 0x28(%RBX),%XMM2,%XMM9	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
LEA -0x1(%RCX),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMULSD 0x70(%RBX),%XMM9,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM10,%XMM10,%XMM11	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM11,%R8D	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %R8D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVE %R9D,%R8D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
MOV %R8D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM2,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM3,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPD %XMM4,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
CALL 40c550 <getBoxFromTuple>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x78(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EAX,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R11,%RSI,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%R10D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
ADD %EDI,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP %EAX,0xc(%RBX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
VMOVAPD -0x40(%RBP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVAPD -0x50(%RBP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD -0x58(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JLE 40c7a1 <putAtomInBox+0xf1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INCL (%R15)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (6.3%)
MOV (%RDX),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R15),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %R10D,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
INC %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R14D,(%RAX,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%R15),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R15),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13D,(%R14,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RBX,%RBX,2),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD 0x20(%R15),%R13	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VMOVUPD %XMM12,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM2,0x10(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x10(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM13,(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
○putAtomInBox	0.20	0.01

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Code clean check

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Vectorization

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Execution units bottlenecks

FMA

Workaround

CALL instructions

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Complex instructions

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Details

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code