OV - exec - Function createFccLattice

	Function: createFccLattice	Module: exec	Source: initAtoms.c:67-109 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 67 - 109

--------------------------------------------------------------------------------

67: {

68:    const real_t* localMin = s->domain->localMin; // alias

[...]

80:    for (int ii=0; ii<3; ++ii)

81:    {

82:       begin[ii] = floor(localMin[ii]/lat);

83:       end[ii]   = ceil (localMax[ii]/lat);

84:    }

85:

86:    real_t px,py,pz;

87:    px=py=pz=0.0;

88:    for (int ix=begin[0]; ix<end[0]; ++ix)

89:       for (int iy=begin[1]; iy<end[1]; ++iy)

90:          for (int iz=begin[2]; iz<end[2]; ++iz)

91:             for (int ib=0; ib<nb; ++ib)

92:             {

93:                real_t rx = (ix+basis[ib][0]) * lat;

94:                real_t ry = (iy+basis[ib][1]) * lat;

95:                real_t rz = (iz+basis[ib][2]) * lat;

96:                if (rx < localMin[0] || rx >= localMax[0]) continue;

97:                if (ry < localMin[1] || ry >= localMax[1]) continue;

98:                if (rz < localMin[2] || rz >= localMax[2]) continue;

99:                int id = ib+nb*(iz+nz*(iy+ny*(ix)));

100:                putAtomInBox(s->boxes, s->atoms, id, 0, rx, ry, rz, px, py, pz);

101:             }

102:

103:    // set total atoms in simulation

104:    startTimer(commReduceTimer);

105:    addIntParallel(&s->atoms->nLocal, &s->atoms->nGlobal, 1);

106:    stopTimer(commReduceTimer);

107:

108:    assert(s->atoms->nGlobal == nb*nx*ny*nz);

109: }

0x40b000 PUSH	%RBP

0x40b001 VMOVAPD	%XMM0,%XMM9

0x40b005 MOV	%RSP,%RBP

0x40b008 PUSH	%R15

0x40b00a MOV	%RCX,%R15

0x40b00d PUSH	%R14

0x40b00f PUSH	%R13

0x40b011 PUSH	%R12

0x40b013 MOV	%ESI,%R12D

0x40b016 PUSH	%RBX

0x40b017 SUB	$0x78,%RSP

0x40b01b VMOVSD	0x7705(%RIP),%XMM0

0x40b023 MOV	0x10(%RCX),%RBX

0x40b027 VDIVSD	%XMM9,%XMM0,%XMM2

0x40b02c MOV	%EDI,-0x98(%RBP)

0x40b032 MOV	%EDX,-0x74(%RBP)

0x40b035 VMULSD	0x60(%RBX),%XMM2,%XMM1

0x40b03a VMULSD	0x78(%RBX),%XMM2,%XMM4

0x40b03f VMULSD	0x68(%RBX),%XMM2,%XMM6

0x40b044 VMULSD	0x80(%RBX),%XMM2,%XMM8

0x40b04c VMULSD	0x70(%RBX),%XMM2,%XMM11

0x40b051 VRNDSCALESD	$0x9,%XMM1,%XMM1,%XMM3

0x40b058 VRNDSCALESD	$0xa,%XMM4,%XMM4,%XMM5

0x40b05f VCVTTSD2SI	%XMM3,%R13D

0x40b063 VCVTTSD2SI	%XMM5,%EAX

0x40b067 VRNDSCALESD	$0x9,%XMM6,%XMM6,%XMM7

0x40b06e VRNDSCALESD	$0xa,%XMM8,%XMM8,%XMM10

0x40b075 VMULSD	0x88(%RBX),%XMM2,%XMM12

0x40b07d VCVTTSD2SI	%XMM7,%R10D

0x40b081 VCVTTSD2SI	%XMM10,%R9D

0x40b086 MOV	%EAX,-0x90(%RBP)

0x40b08c CMP	%R13D,%EAX

0x40b08f JLE	40b52d

0x40b095 CMP	%R9D,%R10D

0x40b098 JGE	40b52d

0x40b09e MOV	%EDX,%ECX

0x40b0a0 MOV	%EDX,%EDI

0x40b0a2 MOV	%R13D,%EDX

0x40b0a5 IMUL	%R12D,%EDX

0x40b0a9 VRNDSCALESD	$0x9,%XMM11,%XMM11,%XMM13

0x40b0b0 VCVTTSD2SI	%XMM13,%ESI

0x40b0b5 ADD	%R10D,%EDX

0x40b0b8 IMUL	%R12D,%EDI

0x40b0bc IMUL	%EDX,%ECX

0x40b0bf MOV	%ESI,-0x78(%RBP)

0x40b0c2 MOV	%R10D,-0x94(%RBP)

0x40b0c9 MOV	%R9D,-0x80(%RBP)

0x40b0cd MOV	%R12D,-0x9c(%RBP)

0x40b0d4 LEA	0x3(,%RSI,4),%R8D

0x40b0dc VRNDSCALESD	$0xa,%XMM12,%XMM12,%XMM14

0x40b0e3 VMOVSD	0x7df5(%RIP),%XMM13

0x40b0eb VCVTTSD2SI	%XMM14,%R14D

0x40b0f0 VMOVSD	0x7de0(%RIP),%XMM14

0x40b0f8 MOV	%EDI,-0x8c(%RBP)

0x40b0fe MOV	%R8D,-0x7c(%RBP)

0x40b102 VXORPS	%XMM15,%XMM15,%XMM15

0x40b107 MOV	%ECX,%EDI

0x40b109 MOV	%R13D,%R8D

(73) 0x40b10c VCVTSI2SD	%R8D,%XMM15,%XMM0

(73) 0x40b111 MOV	-0x94(%RBP),%R12D

(73) 0x40b118 VADDSD	%XMM14,%XMM0,%XMM2

(73) 0x40b11d VADDSD	%XMM13,%XMM0,%XMM1

(73) 0x40b122 VMULSD	%XMM9,%XMM2,%XMM11

(73) 0x40b127 VMULSD	%XMM9,%XMM1,%XMM10

(73) 0x40b12c CMP	%R14D,-0x78(%RBP)

(73) 0x40b130 JGE	40b50c

(73) 0x40b136 MOV	%R8D,-0x84(%RBP)

(73) 0x40b13d MOV	%EDI,-0x88(%RBP)

(73) 0x40b143 MOV	%R12D,%ESI

(73) 0x40b146 MOV	%EDI,%EAX

(73) 0x40b148 MOV	%R15,%RDX

(73) 0x40b14b MOV	%R14D,%R12D

(73) 0x40b14e XCHG	%AX,%AX

  (75) 0x40b150 VCVTSI2SD	%ESI,%XMM15,%XMM3

  (75) 0x40b154 MOV	-0x7c(%RBP),%R14D

  (75) 0x40b158 MOV	-0x78(%RBP),%R9D

  (75) 0x40b15c MOV	%EAX,-0x34(%RBP)

  (75) 0x40b15f VADDSD	%XMM14,%XMM3,%XMM4

  (75) 0x40b164 VADDSD	%XMM13,%XMM3,%XMM5

  (75) 0x40b169 MOV	%ESI,-0x38(%RBP)

  (75) 0x40b16c VMULSD	%XMM9,%XMM4,%XMM12

  (75) 0x40b171 VMULSD	%XMM9,%XMM5,%XMM8

  (75) 0x40b176 LEA	(%R14,%RAX,4),%R10D

  (75) 0x40b17a MOV	%R9D,%R13D

  (75) 0x40b17d MOV	%RDX,%R14

  (75) 0x40b180 MOV	%R10D,%R15D

  (75) 0x40b183 NOPL	(%RAX,%RAX,1)

    (74) 0x40b188 VCVTSI2SD	%R13D,%XMM15,%XMM6

    (74) 0x40b18d VMOVSD	0x60(%RBX),%XMM2

    (74) 0x40b192 VCOMISD	%XMM11,%XMM2

    (74) 0x40b197 VADDSD	%XMM14,%XMM6,%XMM7

    (74) 0x40b19c VADDSD	%XMM13,%XMM6,%XMM0

    (74) 0x40b1a1 VMULSD	%XMM9,%XMM7,%XMM7

    (74) 0x40b1a6 VMULSD	%XMM9,%XMM0,%XMM1

    (74) 0x40b1ab JA	40b350

    (74) 0x40b1b1 VCOMISD	0x78(%RBX),%XMM11

    (74) 0x40b1b6 JAE	40b350

    (74) 0x40b1bc VCOMISD	0x68(%RBX),%XMM12

    (74) 0x40b1c1 JB	40b290

    (74) 0x40b1c7 VCOMISD	0x80(%RBX),%XMM12

    (74) 0x40b1cf JAE	40b290

    (74) 0x40b1d5 VCOMISD	0x70(%RBX),%XMM7

    (74) 0x40b1da JB	40b290

    (74) 0x40b1e0 VCOMISD	0x88(%RBX),%XMM7

    (74) 0x40b1e8 JAE	40b290

    (74) 0x40b1ee VXORPD	%XMM5,%XMM5,%XMM5

    (74) 0x40b1f2 MOV	0x20(%R14),%RSI

    (74) 0x40b1f6 MOV	0x18(%R14),%RDI

    (74) 0x40b1fa VMOVAPD	%XMM7,%XMM2

    (74) 0x40b1fe VMOVSD	%XMM1,-0x58(%RBP)

    (74) 0x40b203 VMOVAPD	%XMM11,%XMM0

    (74) 0x40b207 VMOVAPD	%XMM12,%XMM1

    (74) 0x40b20b XOR	%ECX,%ECX

    (74) 0x40b20d LEA	-0x3(%R15),%EDX

    (74) 0x40b211 VMOVAPD	%XMM5,%XMM4

    (74) 0x40b215 VMOVAPD	%XMM5,%XMM3

    (74) 0x40b219 VMOVSD	%XMM8,-0x70(%RBP)

    (74) 0x40b21e VMOVSD	%XMM9,-0x68(%RBP)

    (74) 0x40b223 VMOVSD	%XMM10,-0x60(%RBP)

    (74) 0x40b228 VMOVSD	%XMM7,-0x50(%RBP)

    (74) 0x40b22d VMOVSD	%XMM12,-0x48(%RBP)

    (74) 0x40b232 VMOVSD	%XMM11,-0x40(%RBP)

    (74) 0x40b237 CALL	40c6b0 <putAtomInBox>

    (74) 0x40b23c VMOVSD	0x60(%RBX),%XMM2

    (74) 0x40b241 VMOVSD	-0x40(%RBP),%XMM11

    (74) 0x40b246 VMOVSD	-0x48(%RBP),%XMM12

    (74) 0x40b24b VCOMISD	%XMM11,%XMM2

    (74) 0x40b250 VMOVSD	-0x50(%RBP),%XMM7

    (74) 0x40b255 VMOVSD	-0x58(%RBP),%XMM1

    (74) 0x40b25a VMOVSD	-0x60(%RBP),%XMM10

    (74) 0x40b25f VMOVSD	-0x68(%RBP),%XMM9

    (74) 0x40b264 VMOVSD	0x7c6c(%RIP),%XMM14

    (74) 0x40b26c VMOVSD	0x7c6c(%RIP),%XMM13

    (74) 0x40b274 VMOVSD	-0x70(%RBP),%XMM8

    (74) 0x40b279 VXORPS	%XMM15,%XMM15,%XMM15

    (74) 0x40b27e JA	40b350

    (74) 0x40b284 VCOMISD	0x78(%RBX),%XMM11

    (74) 0x40b289 JAE	40b350

    (74) 0x40b28f NOP

    (74) 0x40b290 VCOMISD	0x68(%RBX),%XMM8

    (74) 0x40b295 JB	40b350

    (74) 0x40b29b VCOMISD	0x80(%RBX),%XMM8

    (74) 0x40b2a3 JAE	40b350

    (74) 0x40b2a9 VCOMISD	0x70(%RBX),%XMM1

    (74) 0x40b2ae JB	40b350

    (74) 0x40b2b4 VCOMISD	0x88(%RBX),%XMM1

    (74) 0x40b2bc JAE	40b350

    (74) 0x40b2c2 VXORPD	%XMM5,%XMM5,%XMM5

    (74) 0x40b2c6 MOV	0x20(%R14),%RSI

    (74) 0x40b2ca MOV	0x18(%R14),%RDI

    (74) 0x40b2ce VMOVAPD	%XMM1,%XMM2

    (74) 0x40b2d2 VMOVSD	%XMM1,-0x50(%RBP)

    (74) 0x40b2d7 VMOVAPD	%XMM11,%XMM0

    (74) 0x40b2db VMOVAPD	%XMM8,%XMM1

    (74) 0x40b2df LEA	-0x2(%R15),%EDX

    (74) 0x40b2e3 VMOVAPD	%XMM5,%XMM4

    (74) 0x40b2e7 VMOVAPD	%XMM5,%XMM3

    (74) 0x40b2eb XOR	%ECX,%ECX

    (74) 0x40b2ed VMOVSD	%XMM12,-0x70(%RBP)

    (74) 0x40b2f2 VMOVSD	%XMM9,-0x68(%RBP)

    (74) 0x40b2f7 VMOVSD	%XMM10,-0x60(%RBP)

    (74) 0x40b2fc VMOVSD	%XMM7,-0x58(%RBP)

    (74) 0x40b301 VMOVSD	%XMM8,-0x48(%RBP)

    (74) 0x40b306 VMOVSD	%XMM11,-0x40(%RBP)

    (74) 0x40b30b CALL	40c6b0 <putAtomInBox>

    (74) 0x40b310 VMOVSD	0x60(%RBX),%XMM2

    (74) 0x40b315 VMOVSD	-0x70(%RBP),%XMM12

    (74) 0x40b31a VMOVSD	0x7bbe(%RIP),%XMM13

    (74) 0x40b322 VMOVSD	0x7bae(%RIP),%XMM14

    (74) 0x40b32a VMOVSD	-0x68(%RBP),%XMM9

    (74) 0x40b32f VMOVSD	-0x60(%RBP),%XMM10

    (74) 0x40b334 VMOVSD	-0x58(%RBP),%XMM7

    (74) 0x40b339 VMOVSD	-0x50(%RBP),%XMM1

    (74) 0x40b33e VMOVSD	-0x48(%RBP),%XMM8

    (74) 0x40b343 VMOVSD	-0x40(%RBP),%XMM11

    (74) 0x40b348 VXORPS	%XMM15,%XMM15,%XMM15

    (74) 0x40b34d NOPL	(%RAX)

    (74) 0x40b350 VCOMISD	%XMM10,%XMM2

    (74) 0x40b355 JA	40b4d0

    (74) 0x40b35b VCOMISD	0x78(%RBX),%XMM10

    (74) 0x40b360 JAE	40b4d0

    (74) 0x40b366 VCOMISD	0x68(%RBX),%XMM12

    (74) 0x40b36b JB	40b430

    (74) 0x40b371 VCOMISD	0x80(%RBX),%XMM12

    (74) 0x40b379 JAE	40b430

    (74) 0x40b37f VCOMISD	0x70(%RBX),%XMM1

    (74) 0x40b384 JB	40b430

    (74) 0x40b38a VCOMISD	0x88(%RBX),%XMM1

    (74) 0x40b392 JAE	40b430

    (74) 0x40b398 VXORPD	%XMM5,%XMM5,%XMM5

    (74) 0x40b39c MOV	0x20(%R14),%RSI

    (74) 0x40b3a0 MOV	0x18(%R14),%RDI

    (74) 0x40b3a4 VMOVAPD	%XMM1,%XMM2

    (74) 0x40b3a8 VMOVAPD	%XMM10,%XMM0

    (74) 0x40b3ac VMOVAPD	%XMM12,%XMM1

    (74) 0x40b3b0 XOR	%ECX,%ECX

    (74) 0x40b3b2 LEA	-0x1(%R15),%EDX

    (74) 0x40b3b6 VMOVAPD	%XMM5,%XMM4

    (74) 0x40b3ba VMOVAPD	%XMM5,%XMM3

    (74) 0x40b3be VMOVSD	%XMM8,-0x68(%RBP)

    (74) 0x40b3c3 VMOVSD	%XMM9,-0x60(%RBP)

    (74) 0x40b3c8 VMOVSD	%XMM11,-0x50(%RBP)

    (74) 0x40b3cd VMOVSD	%XMM12,-0x48(%RBP)

    (74) 0x40b3d2 VMOVSD	%XMM10,-0x40(%RBP)

    (74) 0x40b3d7 VMOVSD	%XMM7,-0x58(%RBP)

    (74) 0x40b3dc CALL	40c6b0 <putAtomInBox>

    (74) 0x40b3e1 VMOVSD	-0x40(%RBP),%XMM10

    (74) 0x40b3e6 VMOVSD	-0x48(%RBP),%XMM12

    (74) 0x40b3eb VCOMISD	0x60(%RBX),%XMM10

    (74) 0x40b3f0 VMOVSD	-0x50(%RBP),%XMM11

    (74) 0x40b3f5 VMOVSD	-0x60(%RBP),%XMM9

    (74) 0x40b3fa VMOVSD	0x7ad6(%RIP),%XMM14

    (74) 0x40b402 VMOVSD	0x7ad6(%RIP),%XMM13

    (74) 0x40b40a VMOVSD	-0x68(%RBP),%XMM8

    (74) 0x40b40f VXORPS	%XMM15,%XMM15,%XMM15

    (74) 0x40b414 JB	40b4d0

    (74) 0x40b41a VCOMISD	0x78(%RBX),%XMM10

    (74) 0x40b41f VMOVSD	-0x58(%RBP),%XMM7

    (74) 0x40b424 JAE	40b4d0

    (74) 0x40b42a NOPW	(%RAX,%RAX,1)

    (74) 0x40b430 VCOMISD	0x68(%RBX),%XMM8

    (74) 0x40b435 JB	40b4d0

    (74) 0x40b43b VCOMISD	0x80(%RBX),%XMM8

    (74) 0x40b443 JAE	40b4d0

    (74) 0x40b449 VCOMISD	0x70(%RBX),%XMM7

    (74) 0x40b44e JB	40b4d0

    (74) 0x40b454 VCOMISD	0x88(%RBX),%XMM7

    (74) 0x40b45c JAE	40b4d0

    (74) 0x40b45e VXORPD	%XMM5,%XMM5,%XMM5

    (74) 0x40b462 MOV	0x20(%R14),%RSI

    (74) 0x40b466 MOV	0x18(%R14),%RDI

    (74) 0x40b46a VMOVAPD	%XMM8,%XMM1

    (74) 0x40b46e VMOVAPD	%XMM10,%XMM0

    (74) 0x40b472 VMOVAPD	%XMM5,%XMM4

    (74) 0x40b476 VMOVAPD	%XMM5,%XMM3

    (74) 0x40b47a VMOVAPD	%XMM7,%XMM2

    (74) 0x40b47e XOR	%ECX,%ECX

    (74) 0x40b480 MOV	%R15D,%EDX

    (74) 0x40b483 VMOVSD	%XMM12,-0x60(%RBP)

    (74) 0x40b488 VMOVSD	%XMM9,-0x58(%RBP)

    (74) 0x40b48d VMOVSD	%XMM11,-0x50(%RBP)

    (74) 0x40b492 VMOVSD	%XMM8,-0x48(%RBP)

    (74) 0x40b497 VMOVSD	%XMM10,-0x40(%RBP)

    (74) 0x40b49c CALL	40c6b0 <putAtomInBox>

    (74) 0x40b4a1 VMOVSD	-0x60(%RBP),%XMM12

    (74) 0x40b4a6 VMOVSD	0x7a32(%RIP),%XMM13

    (74) 0x40b4ae VMOVSD	0x7a22(%RIP),%XMM14

    (74) 0x40b4b6 VMOVSD	-0x58(%RBP),%XMM9

    (74) 0x40b4bb VMOVSD	-0x50(%RBP),%XMM11

    (74) 0x40b4c0 VMOVSD	-0x48(%RBP),%XMM8

    (74) 0x40b4c5 VMOVSD	-0x40(%RBP),%XMM10

    (74) 0x40b4ca VXORPS	%XMM15,%XMM15,%XMM15

    (74) 0x40b4cf NOP

    (74) 0x40b4d0 INC	%R13D

    (74) 0x40b4d3 ADD	$0x4,%R15D

    (74) 0x40b4d7 CMP	%R13D,%R12D

    (74) 0x40b4da JNE	40b188

  (75) 0x40b4e0 MOV	-0x38(%RBP),%ESI

  (75) 0x40b4e3 MOV	-0x34(%RBP),%EAX

  (75) 0x40b4e6 MOV	-0x74(%RBP),%ECX

  (75) 0x40b4e9 INC	%ESI

  (75) 0x40b4eb MOV	%R14,%RDX

  (75) 0x40b4ee ADD	%ECX,%EAX

  (75) 0x40b4f0 CMP	%ESI,-0x80(%RBP)

  (75) 0x40b4f3 JNE	40b150

(73) 0x40b4f9 MOV	-0x84(%RBP),%R8D

(73) 0x40b500 MOV	-0x88(%RBP),%EDI

(73) 0x40b506 MOV	%R12D,%R14D

(73) 0x40b509 MOV	%RDX,%R15

(73) 0x40b50c MOV	-0x8c(%RBP),%R11D

(73) 0x40b513 INC	%R8D

(73) 0x40b516 ADD	%R11D,%EDI

(73) 0x40b519 CMP	%R8D,-0x90(%RBP)

(73) 0x40b520 JNE	40b10c

0x40b526 MOV	-0x9c(%RBP),%R12D

0x40b52d MOV	$0xa,%EDI

0x40b532 CALL	40ea60 <profileStart>

0x40b537 MOV	0x20(%R15),%RDI

0x40b53b MOV	$0x1,%EDX

0x40b540 LEA	0x4(%RDI),%RSI

0x40b544 CALL	40e3d0 <addIntParallel>

0x40b549 MOV	$0xa,%EDI

0x40b54e CALL	40eaa0 <profileStop>

0x40b553 MOV	-0x98(%RBP),%R10D

0x40b55a MOV	-0x74(%RBP),%R9D

0x40b55e IMUL	%R12D,%R10D

0x40b562 MOV	0x20(%R15),%RBX

0x40b566 IMUL	%R9D,%R10D

0x40b56a SAL	$0x2,%R10D

0x40b56e CMP	%R10D,0x4(%RBX)

0x40b572 JNE	40b583

0x40b574 ADD	$0x78,%RSP

0x40b578 POP	%RBX

0x40b579 POP	%R12

0x40b57b POP	%R13

0x40b57d POP	%R14

0x40b57f POP	%R15

0x40b581 POP	%RBP

0x40b582 RET

0x40b583 MOV	$0x412de0,%ECX

0x40b588 MOV	$0x6c,%EDX

0x40b58d MOV	$0x412d58,%ESI

0x40b592 MOV	$0x412db8,%EDI

0x40b597 CALL	4030c0 <__assert_fail@plt>

0x40b59c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:199	exec
○	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	initAtoms.c:67-109
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:67-68,80-109.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.00 to 15.50 cycles (1.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 18.00 to 2.12 cycles (8.47x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:108
addIntParallel: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:105
profileStart: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:104
profileStop: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:106

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTSD2SI: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88
VRNDSCALESD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

6: multiply
1: divide

The binary function is loading 112 bytes (14 double precision FP elements). The binary function is storing 36 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	89
nb uops	105
loop length	390
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.50 cycles
front end	17.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.00	18.00	7.67	7.67	9.50	5.60	5.80	9.50	9.50	9.50	5.60	7.67
cycles	18.00	18.00	7.67	7.67	9.50	5.60	5.80	9.50	9.50	9.50	5.60	7.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	17.50
Dispatch	18.00
DIV/SQRT	4.00
Overall L1	18.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	6%
load	6%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	14%

INT+FP

all	9%
load	10%
store	6%
mul	10%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

3% of peak load performance is reached (6.22 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40b000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
VMOVAPD %XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %ESI,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x7705(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RCX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVSD %XMM9,%XMM0,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV %EDI,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,-0x74(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMULSD 0x60(%RBX),%XMM2,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0x78(%RBX),%XMM2,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0x68(%RBX),%XMM2,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0x80(%RBX),%XMM2,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0x70(%RBX),%XMM2,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM1,%XMM1,%XMM3	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VRNDSCALESD $0xa,%XMM4,%XMM4,%XMM5	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM3,%R13D	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM5,%EAX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VRNDSCALESD $0x9,%XMM6,%XMM6,%XMM7	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VRNDSCALESD $0xa,%XMM8,%XMM8,%XMM10	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMULSD 0x88(%RBX),%XMM2,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VCVTTSD2SI %XMM7,%R10D	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM10,%R9D	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
MOV %EAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 40b52d <createFccLattice+0x52d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40b52d <createFccLattice+0x52d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R12D,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
VRNDSCALESD $0x9,%XMM11,%XMM11,%XMM13	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM13,%ESI	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
ADD %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
IMUL %R12D,%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %ESI,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R10D,-0x94(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9D,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R12D,-0x9c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x3(,%RSI,4),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VRNDSCALESD $0xa,%XMM12,%XMM12,%XMM14	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVSD 0x7df5(%RIP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCVTTSD2SI %XMM14,%R14D	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VMOVSD 0x7de0(%RIP),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EDI,-0x8c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R8D,-0x7c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VXORPS %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %ECX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV -0x9c(%RBP),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0xa,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 40ea60 <profileStart>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x20(%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x4(%RDI),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 40e3d0 <addIntParallel>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0xa,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 40eaa0 <profileStop>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x98(%RBP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x74(%RBP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
IMUL %R12D,%R10D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
MOV 0x20(%R15),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9D,%R10D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
SAL $0x2,%R10D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
CMP %R10D,0x4(%RBX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JNE 40b583 <createFccLattice+0x583>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV $0x412de0,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x6c,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x412d58,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x412db8,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	initAtoms.c:67-109
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:67-68,80-109.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:108
addIntParallel: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:105
profileStart: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:104
profileStop: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:106

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTSD2SI: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88
VRNDSCALESD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:82
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:83
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:88

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

6: multiply
1: divide

The binary function is loading 112 bytes (14 double precision FP elements). The binary function is storing 36 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	89
nb uops	105
loop length	390
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.50 cycles
front end	17.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.00	18.00	7.67	7.67	9.50	5.60	5.80	9.50	9.50	9.50	5.60	7.67
cycles	18.00	18.00	7.67	7.67	9.50	5.60	5.80	9.50	9.50	9.50	5.60	7.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	17.50
Dispatch	18.00
DIV/SQRT	4.00
Overall L1	18.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	6%
load	6%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	14%

INT+FP

all	9%
load	10%
store	6%
mul	10%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

3% of peak load performance is reached (6.22 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40b000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
VMOVAPD %XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %ESI,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x7705(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RCX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVSD %XMM9,%XMM0,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV %EDI,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,-0x74(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMULSD 0x60(%RBX),%XMM2,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0x78(%RBX),%XMM2,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0x68(%RBX),%XMM2,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0x80(%RBX),%XMM2,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD 0x70(%RBX),%XMM2,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM1,%XMM1,%XMM3	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VRNDSCALESD $0xa,%XMM4,%XMM4,%XMM5	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM3,%R13D	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM5,%EAX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VRNDSCALESD $0x9,%XMM6,%XMM6,%XMM7	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VRNDSCALESD $0xa,%XMM8,%XMM8,%XMM10	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMULSD 0x88(%RBX),%XMM2,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VCVTTSD2SI %XMM7,%R10D	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VCVTTSD2SI %XMM10,%R9D	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
MOV %EAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 40b52d <createFccLattice+0x52d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40b52d <createFccLattice+0x52d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R12D,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
VRNDSCALESD $0x9,%XMM11,%XMM11,%XMM13	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM13,%ESI	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
ADD %R10D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
IMUL %R12D,%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %ESI,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R10D,-0x94(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9D,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R12D,-0x9c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x3(,%RSI,4),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VRNDSCALESD $0xa,%XMM12,%XMM12,%XMM14	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VMOVSD 0x7df5(%RIP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCVTTSD2SI %XMM14,%R14D	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
VMOVSD 0x7de0(%RIP),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EDI,-0x8c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R8D,-0x7c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VXORPS %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %ECX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV -0x9c(%RBP),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0xa,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 40ea60 <profileStart>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x20(%R15),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x4(%RDI),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 40e3d0 <addIntParallel>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0xa,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 40eaa0 <profileStop>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x98(%RBP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x74(%RBP),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
IMUL %R12D,%R10D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
MOV 0x20(%R15),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9D,%R10D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
SAL $0x2,%R10D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
CMP %R10D,0x4(%RBX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JNE 40b583 <createFccLattice+0x583>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV $0x412de0,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x6c,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x412d58,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x412db8,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼createFccLattice–	0.01	0.00
▼Loop 73 - initAtoms.c:88-100 - exec–	0.00	0.00
▼Loop 75 - initAtoms.c:89-100 - exec–	0.00	0.00
○Loop 74 - initAtoms.c:90-100 - exec	0.01	0.02

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code