OV - exec - Function initAtoms

	Function: initAtoms	Module: exec	Source: initAtoms.c:24-50 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h: 13 - 13

--------------------------------------------------------------------------------

13:    return malloc(iSize);

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 22 - 22

--------------------------------------------------------------------------------

22:    a[0] = 0.0;

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 24 - 50

--------------------------------------------------------------------------------

24: {

25:    Atoms* atoms = comdMalloc(sizeof(Atoms));

26:

27:    int maxTotalAtoms = MAXATOMS*boxes->nTotalBoxes;

28:

29:    atoms->gid =      (int*)   comdMalloc(maxTotalAtoms*sizeof(int));

30:    atoms->iSpecies = (int*)   comdMalloc(maxTotalAtoms*sizeof(int));

31:    atoms->r =        (real3*) comdMalloc(maxTotalAtoms*sizeof(real3));

32:    atoms->p =        (real3*) comdMalloc(maxTotalAtoms*sizeof(real3));

33:    atoms->f =        (real3*) comdMalloc(maxTotalAtoms*sizeof(real3));

34:    atoms->U =        (real_t*)comdMalloc(maxTotalAtoms*sizeof(real_t));

35:

36:    atoms->nLocal = 0;

37:    atoms->nGlobal = 0;

38:

39:    for (int iOff = 0; iOff < maxTotalAtoms; iOff++)

40:    {

41:       atoms->gid[iOff] = 0;

42:       atoms->iSpecies[iOff] = 0;

43:       zeroReal3(atoms->r[iOff]);

44:       zeroReal3(atoms->p[iOff]);

45:       zeroReal3(atoms->f[iOff]);

46:       atoms->U[iOff] = 0.;

47:    }

48:

49:    return atoms;

50: }

0x40ad50 PUSH	%RBP

0x40ad51 MOV	%RSP,%RBP

0x40ad54 PUSH	%R15

0x40ad56 PUSH	%R14

0x40ad58 PUSH	%R13

0x40ad5a PUSH	%R12

0x40ad5c MOV	%RDI,%R12

0x40ad5f MOV	$0x38,%EDI

0x40ad64 PUSH	%RBX

0x40ad65 SUB	$0x28,%RSP

0x40ad69 CALL	4030f0 <malloc@plt>

0x40ad6e MOV	0x14(%R12),%ESI

0x40ad73 MOV	%RAX,%RBX

0x40ad76 SAL	$0x6,%ESI

0x40ad79 MOVSXD	%ESI,%R14

0x40ad7c LEA	(,%R14,4),%R15

0x40ad84 MOV	%R15,%RDI

0x40ad87 MOV	%ESI,0x1c(%RSP)

0x40ad8b CALL	4030f0 <malloc@plt>

0x40ad90 MOV	%RAX,0x8(%RBX)

0x40ad94 MOV	%R15,%RDI

0x40ad97 MOV	%RAX,%R13

0x40ad9a CALL	4030f0 <malloc@plt>

0x40ad9f MOV	%RAX,0x10(%RBX)

0x40ada3 LEA	(%R14,%R14,2),%R15

0x40ada7 SAL	$0x3,%R15

0x40adab MOV	%R15,%RDI

0x40adae MOV	%RAX,%R12

0x40adb1 CALL	4030f0 <malloc@plt>

0x40adb6 MOV	%RAX,0x18(%RBX)

0x40adba MOV	%R15,%RDI

0x40adbd MOV	%RAX,0x8(%RSP)

0x40adc2 CALL	4030f0 <malloc@plt>

0x40adc7 MOV	%RAX,0x20(%RBX)

0x40adcb MOV	%R15,%RDI

0x40adce MOV	%RAX,0x10(%RSP)

0x40add3 CALL	4030f0 <malloc@plt>

0x40add8 MOV	%RAX,0x28(%RBX)

0x40addc LEA	(,%R14,8),%RDI

0x40ade4 MOV	%RAX,%R15

0x40ade7 CALL	4030f0 <malloc@plt>

0x40adec MOV	0x1c(%RSP),%EDI

0x40adf0 MOV	%RAX,0x30(%RBX)

0x40adf4 MOVQ	$0,(%RBX)

0x40adfb TEST	%EDI,%EDI

0x40adfd JLE	40af7b

0x40ae03 SHR	$0x3,%EDI

0x40ae06 MOV	%EDI,%R11D

0x40ae09 MOV	0x10(%RSP),%RCX

0x40ae0e MOV	0x8(%RSP),%RDX

0x40ae13 MOV	%RAX,%R10

0x40ae16 SAL	$0x5,%R11

0x40ae1a XOR	%EAX,%EAX

0x40ae1c VPXOR	%XMM1,%XMM1,%XMM1

0x40ae20 VXORPD	%XMM0,%XMM0,%XMM0

(72) 0x40ae24 LEA	0x20(%RAX),%R8

(72) 0x40ae28 VMOVDQU	%YMM1,(%R13,%RAX,1)

(72) 0x40ae2f VMOVDQU	%YMM1,(%R12,%RAX,1)

(72) 0x40ae35 VMOVUPD	%YMM0,(%R10,%RAX,2)

(72) 0x40ae3b VMOVUPD	%YMM0,0x20(%R10,%RAX,2)

(72) 0x40ae42 VMOVDQU	%YMM1,0x20(%R13,%RAX,1)

(72) 0x40ae49 VMOVDQU	%YMM1,0x20(%R12,%RAX,1)

(72) 0x40ae50 ADD	$0x40,%RAX

(72) 0x40ae54 VMOVUPD	%YMM0,(%RDX)

(72) 0x40ae58 VMOVUPD	%YMM0,0x20(%RDX)

(72) 0x40ae5d VMOVUPD	%YMM0,0x40(%RDX)

(72) 0x40ae62 VMOVUPD	%YMM0,0x60(%RDX)

(72) 0x40ae67 VMOVUPD	%YMM0,0x80(%RDX)

(72) 0x40ae6f VMOVUPD	%YMM0,0xa0(%RDX)

(72) 0x40ae77 VMOVUPD	%YMM0,(%RCX)

(72) 0x40ae7b VMOVUPD	%YMM0,0x20(%RCX)

(72) 0x40ae80 VMOVUPD	%YMM0,0x40(%RCX)

(72) 0x40ae85 VMOVUPD	%YMM0,0x60(%RCX)

(72) 0x40ae8a VMOVUPD	%YMM0,0x80(%RCX)

(72) 0x40ae92 VMOVUPD	%YMM0,0xa0(%RCX)

(72) 0x40ae9a VMOVUPD	%YMM0,(%R15)

(72) 0x40ae9f VMOVUPD	%YMM0,0x20(%R15)

(72) 0x40aea5 VMOVUPD	%YMM0,0x40(%R15)

(72) 0x40aeab VMOVUPD	%YMM0,0x60(%R15)

(72) 0x40aeb1 VMOVUPD	%YMM0,0x80(%R15)

(72) 0x40aeba VMOVUPD	%YMM0,0xa0(%R15)

(72) 0x40aec3 VMOVUPD	%YMM0,0xc0(%RDX)

(72) 0x40aecb VMOVUPD	%YMM0,0xe0(%RDX)

(72) 0x40aed3 VMOVUPD	%YMM0,0x100(%RDX)

(72) 0x40aedb VMOVUPD	%YMM0,0x120(%RDX)

(72) 0x40aee3 VMOVUPD	%YMM0,0x140(%RDX)

(72) 0x40aeeb VMOVUPD	%YMM0,0x160(%RDX)

(72) 0x40aef3 VMOVUPD	%YMM0,0xc0(%RCX)

(72) 0x40aefb VMOVUPD	%YMM0,0xe0(%RCX)

(72) 0x40af03 ADD	$0x180,%R15

(72) 0x40af0a VMOVUPD	%YMM0,0x100(%RCX)

(72) 0x40af12 ADD	$0x180,%RDX

(72) 0x40af19 VMOVUPD	%YMM0,0x120(%RCX)

(72) 0x40af21 VMOVUPD	%YMM0,0x140(%RCX)

(72) 0x40af29 VMOVUPD	%YMM0,0x160(%RCX)

(72) 0x40af31 VMOVUPD	%YMM0,-0xc0(%R15)

(72) 0x40af3a VMOVUPD	%YMM0,-0xa0(%R15)

(72) 0x40af43 VMOVUPD	%YMM0,-0x80(%R15)

(72) 0x40af49 VMOVUPD	%YMM0,-0x60(%R15)

(72) 0x40af4f VMOVUPD	%YMM0,-0x40(%R15)

(72) 0x40af55 VMOVUPD	%YMM0,-0x20(%R15)

(72) 0x40af5b VMOVUPD	%YMM0,(%R10,%R8,2)

(72) 0x40af61 VMOVUPD	%YMM0,0x20(%R10,%R8,2)

(72) 0x40af68 ADD	$0x180,%RCX

(72) 0x40af6f CMP	%R11,%RAX

(72) 0x40af72 JNE	40ae24

0x40af78 VZEROUPPER

0x40af7b ADD	$0x28,%RSP

0x40af7f MOV	%RBX,%RAX

0x40af82 POP	%RBX

0x40af83 POP	%R12

0x40af85 POP	%R13

0x40af87 POP	%R14

0x40af89 POP	%R15

0x40af8b POP	%RBP

0x40af8c RET

0x40af8d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	initAtoms.c:24-50
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:24-50

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.33 to 1.33 cycles (9.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.33 to 0.97 cycles (12.73x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

malloc@plt: 7 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:39

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	66
nb uops	74
loop length	236
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.33 cycles
front end	12.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.00	1.13	3.67	3.67	11.50	0.93	3.00	11.50	11.50	11.50	0.93	3.67
cycles	3.00	1.13	3.67	3.67	11.50	0.93	3.00	11.50	11.50	11.50	0.93	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.33
Dispatch	11.50
Overall L1	12.33

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	9%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

INT

all	11%
load	9%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	9%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.33 cycles. At this rate:

1% of peak load performance is reached (1.95 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.16 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.33 to 11.50 cycles (1.07x speedup).

ASM code

In the binary file, the address of the function is: 40ad50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x38,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x14(%R12),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
MOVSXD %ESI,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (,%R14,4),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R14,%R14,2),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x20(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x28(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R14,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x1c(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RAX,0x30(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %EDI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40af7b <initAtoms+0x22b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SHR $0x3,%EDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
MOV %EDI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x10(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x5,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	initAtoms.c:24-50
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22
/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:24-50

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.33 to 1.33 cycles (9.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

malloc@plt: 7 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:39

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	66
nb uops	74
loop length	236
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.33 cycles
front end	12.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.00	1.13	3.67	3.67	11.50	0.93	3.00	11.50	11.50	11.50	0.93	3.67
cycles	3.00	1.13	3.67	3.67	11.50	0.93	3.00	11.50	11.50	11.50	0.93	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.33
Dispatch	11.50
Overall L1	12.33

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	9%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

INT

all	11%
load	9%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	9%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.33 cycles. At this rate:

1% of peak load performance is reached (1.95 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.16 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40ad50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x38,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x14(%R12),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
MOVSXD %ESI,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (,%R14,4),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R14,%R14,2),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x20(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,0x28(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R14,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4030f0 <malloc@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x1c(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RAX,0x30(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %EDI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40af7b <initAtoms+0x22b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SHR $0x3,%EDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
MOV %EDI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x10(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x5,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼initAtoms–	0.01	0.00
○Loop 72 - initAtoms.c:39-46 - exec	0.01	0.02

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code