	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/icx/oneview_results_1786614442 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/icx/oneview_results_1786614442


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/run/base_runs/defaults/icx/exec
  Timestamp:			2026-08-13 11:47:22
  Universal Timestamp:		1786614442
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			gmz12.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		ZEN_V5
  Model Name:			AMD EPYC 9655 96-Core Processor
  Cache Size:			1024 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.29.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Jul 23 16:18:48 EDT 2026
  Compilation Options:		
		exec: Intel(R) Fortran 26.0-1156 
  Number of processes observed:	8
  Number of threads observed:	192
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				40.18 s
  Max (Thread Active Time):		39.88 s
  Average Active Time:			39.76 s
  Activity Ratio:			99.9 %
  Average number of active threads:	189.979
  Affinity Stability:			99.9 %
  Time spent in analyzed loops:		96.4 %
  Time spent in analyzed innermost loops: 96.3 %
  Time spent in user code:		96.4 %
  Compilation Options Score:		16.67
  Array Access Efficiency:		90.7 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.02
  Perfect OpenMP/MPI/Pthread/TBB:	1.01
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.03
  If No Scalar Integer:
      Potential Speedup:		1.01
      Nb Loops to get 80%:		2
  If FP Vectorized:
      Potential Speedup:		1.32
      Nb Loops to get 80%:		13
  If Fully Vectorized:
      Potential Speedup:		2.00
      Nb Loops to get 80%:		23
  If Only FP Arithmetic:
      Potential Speedup:		1.12
      Nb Loops to get 80%:		6




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 9      | 18     | 26     | 36     | 
      Cumulated Speedup | 1.0037 | 1.0055 | 1.0055 | 1.0055 | 1.0055 | 
  Top 5 loops:
    exec - 61:	1.0037
    exec - 123:	1.0046
    exec - 114:	1.0052
    exec - 74:	1.0055
    exec - 189:	1.0055

  If FP Vectorized:
      Number of loops   | 1      | 9      | 18     | 26     | 36     | 
      Cumulated Speedup | 1.0273 | 1.2100 | 1.3112 | 1.3210 | 1.3210 | 
  Top 5 loops:
    exec - 868:	1.0273
    exec - 234:	1.0555
    exec - 111:	1.0784
    exec - 121:	1.1024
    exec - 58:	1.1261

  If Fully Vectorized:
      Number of loops   | 1      | 9      | 18     | 26     | 36     | 
      Cumulated Speedup | 1.0326 | 1.3016 | 1.6246 | 1.9031 | 2.0037 | 
  Top 5 loops:
    exec - 61:	1.0326
    exec - 114:	1.0642
    exec - 58:	1.0952
    exec - 868:	1.128
    exec - 234:	1.1621

  If Only FP Arithmetic:
      Number of loops   | 1      | 9      | 18     | 26     | 36     | 
      Cumulated Speedup | 1.0218 | 1.1098 | 1.1160 | 1.1160 | 1.1160 | 
  Top 5 loops:
    exec - 83:	1.0218
    exec - 74:	1.0429
    exec - 123:	1.0629
    exec - 114:	1.082
    exec - 131:	1.0878



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (39.88 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [0 / 3] Architecture specific options are unknown for some functions (compilation options info are not available)
Architecture specific options are needed to produce efficient code for a specific processor ( -march=(target) ).
Architecture specific options are needed to produce efficient code for a specific processor ( -x(target), -ax(target)
or -march=(target)).

  [0 / 3] Most of time spent in analyzed modules comes from functions without compilation options informations
Functions without compilation options information cumulate 96.58% of the time spent in analyzed modules. For exec,
check that both -g and -grecord-gcc-switches are present. Remark: if such options are indeed used, this can also be
due to some compiler built-in functions (typically math) or statically linked libraries. This warning can be ignored
in that case.

  [0 / 3] Optimization level is unknown for some functions (compilation options info are not available)
To have better performances, it is advised to help the compiler by using a proper optimization level (-O2 of higher).
Warning, depending on compilers, faster optimization levels can decrease numeric accuracy.

  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.01 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (96.36%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 98.95% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.94% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (6.31%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (96.27%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.91%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [3 / 3] Functions mostly use all threads
Functions running on a reduced number of threads (typically sequential code) cover less than 10% of application
walltime (2.87%)

  [3 / 3] Cumulative Outermost/In between loops coverage (0.09%) lower than cumulative innermost loop coverage (96.27%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 61  :
     analysis: Execution Time: 6 % - Vectorization Ratio: 100.00 % - Vector Length Use: 50.00 %
     Loop Computation Issues: 8
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
     Data Access Issues: 2
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.

   + exec - 58  :
     analysis: Execution Time: 5 % - Vectorization Ratio: 100.00 % - Vector Length Use: 50.00 %
     Loop Computation Issues: 8
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.

   + exec - 868 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 95.96 % - Vector Length Use: 47.98 %
     Loop Computation Issues: 24
        [24] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 6
            issues (= instructions) costing 4 points each.
     Control Flow Issues: 2
        [2] [SA] Several paths (2 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 2 issues ( = paths) costing 1 point each.
     Data Access Issues: 8
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [6] [SA] Presence of special instructions executing on a single port (BLEND/MERGE, BROADCAST) - Simplify data
            access and try to get stride 1 access. There are 6 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 4
        [2] [SA] Several paths (2 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 2 issues ( = paths) costing 1 point each.
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
     Inefficient Vectorization: 8
        [6] [SA] Presence of special instructions executing on a single port (BLEND/MERGE, BROADCAST) - Simplify data
            access and try to get stride 1 access. There are 6 issues (= instructions) costing 1 point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.

   + exec - 234 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 100.00 % - Vector Length Use: 50.00 %
     Loop Computation Issues: 12
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.

   + exec - 67  :
     analysis: Execution Time: 5 % - Vectorization Ratio: 100.00 % - Vector Length Use: 50.00 %
     Loop Computation Issues: 4
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 96.38  | 0.38    | 0.01    | 0.20   | 0.00   | 0.03  | 0.00  | 2.99  | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 3                         | 65.61                     | 65.61                     |
   4% to 8%                   | 5                         | 24.51                     | 90.13                     |
   2% to 4%                   | 3                         | 8.66                      | 98.79                     |
   1% to 2%                   | 0                         | 0.00                      | 98.79                     |
   0.5% to 1%                 | 0                         | 0.00                      | 98.79                     |
   0.25% to 0.5%              | 2                         | 0.66                      | 99.45                     |
   0.125% to 0.25%            | 1                         | 0.20                      | 99.65                     |
   < 0.125%                   | 121                       | 0.35                      | 100.00                    |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 0                         | 0.00                      | 0.00                      |
   4% to 8%                   | 10                        | 47.81                     | 47.81                     |
   2% to 4%                   | 14                        | 40.27                     | 88.08                     |
   1% to 2%                   | 6                         | 7.76                      | 95.84                     |
   0.5% to 1%                 | 0                         | 0.00                      | 95.84                     |
   0.25% to 0.5%              | 1                         | 0.29                      | 96.13                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 96.13                     |
   < 0.125%                   | 75                        | 0.14                      | 96.27                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.P... | exec                | 35.50          | 14.12          |
   advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.... | exec                | 18.48          | 7.35           |
   pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2    | exec                | 11.64          | 4.63           |
   viscosity_kernel_module_mp_viscosity_kernel_.DIR.OM... | exec                | 5.31           | 2.11           |
   ideal_gas_kernel_module_mp_ideal_gas_kernel_.DIR.OM... | exec                | 5.20           | 2.07           |
   accelerate_kernel_module_mp_accelerate_kernel_.DIR.... | exec                | 5.02           | 2.00           |
   reset_field_kernel_module_mp_reset_field_kernel_.DI... | exec                | 4.96           | 1.97           |
   flux_calc_kernel_module_mp_flux_calc_kernel_.DIR.OM... | exec                | 4.02           | 1.60           |
   calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PA... | exec                | 3.34           | 1.33           |
   kmp_flag_64<false, true>::wait(kmp_info*, int, void*)  | libiomp5.so         | 2.88           | 1.14           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   61             | exec                | PdV_kernel.f90:111-123,PdV_kernel.f90:131-135          | 6.31           |
   58             | exec                | PdV_kernel.f90:75-87,PdV_kernel.f90:95-99              | 5.32           |
   868            | exec                | viscosity_kernel.f90:55-89                             | 5.31           |
   234            | exec                | ideal_gas_kernel.f90:49-55                             | 5.20           |
   67             | exec                | accelerate_kernel.f90:62-76                            | 5.01           |
   114            | exec                | advec_mom_kernel.f90:151-152,advec_mom_kernel.f90:1... | 4.41           |
   123            | exec                | advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:2... | 4.17           |
   111            | exec                | advec_mom_kernel.f90:183-184                           | 4.03           |
   121            | exec                | advec_mom_kernel.f90:247-248                           | 4.03           |
   182            | exec                | flux_calc_kernel.f90:56-60                             | 4.02           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 61 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:111-123,131-135.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

29% of peak computational performance is used (14.12 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 8.50 to 8.00 cycles (1.06x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
 - For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop



      6.1.1.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.1.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.1.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.1.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 12 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

27 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.1.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 120 FP arithmetical operations:
 - 72: addition or subtraction (12 inside FMA instructions)
 - 40: multiply (12 inside FMA instructions)
 - 8: divide
The binary loop is loading 856 bytes (107 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.1.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.







      6.1.2  -  Loop 58 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:75-87,95-99.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

22% of peak computational performance is used (11.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.2.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 8.00 to 6.00 cycles (1.33x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.2.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.2.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 8.00 to 5.50 cycles (1.45x speedup).


      6.1.2.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 12 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.2.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

19 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.2.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 88 FP arithmetical operations:
 - 40: addition or subtraction (12 inside FMA instructions)
 - 40: multiply (12 inside FMA instructions)
 - 8: divide
The binary loop is loading 568 bytes (71 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.2.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.







      6.1.3  -  Loop 868 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:55-89.

It is main loop of related source loop which is unrolled by 4 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)


      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

16% of peak computational performance is used (8.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
Only 47% of vector register length is used (average across all SSE/AVX instructions).


Details
95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 84% of SSE/AVX loads are used in vector version.
 - 88% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.3.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 27.50 to 17.50 cycles (1.57x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.3.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.3.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 27.50 to 16.75 cycles (1.64x speedup).


      6.1.3.1.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.3.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 20 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.3.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - KORTESTB: 1 occurrences<<list_path_1_complex_1>>
 - VPBROADCASTQ: 1 occurrences<<list_path_1_complex_2>>



      6.1.3.1.8  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.3.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

58 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.3.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 220 FP arithmetical operations:
 - 88: addition or subtraction (20 inside FMA instructions)
 - 108: multiply (20 inside FMA instructions)
 - 20: divide
 - 4: square root
The binary loop is loading 568 bytes (71 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.3.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.




      6.1.3.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

16% of peak computational performance is used (8.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.2.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
Only 47% of vector register length is used (average across all SSE/AVX instructions).


Details
95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 84% of SSE/AVX loads are used in vector version.
 - 88% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.3.2.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 27.50 to 17.50 cycles (1.57x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.3.2.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.3.2.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 27.50 to 16.75 cycles (1.64x speedup).


      6.1.3.2.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.3.2.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 20 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.3.2.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - KORTESTB: 1 occurrences<<list_path_2_complex_1>>
 - VPBROADCASTQ: 1 occurrences<<list_path_2_complex_2>>



      6.1.3.2.8  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

58 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.3.2.9  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 220 FP arithmetical operations:
 - 88: addition or subtraction (20 inside FMA instructions)
 - 108: multiply (20 inside FMA instructions)
 - 20: divide
 - 4: square root
The binary loop is loading 552 bytes (69 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.3.2.10  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.38 FP operations per loaded or stored byte.







      6.1.4  -  Loop 234 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:49-55.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

5% of peak computational performance is used (2.78 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.4.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 11.50 to 4.00 cycles (2.88x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.4.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.4.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 11.50 to 3.00 cycles (3.83x speedup).




      6.1.4.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.4.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 32 FP arithmetical operations:
 - 24: multiply
 - 4: divide
 - 4: square root
The binary loop is loading 64 bytes (8 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.4.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.







      6.1.5  -  Loop 67 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:62-76.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

36% of peak computational performance is used (17.50 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.5.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 8.00 to 7.00 cycles (1.14x speedup).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.5.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.5.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 8.00 to 7.50 cycles (1.07x speedup).


      6.1.5.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 44 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.5.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

24 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.5.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 140 FP arithmetical operations:
 - 76: addition or subtraction (44 inside FMA instructions)
 - 60: multiply (44 inside FMA instructions)
 - 4: divide
The binary loop is loading 736 bytes (92 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.5.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.


      6.1.5.1.9  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !DIR$ UNROLL_AND_JAM(N), UNROLL_AND_JAM=N, UNROLL(N) or UNROLL=N







      6.1.6  -  Loop 114 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:151-152,158-177.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

7% of peak computational performance is used (3.53 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
Only 40% of vector register length is used (average across all SSE/AVX instructions).


Details
98% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.6.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.6.1.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.6.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.03x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.6.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VGATHERQPD: 5 occurrences<<list_path_1_complex_1>>
 - VPBROADCASTD: 1 occurrences<<list_path_1_complex_2>>



      6.1.6.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 3 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.6.1.8  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 19.25 to 12.00 cycles (1.60x speedup).

Details
 - VGATHERQPD: 5 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.6.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

20 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.6.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 68 FP arithmetical operations:
 - 28: addition or subtraction (8 inside FMA instructions)
 - 28: multiply (8 inside FMA instructions)
 - 12: divide
The binary loop is loading 224 bytes (28 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.6.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.







      6.1.7  -  Loop 123 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215,227-241.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)


      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

6% of peak computational performance is used (3.11 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
Only 40% of vector register length is used (average across all SSE/AVX instructions).


Details
91% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 85% of SSE/AVX loads are used in vector version.
 - 88% of SSE/AVX multiply instructions are used in vector version.
 - 66% of SSE/AVX divide and square root instructions are used in vector version.
 - 91% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.7.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.7.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.7.1.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.7.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 12 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.02x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.7.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - KORTESTB: 1 occurrences<<list_path_1_complex_1>>
 - VGATHERQPD: 5 occurrences<<list_path_1_complex_2>>
 - VPBROADCASTQ: 1 occurrences<<list_path_1_complex_3>>



      6.1.7.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.7.1.8  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 21.25 to 14.25 cycles (1.49x speedup).

Details
 - VGATHERQPD: 5 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.7.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
18 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.7.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 66 FP arithmetical operations:
 - 28: addition or subtraction (12 inside FMA instructions)
 - 29: multiply (12 inside FMA instructions)
 - 9: divide
The binary loop is loading 200 bytes (25 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.7.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.




      6.1.7.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

6% of peak computational performance is used (3.14 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.2.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
Only 41% of vector register length is used (average across all SSE/AVX instructions).


Details
92% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 88% of SSE/AVX multiply instructions are used in vector version.
 - 66% of SSE/AVX divide and square root instructions are used in vector version.
 - 91% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.7.2.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.7.2.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.7.2.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.7.2.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 12 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.02x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.7.2.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - KORTESTB: 1 occurrences<<list_path_2_complex_1>>
 - VGATHERQPD: 5 occurrences<<list_path_2_complex_2>>
 - VPBROADCASTQ: 1 occurrences<<list_path_2_complex_3>>



      6.1.7.2.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 5 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.7.2.8  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 21.00 to 14.25 cycles (1.47x speedup).

Details
 - VGATHERQPD: 5 occurrences<<list_path_2_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.7.2.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
18 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.7.2.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 66 FP arithmetical operations:
 - 28: addition or subtraction (12 inside FMA instructions)
 - 29: multiply (12 inside FMA instructions)
 - 9: divide
The binary loop is loading 192 bytes (24 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.7.2.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.







      6.1.8  -  Loop 111 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:183-184.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (4.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.8.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 1.50 cycles (2.67x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.8.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.8.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.25 cycles (3.20x speedup).


      6.1.8.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.




      6.1.8.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.8.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 16 FP arithmetical operations:
 - 8: addition or subtraction (4 inside FMA instructions)
 - 4: multiply (all inside FMA instructions)
 - 4: divide
The binary loop is loading 160 bytes (20 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.8.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.9  -  Loop 121 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:247-248.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (4.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.9.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 1.50 cycles (2.67x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.9.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.9.1.4  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.25 cycles (3.20x speedup).


      6.1.9.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.




      6.1.9.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.9.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 16 FP arithmetical operations:
 - 8: addition or subtraction (4 inside FMA instructions)
 - 4: multiply (all inside FMA instructions)
 - 4: divide
The binary loop is loading 160 bytes (20 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.9.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.10  -  Loop 182 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:56-60.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

27% of peak computational performance is used (13.33 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.10.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - execution of FP add operations (the FP add unit is a bottleneck)
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).


Workaround
 - Reduce the number of FP add instructions
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.10.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -qopt-zmm-usage=high


      6.1.10.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use axHost or xHost
 - Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).





      6.1.10.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

10 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.10.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 40 FP arithmetical operations:
 - 24: addition or subtraction
 - 16: multiply
The binary loop is loading 320 bytes (40 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.10.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.


      6.1.10.1.8  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !DIR$ UNROLL_AND_JAM(N), UNROLL_AND_JAM=N, UNROLL(N) or UNROLL=N





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4072/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/icx/oneview_run_1786614442"
[MAQAO] Info: 
