OV - exec - Loop 830

	Loop Id: 830	Module: exec	Source: viscosity_kernel.f90:56-89	Coverage: 3.89%

0x47dbc0 VMOVUPD	(%RCX,%RAX,1),%ZMM22    [13]

0x47dbc7 VMOVUPD	(%R10,%RAX,1),%ZMM7    [1]

0x47dbce VMOVUPD	(%R9,%RAX,1),%ZMM5    [10]

0x47dbd5 VMOVUPD	(%R8,%RAX,1),%ZMM2    [15]

0x47dbdc VMOVUPD	(%R12,%RAX,1),%ZMM6    [14]

0x47dbe3 VMOVUPD	(%RBX,%RAX,1),%ZMM3    [9]

0x47dbea VMOVUPD	(%RDI,%RAX,1),%ZMM18    [18]

0x47dbf1 VMOVQ	%XMM30,%RDX

0x47dbf7 VADDPD	%ZMM5,%ZMM7,%ZMM23

0x47dbfd VADDPD	%ZMM7,%ZMM22,%ZMM4

0x47dc03 VMOVUPD	(%R15,%RAX,1),%ZMM7    [16]

0x47dc0a VADDPD	%ZMM5,%ZMM2,%ZMM0

0x47dc10 VMOVUPD	(%R13,%RAX,1),%ZMM5    [3]

0x47dc18 VADDPD	%ZMM2,%ZMM22,%ZMM2

0x47dc1e VSUBPD	%ZMM0,%ZMM4,%ZMM21

0x47dc24 VADDPD	%ZMM3,%ZMM5,%ZMM4

0x47dc2a VADDPD	%ZMM5,%ZMM7,%ZMM0

0x47dc30 VADDPD	%ZMM6,%ZMM7,%ZMM7

0x47dc36 VADDPD	%ZMM3,%ZMM6,%ZMM5

0x47dc3c VSUBPD	%ZMM2,%ZMM23,%ZMM3

0x47dc42 VSUBPD	%ZMM7,%ZMM4,%ZMM6

0x47dc48 VSUBPD	%ZMM5,%ZMM0,%ZMM25

0x47dc4e VMOVSD	(%RSI,%R14,8),%XMM5    [4]

0x47dc54 VBROADCASTSD	%XMM5,%ZMM19

0x47dc5a VMULPD	%ZMM10,%ZMM3,%ZMM0

0x47dc60 VADDSD	0x8(%RSI,%R14,8),%XMM5,%XMM5    [4]

0x47dc67 VMULPD	%ZMM10,%ZMM6,%ZMM4

0x47dc6d VMULPD	%ZMM19,%ZMM25,%ZMM20

0x47dc73 VDIVPD	%ZMM19,%ZMM0,%ZMM2

0x47dc79 VMOVUPD	(%RDX,%RAX,1),%ZMM0    [12]

0x47dc80 VMOVQ	%XMM31,%RDX

0x47dc86 VSUBPD	(%RDX,%RAX,1),%ZMM0,%ZMM7    [11]

0x47dc8d VFMADD231PD	%ZMM18,%ZMM21,%ZMM20

0x47dc93 VMOVQ	%XMM27,%RDX

0x47dc99 VBROADCASTSD	%XMM5,%ZMM0

0x47dc9f VADDPD	(%RDX,%RAX,1),%ZMM18,%ZMM6    [8]

0x47dca6 VMOVQ	%XMM28,%RDX

0x47dcac VCMPPD	$0xd,%ZMM8,%ZMM20,%K1

0x47dcb3 VDIVPD	%ZMM18,%ZMM4,%ZMM3

0x47dcb9 VMOVUPD	(%R11,%RAX,1),%ZMM4    [2]

0x47dcc0 VDIVPD	%ZMM6,%ZMM7,%ZMM7

0x47dcc6 VADDPD	%ZMM3,%ZMM2,%ZMM2

0x47dccc VSUBPD	(%RDX,%RAX,1),%ZMM4,%ZMM3    [7]

0x47dcd3 VMULPD	%ZMM10,%ZMM21,%ZMM4

0x47dcd9 MOV	0x200(%RSP),%RDX    [17]

0x47dce1 VDIVPD	%ZMM18,%ZMM4,%ZMM4

0x47dce7 VMULPD	%ZMM7,%ZMM7,%ZMM5

0x47dced VCMPPD	$0xd,%ZMM8,%ZMM7,%K3

0x47dcf4 VDIVPD	%ZMM0,%ZMM3,%ZMM0

0x47dcfa VMULPD	%ZMM10,%ZMM25,%ZMM3

0x47dd00 VDIVPD	%ZMM19,%ZMM3,%ZMM3

0x47dd06 VMULPD	%ZMM0,%ZMM0,%ZMM6

0x47dd0c VMULPD	%ZMM6,%ZMM3,%ZMM3

0x47dd12 VFMADD132PD	%ZMM5,%ZMM3,%ZMM4

0x47dd18 VMULPD	%ZMM0,%ZMM7,%ZMM3

0x47dd1e VADDPD	%ZMM6,%ZMM5,%ZMM5

0x47dd24 VANDPD	%ZMM9,%ZMM0,%ZMM0

0x47dd2a VMAXPD	%ZMM12,%ZMM5,%ZMM6

0x47dd30 VFMADD132PD	%ZMM3,%ZMM4,%ZMM2

0x47dd36 VMAXPD	%ZMM12,%ZMM0,%ZMM3

0x47dd3c VDIVPD	%ZMM6,%ZMM2,%ZMM5

0x47dd42 VANDPD	%ZMM9,%ZMM7,%ZMM2

0x47dd48 VMAXPD	%ZMM12,%ZMM2,%ZMM6

0x47dd4e VCMPPD	$0xe,%ZMM8,%ZMM6,%K2

0x47dd55 VXORPD	%ZMM13,%ZMM6,%ZMM4

0x47dd5b VCMPPD	$0x1,%ZMM8,%ZMM7,%K7{%K2}

0x47dd62 VCMPPD	$0xe,%ZMM8,%ZMM5,%K0

0x47dd69 KORB	%K1,%K0,%K4

0x47dd6d KANDNB	%K7,%K4,%K1

0x47dd71 KANDNB	%K3,%K4,%K6

0x47dd75 VBLENDMPD	%ZMM15,%ZMM14,%ZMM7{%K1}

0x47dd7b VMOVAPD	%ZMM6,%ZMM4{%K6}

0x47dd81 KNOTB	%K4,%K5

0x47dd85 VMOVUPD	(%RDX,%RAX,1),%ZMM11{%K5}    [6]

0x47dd8c VMULPD	%ZMM7,%ZMM3,%ZMM6

0x47dd92 VMOVQ	%XMM29,%RDX

0x47dd98 VMULPD	%ZMM6,%ZMM6,%ZMM2

0x47dd9e VADDPD	%ZMM11,%ZMM11,%ZMM0

0x47dda4 VFMADD231PD	%ZMM4,%ZMM4,%ZMM2

0x47ddaa VSQRTPD	%ZMM2,%ZMM7

0x47ddb0 VMULPD	%ZMM7,%ZMM18,%ZMM26

0x47ddb6 VMULPD	%ZMM7,%ZMM19,%ZMM21

0x47ddbc VDIVPD	%ZMM4,%ZMM26,%ZMM22

0x47ddc2 VDIVPD	%ZMM6,%ZMM21,%ZMM25

0x47ddc8 VANDPD	%ZMM9,%ZMM22,%ZMM23

0x47ddce VANDPD	%ZMM9,%ZMM25,%ZMM18

0x47ddd4 VMINPD	%ZMM18,%ZMM23,%ZMM19

0x47ddda VMULPD	%ZMM19,%ZMM5,%ZMM5

0x47dde0 VMULPD	%ZMM5,%ZMM5,%ZMM4

0x47dde6 VMULPD	%ZMM0,%ZMM4,%ZMM3{%K5}{z}

0x47ddec VMOVUPD	%ZMM3,(%RDX,%RAX,1)    [5]

0x47ddf3 MOV	0x1e0(%RSP),%RDX    [17]

0x47ddfb ADD	$0x40,%RAX

0x47ddff CMP	%RDX,%RAX

0x47de02 JNE	47dbc0

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 56 - 89

--------------------------------------------------------------------------------

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Coverage (%)	Name	Source Location	Module
►99.89+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►86.54+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►12.09+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec
►1.36+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec

Coverage (%)	Name	Source Location	Module
►91.51+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►7.69+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►92.91+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►6.86+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►95.34+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►4.02+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►95.54+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.33+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.41
Bottlenecks	P10, P11,
Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:56-89
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	44.50
CQA cycles if no scalar integer	44.50
CQA cycles if FP arith vectorized	44.50
CQA cycles if fully vectorized	44.50
Front-end cycles	11.75
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	18.50
P11 cycles	18.00
P12 cycles	16.75
P13 cycles	16.75
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	44.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	95.00
Nb uops	94.00
Nb loads	19.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	9.37
Nb FLOP add-sub	145.00
Nb FLOP mul	128.00
Nb FLOP fma	32.00
Nb FLOP div	72.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.73
Bytes prefetched	0.00
Bytes loaded	992.00
Bytes stored	64.00
Stride 0	2.00
Stride 1	16.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	89.53
Vectorization ratio load	88.24
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	94.74
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	69.57
Vector-efficiency ratio all	90.84
Vector-efficiency ratio load	89.71
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.39
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	73.37

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.41
Bottlenecks	P10, P11,
Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:56-89
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	44.50
CQA cycles if no scalar integer	44.50
CQA cycles if FP arith vectorized	44.50
CQA cycles if fully vectorized	44.50
Front-end cycles	11.75
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	18.50
P11 cycles	18.00
P12 cycles	16.75
P13 cycles	16.75
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	44.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	95.00
Nb uops	94.00
Nb loads	19.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	9.37
Nb FLOP add-sub	145.00
Nb FLOP mul	128.00
Nb FLOP fma	32.00
Nb FLOP div	72.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.73
Bytes prefetched	0.00
Bytes loaded	992.00
Bytes stored	64.00
Stride 0	2.00
Stride 1	16.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	89.53
Vectorization ratio load	88.24
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	94.74
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	69.57
Vector-efficiency ratio all	90.84
Vector-efficiency ratio load	89.71
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.39
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	73.37

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:56-89
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56-89.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 90% of vector register length is used (average across all SSE/AVX instructions).

Details

89% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX loads are used in vector version.
94% of SSE/AVX addition or subtraction instructions are used in vector version.
69% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 44.50 to 18.50 cycles (2.41x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 44.50 to 17.50 cycles (2.54x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Vector unaligned load/store instructions

Detected 13 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 13 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:60
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:65
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:66
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:89
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:89

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 57 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 417 FP arithmetical operations:

177: addition or subtraction (32 inside FMA instructions)
160: multiply (32 inside FMA instructions)
72: divide
8: square root

The binary loop is loading 992 bytes (124 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.39 FP operations per loaded or stored byte.

General properties

nb instructions	95
nb uops	94
loop length	584
used x86 registers	15
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	23
nb stack references	2
ADD-SUB / MUL ratio	1.19

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	5.00	5.00	5.00	5.00	18.50	18.00	16.75	16.75	3.00	3.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	5.00	5.00	5.00	5.00	18.50	18.00	16.75	16.75	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	44.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.75
Dispatch	18.50
DIV/SQRT	44.50
Data deps.	1.00
Overall L1	44.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	95%
load	88%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	89%
load	88%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	69%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	95%
load	89%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	90%

INT+FP

all	90%
load	89%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	73%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.50 cycles. At this rate:

8% of peak load performance is reached (22.29 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 47dbc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%RCX,%RAX,1),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R10,%RAX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R9,%RAX,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R8,%RAX,1),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RBX,%RAX,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RDI,%RAX,1),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM30,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDPD %ZMM5,%ZMM7,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM7,%ZMM22,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R15,%RAX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM5,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R13,%RAX,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM22,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM0,%ZMM4,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM5,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM5,%ZMM7,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM6,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM6,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM2,%ZMM23,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM7,%ZMM4,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM0,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVSD (%RSI,%R14,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM5,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMULPD %ZMM10,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDSD 0x8(%RSI,%R14,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULPD %ZMM10,%ZMM6,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM25,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM19,%ZMM0,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMOVUPD (%RDX,%RAX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM31,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VSUBPD (%RDX,%RAX,1),%ZMM0,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD %ZMM18,%ZMM21,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVQ %XMM27,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM5,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VADDPD (%RDX,%RAX,1),%ZMM18,%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVQ %XMM28,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VCMPPD $0xd,%ZMM8,%ZMM20,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
VDIVPD %ZMM18,%ZMM4,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMOVUPD (%R11,%RAX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM6,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VADDPD %ZMM3,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD (%RDX,%RAX,1),%ZMM4,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM10,%ZMM21,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x200(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VDIVPD %ZMM18,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMULPD %ZMM7,%ZMM7,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0xd,%ZMM8,%ZMM7,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
VDIVPD %ZMM0,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMULPD %ZMM10,%ZMM25,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM19,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMULPD %ZMM0,%ZMM0,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM5,%ZMM3,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM7,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM6,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VANDPD %ZMM9,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VMAXPD %ZMM12,%ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD132PD %ZMM3,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMAXPD %ZMM12,%ZMM0,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VDIVPD %ZMM6,%ZMM2,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VANDPD %ZMM9,%ZMM7,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VMAXPD %ZMM12,%ZMM2,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM6,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
VXORPD %ZMM13,%ZMM6,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VCMPPD $0x1,%ZMM8,%ZMM7,%K7{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM5,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
KORB %K1,%K0,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KANDNB %K7,%K4,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KANDNB %K3,%K4,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VBLENDMPD %ZMM15,%ZMM14,%ZMM7{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VMOVAPD %ZMM6,%ZMM4{%K6}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
KNOTB %K4,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMOVUPD (%RDX,%RAX,1),%ZMM11{%K5}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM7,%ZMM3,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM29,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULPD %ZMM6,%ZMM6,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM11,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD %ZMM4,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM2,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMULPD %ZMM7,%ZMM18,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM7,%ZMM19,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM4,%ZMM26,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VDIVPD %ZMM6,%ZMM21,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VANDPD %ZMM9,%ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VANDPD %ZMM9,%ZMM25,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VMINPD %ZMM18,%ZMM23,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM5,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM4,%ZMM3{%K5}{z}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%RDX,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
MOV 0x1e0(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x40,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 47dbc0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x640>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:56-89
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 90% of vector register length is used (average across all SSE/AVX instructions).

Details

89% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX loads are used in vector version.
94% of SSE/AVX addition or subtraction instructions are used in vector version.
69% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 44.50 to 17.50 cycles (2.54x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Vector unaligned load/store instructions

Detected 13 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 13 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:60
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:58
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:65
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:66
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:89
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:89

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 417 FP arithmetical operations:

177: addition or subtraction (32 inside FMA instructions)
160: multiply (32 inside FMA instructions)
72: divide
8: square root

The binary loop is loading 992 bytes (124 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.39 FP operations per loaded or stored byte.

General properties

nb instructions	95
nb uops	94
loop length	584
used x86 registers	15
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	23
nb stack references	2
ADD-SUB / MUL ratio	1.19

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	5.00	5.00	5.00	5.00	18.50	18.00	16.75	16.75	3.00	3.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	5.00	5.00	5.00	5.00	18.50	18.00	16.75	16.75	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	44.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.75
Dispatch	18.50
DIV/SQRT	44.50
Data deps.	1.00
Overall L1	44.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	95%
load	88%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	89%
load	88%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	69%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	95%
load	89%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	90%

INT+FP

all	90%
load	89%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	73%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.50 cycles. At this rate:

8% of peak load performance is reached (22.29 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 47dbc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%RCX,%RAX,1),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R10,%RAX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R9,%RAX,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R8,%RAX,1),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RBX,%RAX,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RDI,%RAX,1),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM30,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDPD %ZMM5,%ZMM7,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM7,%ZMM22,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R15,%RAX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM5,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R13,%RAX,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM22,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM0,%ZMM4,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM5,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM5,%ZMM7,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM6,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM6,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM2,%ZMM23,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM7,%ZMM4,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM0,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVSD (%RSI,%R14,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM5,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMULPD %ZMM10,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDSD 0x8(%RSI,%R14,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULPD %ZMM10,%ZMM6,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM25,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM19,%ZMM0,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMOVUPD (%RDX,%RAX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM31,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VSUBPD (%RDX,%RAX,1),%ZMM0,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD %ZMM18,%ZMM21,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVQ %XMM27,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM5,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VADDPD (%RDX,%RAX,1),%ZMM18,%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVQ %XMM28,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VCMPPD $0xd,%ZMM8,%ZMM20,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
VDIVPD %ZMM18,%ZMM4,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMOVUPD (%R11,%RAX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM6,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VADDPD %ZMM3,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD (%RDX,%RAX,1),%ZMM4,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM10,%ZMM21,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x200(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VDIVPD %ZMM18,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMULPD %ZMM7,%ZMM7,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0xd,%ZMM8,%ZMM7,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
VDIVPD %ZMM0,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMULPD %ZMM10,%ZMM25,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM19,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMULPD %ZMM0,%ZMM0,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM5,%ZMM3,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM7,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM6,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VANDPD %ZMM9,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VMAXPD %ZMM12,%ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD132PD %ZMM3,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMAXPD %ZMM12,%ZMM0,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VDIVPD %ZMM6,%ZMM2,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VANDPD %ZMM9,%ZMM7,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VMAXPD %ZMM12,%ZMM2,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM6,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
VXORPD %ZMM13,%ZMM6,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VCMPPD $0x1,%ZMM8,%ZMM7,%K7{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM8,%ZMM5,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
KORB %K1,%K0,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KANDNB %K7,%K4,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KANDNB %K3,%K4,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VBLENDMPD %ZMM15,%ZMM14,%ZMM7{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VMOVAPD %ZMM6,%ZMM4{%K6}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
KNOTB %K4,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMOVUPD (%RDX,%RAX,1),%ZMM11{%K5}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM7,%ZMM3,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM29,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULPD %ZMM6,%ZMM6,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM11,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD %ZMM4,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM2,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMULPD %ZMM7,%ZMM18,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM7,%ZMM19,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM4,%ZMM26,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VDIVPD %ZMM6,%ZMM21,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VANDPD %ZMM9,%ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VANDPD %ZMM9,%ZMM25,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VMINPD %ZMM18,%ZMM23,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM5,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM4,%ZMM3{%K5}{z}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%RDX,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
MOV 0x1e0(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x40,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 47dbc0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x640>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

▶Scalability Runs Description

Run 8x1	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 1I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x8	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 8I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x12	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 12I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x16	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 16I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x20	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 20I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x24	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 24I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads

(8x1) Efficiency	(8x1) Potential Speed-Up (%)	(8x8) Efficiency	(8x8) Potential Speed-Up (%)	(8x12) Efficiency	(8x12) Potential Speed-Up (%)	(8x16) Efficiency	(8x16) Potential Speed-Up (%)	(8x20) Efficiency	(8x20) Potential Speed-Up (%)	(8x24) Efficiency	(8x24) Potential Speed-Up (%)
1	0	0.5	1.27	0.33	1.81	0.25	1.91	0.2	1.94	0.16	2.3

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
8x1	8	1	1	1	4.0300002098083	3.8936102390289
8x8	64	0.5	4.03	8	1.0799999237061	2.5679883956909
8x12	96	0.33	3.98	12	1.0899999141693	2.7065443992615
8x16	128	0.25	4.04	16	1.1750000715256	2.5491070747375
8x20	160	0.2	4.09	20	1.1649998426437	2.439864397049
8x24	192	0.16	3.92	24	1.1000000238419	2.7528154850006

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency