OV - exec - Loop 121

	Loop Id: 121	Module: exec	Source: advec_mom_kernel.f90:106-107	Coverage: 1.83%

0x423010 VMOVUPD	(%R10,%RAX,1),%ZMM14    [2]

0x423017 VMOVUPD	%ZMM14,(%R15,%RAX,1)    [1]

0x42301e VADDPD	(%RBX,%RAX,1),%ZMM14,%ZMM15    [6]

0x423025 VSUBPD	(%R14,%RAX,1),%ZMM15,%ZMM5    [3]

0x42302c VMOVUPD	%ZMM5,(%R12,%RAX,1)    [4]

0x423033 VMOVUPD	0x40(%R10,%RAX,1),%ZMM1    [2]

0x42303b VMOVUPD	%ZMM1,0x40(%R15,%RAX,1)    [1]

0x423043 VADDPD	0x40(%RBX,%RAX,1),%ZMM1,%ZMM0    [6]

0x42304b VSUBPD	0x40(%R14,%RAX,1),%ZMM0,%ZMM11    [3]

0x423053 VMOVUPD	%ZMM11,0x40(%R12,%RAX,1)    [4]

0x42305b VMOVUPD	0x80(%R10,%RAX,1),%ZMM2    [2]

0x423063 VMOVUPD	%ZMM2,0x80(%R15,%RAX,1)    [1]

0x42306b VADDPD	0x80(%RBX,%RAX,1),%ZMM2,%ZMM12    [6]

0x423073 VSUBPD	0x80(%R14,%RAX,1),%ZMM12,%ZMM13    [3]

0x42307b VMOVUPD	%ZMM13,0x80(%R12,%RAX,1)    [4]

0x423083 VMOVUPD	0xc0(%R10,%RAX,1),%ZMM14    [2]

0x42308b VMOVUPD	%ZMM14,0xc0(%R15,%RAX,1)    [1]

0x423093 VADDPD	0xc0(%RBX,%RAX,1),%ZMM14,%ZMM15    [6]

0x42309b VSUBPD	0xc0(%R14,%RAX,1),%ZMM15,%ZMM5    [3]

0x4230a3 VMOVUPD	%ZMM5,0xc0(%R12,%RAX,1)    [4]

0x4230ab VMOVUPD	0x100(%R10,%RAX,1),%ZMM1    [2]

0x4230b3 VMOVUPD	%ZMM1,0x100(%R15,%RAX,1)    [1]

0x4230bb VADDPD	0x100(%RBX,%RAX,1),%ZMM1,%ZMM0    [6]

0x4230c3 VSUBPD	0x100(%R14,%RAX,1),%ZMM0,%ZMM11    [3]

0x4230cb VMOVUPD	%ZMM11,0x100(%R12,%RAX,1)    [4]

0x4230d3 VMOVUPD	0x140(%R10,%RAX,1),%ZMM2    [2]

0x4230db VMOVUPD	%ZMM2,0x140(%R15,%RAX,1)    [1]

0x4230e3 VADDPD	0x140(%RBX,%RAX,1),%ZMM2,%ZMM12    [6]

0x4230eb VSUBPD	0x140(%R14,%RAX,1),%ZMM12,%ZMM13    [3]

0x4230f3 VMOVUPD	%ZMM13,0x140(%R12,%RAX,1)    [4]

0x4230fb VMOVUPD	0x180(%R10,%RAX,1),%ZMM14    [2]

0x423103 VMOVUPD	%ZMM14,0x180(%R15,%RAX,1)    [1]

0x42310b VADDPD	0x180(%RBX,%RAX,1),%ZMM14,%ZMM15    [6]

0x423113 MOV	0xe0(%RSP),%RDX    [5]

0x42311b VSUBPD	0x180(%R14,%RAX,1),%ZMM15,%ZMM5    [3]

0x423123 VMOVUPD	%ZMM5,0x180(%R12,%RAX,1)    [4]

0x42312b VMOVUPD	0x1c0(%R10,%RAX,1),%ZMM1    [2]

0x423133 VMOVUPD	%ZMM1,0x1c0(%R15,%RAX,1)    [1]

0x42313b VADDPD	0x1c0(%RBX,%RAX,1),%ZMM1,%ZMM0    [6]

0x423143 VSUBPD	0x1c0(%R14,%RAX,1),%ZMM0,%ZMM11    [3]

0x42314b VMOVUPD	%ZMM11,0x1c0(%R12,%RAX,1)    [4]

0x423153 ADD	$0x200,%RAX

0x423159 CMP	%RDX,%RAX

0x42315c JNE	423010

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 106 - 107

--------------------------------------------------------------------------------

106:           post_vol(j,k)=volume(j,k)

107:           pre_vol(j,k)=post_vol(j,k)+vol_flux_y(j  ,k+1)-vol_flux_y(j,k)

Coverage (%)	Name	Source Location	Module
►50.05+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:107	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec
►49.88+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:105	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►86.58+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►6.00+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:107	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec
►5.93+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:105	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►91.57+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.88+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:105	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec
►3.76+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:107	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►93.16+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.40+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:105	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec
►3.40+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:107	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►95.20+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.08+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:107	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec
►2.06+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:105	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►95.76+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.69+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:107	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec
►1.60+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:105	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P6, P7, P8, P9,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:106-107
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.25
CQA cycles if no scalar integer	10.25
CQA cycles if FP arith vectorized	10.25
CQA cycles if fully vectorized	10.25
Front-end cycles	5.38
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	10.25
P7 cycles	10.25
P8 cycles	10.25
P9 cycles	10.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	8.00
P15 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	43.00
Nb loads	25.00
Nb stores	16.00
Nb stack references	1.00
FLOP/cycle	12.49
Nb FLOP add-sub	128.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	250.54
Bytes prefetched	0.00
Bytes loaded	1544.00
Bytes stored	1024.00
Stride 0	1.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P6, P7, P8, P9,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:106-107
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.25
CQA cycles if no scalar integer	10.25
CQA cycles if FP arith vectorized	10.25
CQA cycles if fully vectorized	10.25
Front-end cycles	5.38
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	10.25
P7 cycles	10.25
P8 cycles	10.25
P9 cycles	10.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	8.00
P15 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	43.00
Nb loads	25.00
Nb stores	16.00
Nb stack references	1.00
FLOP/cycle	12.49
Nb FLOP add-sub	128.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	250.54
Bytes prefetched	0.00
Bytes loaded	1544.00
Bytes stored	1024.00
Stride 0	1.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:106-107
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106-107.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.25 to 8.00 cycles (1.28x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Vector unaligned load/store instructions

Detected 24 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 24 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

16 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

128: addition or subtraction

The binary loop is loading 1544 bytes (193 double precision FP elements). The binary loop is storing 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	44
nb uops	43
loop length	338
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	9
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	10.25	10.25	10.25	10.25	0.00	0.00	8.00	8.00	8.00	8.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	10.25	10.25	10.25	10.25	0.00	0.00	8.00	8.00	8.00	8.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.38
Dispatch	10.25
Data deps.	1.00
Overall L1	10.25

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.25 cycles. At this rate:

58% of peak load performance is reached (150.63 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
78% of peak store performance is reached (99.90 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 423010

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R10,%RAX,1),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM14,(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD (%RBX,%RAX,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD (%R14,%RAX,1),%ZMM15,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM5,(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x40(%R10,%RAX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM1,0x40(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x40(%RBX,%RAX,1),%ZMM1,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0x40(%R14,%RAX,1),%ZMM0,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM11,0x40(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x80(%R10,%RAX,1),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x80(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x80(%RBX,%RAX,1),%ZMM2,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0x80(%R14,%RAX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM13,0x80(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0xc0(%R10,%RAX,1),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM14,0xc0(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0xc0(%RBX,%RAX,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0xc0(%R14,%RAX,1),%ZMM15,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM5,0xc0(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x100(%R10,%RAX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM1,0x100(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x100(%RBX,%RAX,1),%ZMM1,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0x100(%R14,%RAX,1),%ZMM0,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM11,0x100(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x140(%R10,%RAX,1),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x140(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x140(%RBX,%RAX,1),%ZMM2,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0x140(%R14,%RAX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM13,0x140(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x180(%R10,%RAX,1),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM14,0x180(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x180(%RBX,%RAX,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOV 0xe0(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VSUBPD 0x180(%R14,%RAX,1),%ZMM15,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM5,0x180(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM1,0x1c0(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x1c0(%RBX,%RAX,1),%ZMM1,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0x1c0(%R14,%RAX,1),%ZMM0,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM11,0x1c0(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x200,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 423010 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3a80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:106-107
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.25 to 8.00 cycles (1.28x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Vector unaligned load/store instructions

Detected 24 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 24 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:106
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:107

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

16 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

128: addition or subtraction

The binary loop is loading 1544 bytes (193 double precision FP elements). The binary loop is storing 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	44
nb uops	43
loop length	338
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	9
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	10.25	10.25	10.25	10.25	0.00	0.00	8.00	8.00	8.00	8.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	10.25	10.25	10.25	10.25	0.00	0.00	8.00	8.00	8.00	8.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.38
Dispatch	10.25
Data deps.	1.00
Overall L1	10.25

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.25 cycles. At this rate:

58% of peak load performance is reached (150.63 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
78% of peak store performance is reached (99.90 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 423010

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R10,%RAX,1),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM14,(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD (%RBX,%RAX,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD (%R14,%RAX,1),%ZMM15,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM5,(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x40(%R10,%RAX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM1,0x40(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x40(%RBX,%RAX,1),%ZMM1,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0x40(%R14,%RAX,1),%ZMM0,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM11,0x40(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x80(%R10,%RAX,1),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x80(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x80(%RBX,%RAX,1),%ZMM2,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0x80(%R14,%RAX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM13,0x80(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0xc0(%R10,%RAX,1),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM14,0xc0(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0xc0(%RBX,%RAX,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0xc0(%R14,%RAX,1),%ZMM15,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM5,0xc0(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x100(%R10,%RAX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM1,0x100(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x100(%RBX,%RAX,1),%ZMM1,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0x100(%R14,%RAX,1),%ZMM0,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM11,0x100(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x140(%R10,%RAX,1),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x140(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x140(%RBX,%RAX,1),%ZMM2,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0x140(%R14,%RAX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM13,0x140(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x180(%R10,%RAX,1),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM14,0x180(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x180(%RBX,%RAX,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOV 0xe0(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VSUBPD 0x180(%R14,%RAX,1),%ZMM15,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM5,0x180(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD %ZMM1,0x1c0(%R15,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VADDPD 0x1c0(%RBX,%RAX,1),%ZMM1,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD 0x1c0(%R14,%RAX,1),%ZMM0,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD %ZMM11,0x1c0(%R12,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x200,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 423010 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3a80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

▶Scalability Runs Description

Run 8x1	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 1I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x8	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 8I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x12	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 12I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x16	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 16I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x20	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 20I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads
Run 8x24	Number processes: 8Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> Dataset: Run Directory: /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_7/oneview_run_1740498538OMP_NUM_THREADS: 24I_MPI_PIN_ORDER: bunchOMP_DISPLAY_AFFINITY: TRUEOMP_PROC_BIND: spreadOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEI_MPI_PIN_DOMAIN: autoI_MPI_DEBUG: 4OMP_PLACES: threads

(8x1) Efficiency	(8x1) Potential Speed-Up (%)	(8x8) Efficiency	(8x8) Potential Speed-Up (%)	(8x12) Efficiency	(8x12) Potential Speed-Up (%)	(8x16) Efficiency	(8x16) Potential Speed-Up (%)	(8x20) Efficiency	(8x20) Potential Speed-Up (%)	(8x24) Efficiency	(8x24) Potential Speed-Up (%)
1	0	0.25	1.83	0.16	2.2	0.12	2.15	0.1	2.13	0.08	2.42

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
8x1	8	1	1	1	1.9099999666214	1.8298751115799
8x8	64	0.25	2	8	1.0300000905991	2.4357399940491
8x12	96	0.16	1.93	12	1.0099999904633	2.6237058639526
8x16	128	0.12	1.97	16	1.0899999141693	2.4500632286072
8x20	160	0.1	1.98	20	1.0899999141693	2.3691816329956
8x24	192	0.08	1.93	24	1.0249999761581	2.6317446231842

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency