OV - exec - Loop 56

	Loop Id: 56	Module: exec	Source: PdV_kernel.f90:78-99 [...]	Coverage: 5.59%

0x413560 VMOVQ	%XMM7,%RSI

0x413565 VMOVUPD	(%R8,%RDX,1),%ZMM4    [17]

0x41356c VMOVUPD	(%RDI,%RDX,1),%ZMM1    [3]

0x413573 VMOVUPD	(%RSI,%RDX,1),%ZMM3    [21]

0x41357a VMOVQ	%XMM11,%RSI

0x41357f VADDPD	(%R15,%RDX,1),%ZMM3,%ZMM10    [8]

0x413586 VMOVUPD	(%R12,%RDX,1),%ZMM3    [6]

0x41358d VADDPD	(%RSI,%RDX,1),%ZMM4,%ZMM5    [20]

0x413594 VMOVUPD	(%R13,%RDX,1),%ZMM4    [7]

0x41359c VMOVQ	%XMM12,%RSI

0x4135a1 VADDPD	%ZMM1,%ZMM1,%ZMM2

0x4135a7 VMOVUPD	(%R11,%RDX,1),%ZMM1    [15]

0x4135ae VMULPD	%ZMM2,%ZMM5,%ZMM0

0x4135b4 VADDPD	(%RSI,%RDX,1),%ZMM3,%ZMM5    [14]

0x4135bb VADDPD	%ZMM4,%ZMM4,%ZMM2

0x4135c1 VADDPD	(%R14,%RDX,1),%ZMM1,%ZMM3    [18]

0x4135c8 VMOVUPD	(%R10,%RDX,1),%ZMM4    [1]

0x4135cf MOV	0x378(%RSP),%RSI    [19]

0x4135d7 VADDPD	%ZMM4,%ZMM4,%ZMM1

0x4135dd VMULPD	%ZMM1,%ZMM3,%ZMM4

0x4135e3 VMULSD	(%RSI),%XMM9,%XMM3    [13]

0x4135e7 MOV	0x368(%RSP),%RSI    [19]

0x4135ef VFMADD231PD	%ZMM2,%ZMM5,%ZMM4

0x4135f5 VMOVUPD	(%R9,%RDX,1),%ZMM5    [2]

0x4135fc VADDPD	%ZMM5,%ZMM5,%ZMM2

0x413602 VMOVUPD	(%RBX,%RDX,1),%ZMM5    [4]

0x413609 VFMADD132PD	%ZMM2,%ZMM0,%ZMM10

0x41360f VBROADCASTSD	%XMM3,%ZMM0

0x413615 VMOVUPD	(%RCX,%RDX,1),%ZMM3    [16]

0x41361c VSUBPD	%ZMM10,%ZMM4,%ZMM10

0x413622 VMULPD	%ZMM0,%ZMM10,%ZMM4

0x413628 VADDPD	(%RSI,%RDX,1),%ZMM3,%ZMM10    [12]

0x41362f MOV	0x358(%RSP),%RSI    [19]

0x413637 VDIVPD	(%RAX,%RDX,1),%ZMM10,%ZMM0    [5]

0x41363e VADDPD	%ZMM4,%ZMM5,%ZMM1

0x413644 VDIVPD	%ZMM1,%ZMM5,%ZMM2

0x41364a VDIVPD	%ZMM5,%ZMM8,%ZMM5

0x413650 VMULPD	%ZMM5,%ZMM0,%ZMM1

0x413656 VFNMADD213PD	(%RSI,%RDX,1),%ZMM1,%ZMM4    [11]

0x41365d MOV	0x370(%RSP),%RSI    [19]

0x413665 VMOVUPD	%ZMM4,(%RSI,%RDX,1)    [10]

0x41366c VMULPD	(%RAX,%RDX,1),%ZMM2,%ZMM4    [5]

0x413673 MOV	0x360(%RSP),%RSI    [19]

0x41367b VMOVUPD	%ZMM4,(%RSI,%RDX,1)    [9]

0x413682 MOV	0x350(%RSP),%RSI    [19]

0x41368a ADD	$0x40,%RDX

0x41368e CMP	%RSI,%RDX

0x413691 JNE	413560

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 78 - 99

--------------------------------------------------------------------------------

78:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

79:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

80:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

81:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

82:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

83:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

84:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

85:           total_flux=right_flux-left_flux+top_flux-bottom_flux

86:

87:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

93:           recip_volume=1.0/volume(j,k)

94:

95:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

96:

97:           energy1(j,k)=energy0(j,k)-energy_change

98:

99:           density1(j,k)=density0(j,k)*volume_change_s

Coverage (%)	Name	Source Location	Module
►95.55+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.55+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	pdv_kernel	PdV_kernel.f90:145	exec
○	pdv	PdV.f90:58	exec
○	hydro	hydro.f90:56	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P10, P11,
Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:78-87,PdV_kernel.f90:93-99
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	5.88
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	6.50
P11 cycles	6.50
P12 cycles	5.50
P13 cycles	5.50
P14 cycles	2.50
P15 cycles	2.50
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	47.00
Nb loads	25.00
Nb stores	2.00
Nb stack references	6.00
FLOP/cycle	16.75
Nb FLOP add-sub	88.00
Nb FLOP mul	41.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	111.33
Bytes prefetched	0.00
Bytes loaded	1208.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	19.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	87.18
Vectorization ratio load	94.74
Vectorization ratio store	100.00
Vectorization ratio mul	83.33
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	88.78
Vector-efficiency ratio load	95.39
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	85.42
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P10, P11,
Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:78-87,PdV_kernel.f90:93-99
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	5.88
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	6.50
P11 cycles	6.50
P12 cycles	5.50
P13 cycles	5.50
P14 cycles	2.50
P15 cycles	2.50
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	47.00
Nb loads	25.00
Nb stores	2.00
Nb stack references	6.00
FLOP/cycle	16.75
Nb FLOP add-sub	88.00
Nb FLOP mul	41.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	111.33
Bytes prefetched	0.00
Bytes loaded	1208.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	19.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	87.18
Vectorization ratio load	94.74
Vectorization ratio store	100.00
Vectorization ratio mul	83.33
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	88.78
Vector-efficiency ratio load	95.39
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	85.42
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:78-99
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:78-87,93-99.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all SSE/AVX instructions).

Details

87% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

94% of SSE/AVX loads are used in vector version.
83% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 6.75 cycles (1.78x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.00 cycles (1.71x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 12 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 12 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:82
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:82
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:78
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:80
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:80
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:84
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:84
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:78
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:87
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:95
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:97
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:99

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 22 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 201 FP arithmetical operations:

112: addition or subtraction (24 inside FMA instructions)
65: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1208 bytes (151 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	48
nb uops	47
loop length	311
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	8
nb stack references	6
ADD-SUB / MUL ratio	1.83

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	6.50	6.50	5.50	5.50	2.50	2.50
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	6.50	6.50	5.50	5.50	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	12.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.88
Dispatch	6.75
DIV/SQRT	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	94%
load	94%
store	100%
mul	83%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

INT+FP

all	87%
load	94%
store	100%
mul	83%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	95%
load	95%
store	100%
mul	85%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

INT+FP

all	88%
load	95%
store	100%
mul	85%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

39% of peak load performance is reached (100.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 413560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVQ %XMM7,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%R8,%RDX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RDI,%RDX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RSI,%RDX,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDPD (%R15,%RDX,1),%ZMM3,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R12,%RDX,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD (%RSI,%RDX,1),%ZMM4,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R13,%RDX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDPD %ZMM1,%ZMM1,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R11,%RDX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM5,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDPD (%RSI,%RDX,1),%ZMM3,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD (%R14,%RDX,1),%ZMM1,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R10,%RDX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x378(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %ZMM4,%ZMM4,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM3,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULSD (%RSI),%XMM9,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x368(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD231PD %ZMM2,%ZMM5,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD (%R9,%RDX,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM5,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%RBX,%RDX,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM2,%ZMM0,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD %XMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVUPD (%RCX,%RDX,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM4,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM10,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDPD (%RSI,%RDX,1),%ZMM3,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOV 0x358(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VDIVPD (%RAX,%RDX,1),%ZMM10,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VADDPD %ZMM4,%ZMM5,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VDIVPD %ZMM1,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VDIVPD %ZMM5,%ZMM8,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMULPD %ZMM5,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFNMADD213PD (%RSI,%RDX,1),%ZMM1,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x370(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD %ZMM4,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMULPD (%RAX,%RDX,1),%ZMM2,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x360(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD %ZMM4,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
MOV 0x350(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x40,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 413560 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x8a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:78-99
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all SSE/AVX instructions).

Details

87% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

94% of SSE/AVX loads are used in vector version.
83% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.00 cycles (1.71x speedup).

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 12 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 12 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:82
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:82
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:78
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:80
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:80
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:84
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:84
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:78
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:87
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:95
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:97
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:99

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 201 FP arithmetical operations:

112: addition or subtraction (24 inside FMA instructions)
65: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1208 bytes (151 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	48
nb uops	47
loop length	311
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	8
nb stack references	6
ADD-SUB / MUL ratio	1.83

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	6.50	6.50	5.50	5.50	2.50	2.50
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	6.50	6.50	5.50	5.50	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	12.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.88
Dispatch	6.75
DIV/SQRT	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	94%
load	94%
store	100%
mul	83%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

INT+FP

all	87%
load	94%
store	100%
mul	83%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	95%
load	95%
store	100%
mul	85%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

INT+FP

all	88%
load	95%
store	100%
mul	85%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

39% of peak load performance is reached (100.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 413560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVQ %XMM7,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%R8,%RDX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RDI,%RDX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RSI,%RDX,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDPD (%R15,%RDX,1),%ZMM3,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R12,%RDX,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD (%RSI,%RDX,1),%ZMM4,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R13,%RDX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDPD %ZMM1,%ZMM1,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R11,%RDX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM5,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDPD (%RSI,%RDX,1),%ZMM3,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD (%R14,%RDX,1),%ZMM1,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R10,%RDX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x378(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %ZMM4,%ZMM4,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM3,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULSD (%RSI),%XMM9,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x368(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD231PD %ZMM2,%ZMM5,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD (%R9,%RDX,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM5,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%RBX,%RDX,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM2,%ZMM0,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD %XMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVUPD (%RCX,%RDX,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM4,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM10,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDPD (%RSI,%RDX,1),%ZMM3,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOV 0x358(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VDIVPD (%RAX,%RDX,1),%ZMM10,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VADDPD %ZMM4,%ZMM5,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VDIVPD %ZMM1,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VDIVPD %ZMM5,%ZMM8,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMULPD %ZMM5,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFNMADD213PD (%RSI,%RDX,1),%ZMM1,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x370(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD %ZMM4,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMULPD (%RAX,%RDX,1),%ZMM2,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x360(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD %ZMM4,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
MOV 0x350(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x40,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 413560 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x8a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code