OV - exec - Loop 221

	Loop Id: 221	Module: exec	Source: initialise_chunk_kernel.f90:111-111	Coverage: 0.01%

0x4320c0 VMOVSD	(%R14),%XMM7    [3]

0x4320c5 VMULSD	(%R13),%XMM7,%XMM5    [2]

0x4320cb VBROADCASTSD	%XMM5,%ZMM8

0x4320d1 ADD	$0x200,%RAX

0x4320d7 VMOVUPD	%ZMM8,-0x200(%RAX)    [1]

0x4320de VMOVSD	(%R14),%XMM9    [3]

0x4320e3 VMULSD	(%R13),%XMM9,%XMM10    [2]

0x4320e9 VBROADCASTSD	%XMM10,%ZMM11

0x4320ef VMOVUPD	%ZMM11,-0x1c0(%RAX)    [1]

0x4320f6 VMOVSD	(%R14),%XMM12    [3]

0x4320fb VMULSD	(%R13),%XMM12,%XMM14    [2]

0x432101 VBROADCASTSD	%XMM14,%ZMM15

0x432107 VMOVUPD	%ZMM15,-0x180(%RAX)    [1]

0x43210e VMOVSD	(%R14),%XMM1    [3]

0x432113 VMULSD	(%R13),%XMM1,%XMM2    [2]

0x432119 VBROADCASTSD	%XMM2,%ZMM6

0x43211f VMOVUPD	%ZMM6,-0x140(%RAX)    [1]

0x432126 VMOVSD	(%R14),%XMM3    [3]

0x43212b VMULSD	(%R13),%XMM3,%XMM4    [2]

0x432131 VBROADCASTSD	%XMM4,%ZMM7

0x432137 VMOVUPD	%ZMM7,-0x100(%RAX)    [1]

0x43213e VMOVSD	(%R14),%XMM5    [3]

0x432143 VMULSD	(%R13),%XMM5,%XMM8    [2]

0x432149 VBROADCASTSD	%XMM8,%ZMM9

0x43214f VMOVUPD	%ZMM9,-0xc0(%RAX)    [1]

0x432156 VMOVSD	(%R14),%XMM10    [3]

0x43215b VMULSD	(%R13),%XMM10,%XMM11    [2]

0x432161 VBROADCASTSD	%XMM11,%ZMM12

0x432167 VMOVUPD	%ZMM12,-0x80(%RAX)    [1]

0x43216e VMOVSD	(%R14),%XMM14    [3]

0x432173 VMULSD	(%R13),%XMM14,%XMM15    [2]

0x432179 VBROADCASTSD	%XMM15,%ZMM1

0x43217f VMOVUPD	%ZMM1,-0x40(%RAX)    [1]

0x432186 CMP	%R9,%RAX

0x432189 JNE	4320c0

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90: 111 - 111

--------------------------------------------------------------------------------

111:         volume(j,k)=dx*dy

Coverage (%)	Name	Source Location	Module
►96.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►4.00+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	initialise_chunk_kernel	initialise_chunk_kernel.f90:135	exec
○	initialise_chunk	initialise_chunk.f90:58	exec
○	start	start.f90:106	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.41
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P6, P7, P8, P9,
Function	__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0
Source	initialise_chunk_kernel.f90:111-111
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	4.25
CQA cycles if fully vectorized	4.00
Front-end cycles	4.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	5.50
P11 cycles	5.50
P12 cycles	5.00
P13 cycles	0.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	16.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	1.33
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	106.67
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	512.00
Stride 0	2.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	25.00
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	34.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.41
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P6, P7, P8, P9,
Function	__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0
Source	initialise_chunk_kernel.f90:111-111
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	4.25
CQA cycles if fully vectorized	4.00
Front-end cycles	4.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	5.50
P11 cycles	5.50
P12 cycles	5.00
P13 cycles	0.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	16.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	1.33
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	106.67
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	512.00
Stride 0	2.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	25.00
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	34.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0
Source file and lines	initialise_chunk_kernel.f90:111-111
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 34% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.00 to 4.00 cycles (1.50x speedup).

Details

25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 5.50 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Vector unaligned load/store instructions

Detected 8 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: multiply

The binary loop is loading 128 bytes (16 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	35
nb uops	34
loop length	207
used x86 registers	4
used mmx registers	0
used xmm registers	13
used ymm registers	0
used zmm registers	8
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.00	6.00	6.00	6.00	5.50	5.50	5.00	0.00	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.00	6.00	6.00	6.00	5.50	5.50	5.00	0.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	25%
load	0%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	34%
load	12%
store	100%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

8% of peak load performance is reached (21.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
66% of peak store performance is reached (85.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4320c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD (%R14),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM7,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM5,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x200,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM8,-0x200(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM11,-0x1c0(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM12,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM14,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM15,-0x180(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM6,-0x140(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM7,-0x100(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM5,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM9,-0xc0(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM10,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM11,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM12,-0x80(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM14,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM15,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM1,-0x40(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
CMP %R9,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4320c0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1300>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0
Source file and lines	initialise_chunk_kernel.f90:111-111
Module	exec

gain
potential
hint
expert

Vectorization

Details

25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 5.50 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Vector unaligned load/store instructions

Detected 8 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:111

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: multiply

The binary loop is loading 128 bytes (16 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	35
nb uops	34
loop length	207
used x86 registers	4
used mmx registers	0
used xmm registers	13
used ymm registers	0
used zmm registers	8
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.00	6.00	6.00	6.00	5.50	5.50	5.00	0.00	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.00	6.00	6.00	6.00	5.50	5.50	5.00	0.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	25%
load	0%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	34%
load	12%
store	100%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

8% of peak load performance is reached (21.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
66% of peak store performance is reached (85.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4320c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD (%R14),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM7,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM5,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x200,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM8,-0x200(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM11,-0x1c0(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM12,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM14,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM15,-0x180(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM6,-0x140(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM7,-0x100(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM5,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM9,-0xc0(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM10,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM11,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM12,-0x80(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVSD (%R14),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R13),%XMM14,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM15,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %ZMM1,-0x40(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
CMP %R9,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4320c0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1300>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code