OV - exec - Loop 162

	Loop Id: 162	Module: exec	Source: field_summary_kernel.f90:62-71	Coverage: 0.31%

0x42a5b0 VMOVUPD	(%R11,%RAX,8),%XMM10    [5]

0x42a5b6 VMOVUPD	(%RBX,%RAX,8),%XMM15    [7]

0x42a5bb LEA	0x1(%RAX),%RDX

0x42a5bf VMULPD	%XMM10,%XMM10,%XMM0

0x42a5c4 VMOVUPD	(%R9,%RAX,8),%XMM10    [2]

0x42a5ca VFMADD132PD	%XMM15,%XMM0,%XMM15

0x42a5cf VMOVUPD	(%R10,%RAX,8),%XMM0    [4]

0x42a5d5 VMULPD	%XMM3,%XMM15,%XMM11

0x42a5d9 VUNPCKHPD	%XMM11,%XMM11,%XMM1

0x42a5de VADDPD	%XMM11,%XMM1,%XMM15

0x42a5e3 VMULPD	%XMM10,%XMM10,%XMM11

0x42a5e8 VFMADD132PD	%XMM0,%XMM11,%XMM0

0x42a5ed VMULPD	%XMM3,%XMM0,%XMM1

0x42a5f1 VUNPCKHPD	%XMM1,%XMM1,%XMM0

0x42a5f5 VADDPD	%XMM1,%XMM0,%XMM10

0x42a5f9 VADDSD	%XMM10,%XMM15,%XMM15

0x42a5fe VMOVSD	(%R8,%RAX,8),%XMM10    [1]

0x42a604 VMULSD	%XMM4,%XMM15,%XMM1

0x42a608 VMULSD	(%RDI,%RAX,8),%XMM10,%XMM11    [3]

0x42a60d VFMADD231SD	(%RSI,%RAX,8),%XMM11,%XMM12    [6]

0x42a613 VADDSD	%XMM11,%XMM13,%XMM13

0x42a618 VFMADD132SD	%XMM1,%XMM2,%XMM11

0x42a61d VMOVUPD	(%R11,%RDX,8),%XMM2    [5]

0x42a623 VADDSD	%XMM10,%XMM14,%XMM14

0x42a628 VFMADD132SD	(%RCX,%RAX,8),%XMM9,%XMM10    [8]

0x42a62e VMOVUPD	(%RBX,%RDX,8),%XMM9    [7]

0x42a633 ADD	$0x2,%RAX

0x42a637 VMULPD	%XMM2,%XMM2,%XMM0

0x42a63b VMOVUPD	(%R9,%RDX,8),%XMM2    [2]

0x42a641 VFMADD132PD	%XMM9,%XMM0,%XMM9

0x42a646 VMOVUPD	(%R10,%RDX,8),%XMM0    [4]

0x42a64c VMULPD	%XMM3,%XMM9,%XMM15

0x42a650 VUNPCKHPD	%XMM15,%XMM15,%XMM1

0x42a655 VADDPD	%XMM15,%XMM1,%XMM9

0x42a65a VMULPD	%XMM2,%XMM2,%XMM15

0x42a65e VFMADD132PD	%XMM0,%XMM15,%XMM0

0x42a663 VMULPD	%XMM3,%XMM0,%XMM1

0x42a667 VUNPCKHPD	%XMM1,%XMM1,%XMM0

0x42a66b VADDPD	%XMM1,%XMM0,%XMM2

0x42a66f VADDSD	%XMM2,%XMM9,%XMM15

0x42a673 VMOVSD	(%R8,%RDX,8),%XMM9    [1]

0x42a679 VMULSD	%XMM4,%XMM15,%XMM1

0x42a67d VMULSD	(%RDI,%RDX,8),%XMM9,%XMM2    [3]

0x42a682 VADDSD	%XMM9,%XMM14,%XMM14

0x42a687 VADDSD	%XMM2,%XMM13,%XMM13

0x42a68b VFMADD231SD	(%RSI,%RDX,8),%XMM2,%XMM12    [6]

0x42a691 VFMADD132SD	(%RCX,%RDX,8),%XMM10,%XMM9    [8]

0x42a697 VFMADD132SD	%XMM1,%XMM11,%XMM2

0x42a69c CMP	%EAX,%R12D

0x42a69f JGE	42a5b0

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 62 - 71

--------------------------------------------------------------------------------

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

Coverage (%)	Name	Source Location	Module
►94.76+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.72+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	field_summary_kernel	field_summary_kernel.f90:77	exec
○	field_summary	field_summary.f90:69	exec
○	hydro	hydro.f90:74	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.75
CQA speedup if fully vectorized	5.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.57
Bottlenecks	P10, P11,
Function	__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0
Source	field_summary_kernel.f90:62-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	2.13
Front-end cycles	6.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.00
P13 cycles	7.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	49.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	5.64
Nb FLOP add-sub	14.00
Nb FLOP mul	20.00
Nb FLOP fma	14.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.45
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	4.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	52.17
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	66.67
Vectorization ratio add_sub	40.00
Vectorization ratio fma	40.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.02
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	20.83
Vector-efficiency ratio add_sub	17.50
Vector-efficiency ratio fma	17.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.75
CQA speedup if fully vectorized	5.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.57
Bottlenecks	P10, P11,
Function	__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0
Source	field_summary_kernel.f90:62-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	2.13
Front-end cycles	6.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.00
P13 cycles	7.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	49.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	5.64
Nb FLOP add-sub	14.00
Nb FLOP mul	20.00
Nb FLOP fma	14.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.45
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	4.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	52.17
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	66.67
Vectorization ratio add_sub	40.00
Vectorization ratio fma	40.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.02
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	20.83
Vector-efficiency ratio add_sub	17.50
Vector-efficiency ratio fma	17.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0
Source file and lines	field_summary_kernel.f90:62-71
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:62-71.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 19% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.00 to 2.12 cycles (5.18x speedup).

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
40% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
40% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.00 to 7.00 cycles (1.57x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 16 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 62 FP arithmetical operations:

28: addition or subtraction (14 inside FMA instructions)
34: multiply (14 inside FMA instructions)

The binary loop is loading 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	50
nb uops	49
loop length	245
used x86 registers	11
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.83

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	11.00	11.00	7.00	7.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	11.00	11.00	7.00	7.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	6.13
Dispatch	11.00
Data deps.	8.00
Overall L1	11.00

Vectorization ratios

all	52%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	40%
fma	40%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	19%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	20%
add-sub	17%
fma	17%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

6% of peak load performance is reached (17.45 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42a5b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RBX,%RAX,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
LEA 0x1(%RAX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD %XMM10,%XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R9,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD132PD %XMM15,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD (%R10,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM3,%XMM15,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VUNPCKHPD %XMM11,%XMM11,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
VADDPD %XMM11,%XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VMULPD %XMM10,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VFMADD132PD %XMM0,%XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMULPD %XMM3,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VUNPCKHPD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
VADDPD %XMM1,%XMM0,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VADDSD %XMM10,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VMOVSD (%R8,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMULSD (%RDI,%RAX,8),%XMM10,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD231SD (%RSI,%RAX,8),%XMM11,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VADDSD %XMM11,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VFMADD132SD %XMM1,%XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVUPD (%R11,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VADDSD %XMM10,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VFMADD132SD (%RCX,%RAX,8),%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVUPD (%RBX,%RDX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD %XMM2,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R9,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD132PD %XMM9,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD (%R10,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM3,%XMM9,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VUNPCKHPD %XMM15,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
VADDPD %XMM15,%XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VMULPD %XMM2,%XMM2,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VFMADD132PD %XMM0,%XMM15,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMULPD %XMM3,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VUNPCKHPD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
VADDPD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VADDSD %XMM2,%XMM9,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VMOVSD (%R8,%RDX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMULSD (%RDI,%RDX,8),%XMM9,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VADDSD %XMM9,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VADDSD %XMM2,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VFMADD231SD (%RSI,%RDX,8),%XMM2,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VFMADD132SD (%RCX,%RDX,8),%XMM10,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM1,%XMM11,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
CMP %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JGE 42a5b0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0
Source file and lines	field_summary_kernel.f90:62-71
Module	exec

gain
potential
hint
expert

Vectorization

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
40% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
40% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 62 FP arithmetical operations:

28: addition or subtraction (14 inside FMA instructions)
34: multiply (14 inside FMA instructions)

The binary loop is loading 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	50
nb uops	49
loop length	245
used x86 registers	11
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.83

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	11.00	11.00	7.00	7.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	11.00	11.00	7.00	7.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	6.13
Dispatch	11.00
Data deps.	8.00
Overall L1	11.00

Vectorization ratios

all	52%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	40%
fma	40%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	19%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	20%
add-sub	17%
fma	17%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

6% of peak load performance is reached (17.45 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42a5b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RBX,%RAX,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
LEA 0x1(%RAX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD %XMM10,%XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R9,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD132PD %XMM15,%XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD (%R10,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM3,%XMM15,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VUNPCKHPD %XMM11,%XMM11,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
VADDPD %XMM11,%XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VMULPD %XMM10,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VFMADD132PD %XMM0,%XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMULPD %XMM3,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VUNPCKHPD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
VADDPD %XMM1,%XMM0,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VADDSD %XMM10,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VMOVSD (%R8,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMULSD (%RDI,%RAX,8),%XMM10,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VFMADD231SD (%RSI,%RAX,8),%XMM11,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VADDSD %XMM11,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VFMADD132SD %XMM1,%XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVUPD (%R11,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VADDSD %XMM10,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VFMADD132SD (%RCX,%RAX,8),%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVUPD (%RBX,%RDX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD %XMM2,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R9,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD132PD %XMM9,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD (%R10,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM3,%XMM9,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VUNPCKHPD %XMM15,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
VADDPD %XMM15,%XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VMULPD %XMM2,%XMM2,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VFMADD132PD %XMM0,%XMM15,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMULPD %XMM3,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VUNPCKHPD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
VADDPD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VADDSD %XMM2,%XMM9,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VMOVSD (%R8,%RDX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMULSD (%RDI,%RDX,8),%XMM9,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
VADDSD %XMM9,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VADDSD %XMM2,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VFMADD231SD (%RSI,%RDX,8),%XMM2,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VFMADD132SD (%RCX,%RDX,8),%XMM10,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM1,%XMM11,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
CMP %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JGE 42a5b0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code