OV - exec - Loop 102

	Loop Id: 102	Module: exec	Source: advec_mom_kernel.f90:151-176	Coverage: 0.01%

0x4206f0 VMOVD	%XMM6,%R15D

0x4206f5 CMP	%R15D,0xf8(%RSP)

0x4206fd JG	420871

0x420703 MOVSXD	0xf0(%RSP),%RAX

0x42070b VMOVQ	%XMM26,%R12

0x420711 MOV	%R13,%RDX

0x420714 MOV	%R14D,0x120(%RSP)

0x42071c VXORPD	%XMM7,%XMM7,%XMM7

0x420720 MOV	%R11,%R14

0x420723 VMOVSD	0x8216d(%RIP),%XMM10

0x42072b MOV	%R9,%R11

0x42072e LEA	0x1(%RAX),%RDI

0x420732 LEA	0x1(%RAX,%R12,1),%RSI

0x420737 MOV	%RSI,%R13

0x42073a MOV	%RDI,%R10

0x42073d JMP	420834

  (103) 0x420750 LEA	-0x2(%RAX),%R12D

  (103) 0x420754 MOV	%RAX,%RSI

  (103) 0x420757 MOVSXD	%R12D,%R9

  (103) 0x42075a MOVSXD	%R12D,%R12

  (103) 0x42075d ADD	%R11,%RSI

  (103) 0x420760 LEA	(%R11,%R15,1),%RDI

  (103) 0x420764 ADD	%R11,%R12

  (103) 0x420767 VMOVSD	(%RCX,%RDI,8),%XMM1

  (103) 0x42076c VMOVSD	(%RCX,%RSI,8),%XMM2

  (103) 0x420771 VSUBSD	%XMM1,%XMM2,%XMM0

  (103) 0x420775 VSUBSD	(%RCX,%R12,8),%XMM1,%XMM15

  (103) 0x42077b VMULSD	%XMM15,%XMM0,%XMM4

  (103) 0x420780 VCOMISD	%XMM7,%XMM4

  (103) 0x420784 JBE	42081e

  (103) 0x42078a VANDPD	%XMM8,%XMM15,%XMM2

  (103) 0x42078f VCOMISD	%XMM0,%XMM7

  (103) 0x420793 VANDPD	%XMM8,%XMM0,%XMM15

  (103) 0x420798 JAE	422ca0

  (103) 0x42079e VMOVAPD	%XMM9,%XMM18

  (103) 0x4207a4 VMOVAPD	%XMM9,%XMM17

  (103) 0x4207aa ADD	%RDX,%R15

  (103) 0x4207ad VMOVQ	%XMM13,%RSI

  (103) 0x4207b2 VANDPD	%XMM8,%XMM3,%XMM5

  (103) 0x4207b7 VMOVQ	%XMM14,%RDI

  (103) 0x4207bc VDIVSD	(%RSI,%R15,8),%XMM5,%XMM4

  (103) 0x4207c2 MOV	0x128(%RSP),%R15

  (103) 0x4207ca VADDSD	%XMM18,%XMM4,%XMM0

  (103) 0x4207d0 VMOVSD	-0x8(%R8,%RAX,8),%XMM16

  (103) 0x4207d8 VMULSD	%XMM2,%XMM0,%XMM5

  (103) 0x4207dc VMULSD	%XMM10,%XMM16,%XMM19

  (103) 0x4207e2 VMINSD	%XMM2,%XMM15,%XMM2

  (103) 0x4207e6 VSUBSD	%XMM4,%XMM18,%XMM25

  (103) 0x4207ec ADD	%R15,%R9

  (103) 0x4207ef VDIVSD	(%RDI,%R9,8),%XMM5,%XMM0

  (103) 0x4207f5 VSUBSD	%XMM4,%XMM12,%XMM5

  (103) 0x4207f9 VMULSD	%XMM15,%XMM5,%XMM5

  (103) 0x4207fe VDIVSD	%XMM16,%XMM5,%XMM5

  (103) 0x420804 VADDSD	%XMM5,%XMM0,%XMM0

  (103) 0x420808 VMULSD	%XMM19,%XMM0,%XMM5

  (103) 0x42080e VMINSD	%XMM2,%XMM5,%XMM15

  (103) 0x420812 VMULSD	%XMM25,%XMM15,%XMM4

  (103) 0x420818 VFMADD231SD	%XMM4,%XMM17,%XMM1

  (103) 0x42081e VMULSD	%XMM3,%XMM1,%XMM3

  (103) 0x420822 VMOVSD	%XMM3,-0x8(%R14,%RAX,8)

  (103) 0x420829 MOV	%R10,%RAX

  (103) 0x42082c CMP	%R10,%R13

  (103) 0x42082f JE	420860

  (103) 0x420831 INC	%R10

  (103) 0x420834 VMOVSD	-0x8(%RBX,%RAX,8),%XMM3

  (103) 0x42083a LEA	-0x1(%RAX),%R15

  (103) 0x42083e VCOMISD	%XMM3,%XMM7

  (103) 0x420842 JBE	420750

  (103) 0x420848 MOV	%R15,%RSI

  (103) 0x42084b MOVSXD	%EAX,%R9

  (103) 0x42084e LEA	0x1(%RAX),%R12D

  (103) 0x420852 MOV	%RAX,%R15

  (103) 0x420855 JMP	42075a

0x420860 MOV	%R11,%R9

0x420863 MOV	%R14,%R11

0x420866 MOV	0x120(%RSP),%R14D

0x42086e MOV	%RDX,%R13

0x420871 MOV	0x138(%RSP),%R10

0x420879 MOV	0x118(%RSP),%R12

0x420881 VMOVQ	%XMM21,%RDX

0x420887 VMOVQ	%XMM11,%RSI

0x42088c INC	%R14D

0x42088f ADD	%RDX,%R11

0x420892 ADD	%RSI,%RBX

0x420895 ADD	%R10,%R13

0x420898 ADD	%R12,%R9

0x42089b CMP	%R14D,0x108(%RSP)

0x4208a3 JG	4206f0

  (103) 0x422ca0 VMOVSD	0x7fbde(%RIP),%XMM17

  (103) 0x422caa VMOVSD	0x7f8b4(%RIP),%XMM18

  (103) 0x422cb4 JMP	4207aa

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 151 - 176

--------------------------------------------------------------------------------

151:         DO j=x_min-1,x_max+1

152:           IF(node_flux(j,k).LT.0.0)THEN

153:             upwind=j+2

154:             donor=j+1

155:             downwind=j

156:             dif=donor

157:           ELSE

158:             upwind=j-1

159:             donor=j

160:             downwind=j+1

161:             dif=upwind

162:           ENDIF

163:           sigma=ABS(node_flux(j,k))/(node_mass_pre(donor,k))

164:           width=celldx(j)

165:           vdiffuw=vel1(donor,k)-vel1(upwind,k)

166:           vdiffdw=vel1(downwind,k)-vel1(donor,k)

167:           limiter=0.0

168:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

169:             auw=ABS(vdiffuw)

170:             adw=ABS(vdiffdw)

171:             wind=1.0_8

172:             IF(vdiffdw.LE.0.0) wind=-1.0_8

173:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldx(dif))/6.0_8,auw,adw)

174:           ENDIF

175:           advec_vel_s=vel1(donor,k)+(1.0-sigma)*limiter

176:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

Coverage (%)	Name	Source Location	Module
►97.22+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.94
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.41
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.72
Bottlenecks	micro-operation queue,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:151-152,advec_mom_kernel.f90:163-163,advec_mom_kernel.f90:173-173
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.88
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	3.88
CQA cycles if fully vectorized	0.29
Front-end cycles	3.88
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	7.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.35
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	5.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	7.69
Vector-efficiency ratio all	12.19
Vector-efficiency ratio load	10.42
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.94
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.41
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.72
Bottlenecks	micro-operation queue,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:151-152,advec_mom_kernel.f90:163-163,advec_mom_kernel.f90:173-173
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.88
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	3.88
CQA cycles if fully vectorized	0.29
Front-end cycles	3.88
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	7.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.35
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	5.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	7.69
Vector-efficiency ratio all	12.19
Vector-efficiency ratio load	10.42
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:151-176
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:151-176.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:151-152,163,173.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=13
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 13 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.88 to 2.00 cycles (1.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.88 to 0.29 cycles (13.41x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:173

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	31
nb uops	31
loop length	155
used x86 registers	13
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.88 cycles
front end	3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.00	2.00	2.00	2.00	2.00	2.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.00	2.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.88
Dispatch	2.25
Overall L1	3.88

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	11%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.88 cycles. At this rate:

4% of peak load performance is reached (10.32 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.03 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.88 to 2.25 cycles (1.72x speedup).

ASM code

In the binary file, the address of the loop is: 4206f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
VMOVD %XMM6,%R15D	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
CMP %R15D,0xf8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (6.3%)
JG 420871 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x12e1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0xf0(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVQ %XMM26,%R12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R14D,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R11,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8216d(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %R9,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA 0x1(%RAX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%RAX,%R12,1),%RSI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 420834 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x12a4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %R11,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x120(%RSP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x138(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV 0x118(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %XMM21,%RDX	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RSI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R10,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R12,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R14D,0x108(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JG 4206f0 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1160>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:151-176
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=13
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.88 to 2.00 cycles (1.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:173

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	31
nb uops	31
loop length	155
used x86 registers	13
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.88 cycles
front end	3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.00	2.00	2.00	2.00	2.00	2.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.00	2.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.88
Dispatch	2.25
Overall L1	3.88

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	11%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.88 cycles. At this rate:

4% of peak load performance is reached (10.32 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.03 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4206f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
VMOVD %XMM6,%R15D	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
CMP %R15D,0xf8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (6.3%)
JG 420871 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x12e1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0xf0(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVQ %XMM26,%R12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R14D,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R11,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8216d(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %R9,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA 0x1(%RAX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%RAX,%R12,1),%RSI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 420834 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x12a4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %R11,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x120(%RSP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x138(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV 0x118(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %XMM21,%RDX	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RSI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R10,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R12,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R14D,0x108(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JG 4206f0 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1160>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code