OV - exec - Function __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp

	Function: __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0	Module: exec	Source: ideal_gas_kernel.f90:45-55	Coverage (incl. loops): 5.56% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90: 45 - 55

--------------------------------------------------------------------------------

45:     !$OMP PARALLEL

46:     !$OMP DO PRIVATE(v,pressurebyenergy,pressurebyvolume,sound_speed_squared)

47:     DO k=y_min,y_max

48:     !$OMP SIMD

49:       DO j=x_min,x_max

50:         v=1.0_8/density(j,k)

51:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

52:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

53:         pressurebyvolume=-density(j,k)*pressure(j,k)

54:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

55:         soundspeed(j,k)=SQRT(sound_speed_squared)

0x430340 PUSH	%RBP

0x430341 MOV	%RSP,%RBP

0x430344 PUSH	%R15

0x430346 PUSH	%R14

0x430348 PUSH	%R13

0x43034a PUSH	%R12

0x43034c PUSH	%RBX

0x43034d MOV	%RDI,%R12

0x430350 AND	$-0x40,%RSP

0x430354 SUB	$0x40,%RSP

0x430358 MOV	0x10(%RDI),%RAX

0x43035c MOV	(%RAX),%R14D

0x43035f CALL	402370 <@plt_start@+0x350>

0x430364 MOV	%EAX,%R13D

0x430367 CALL	4022e0 <@plt_start@+0x2c0>

0x43036c MOV	0x18(%R12),%RDX

0x430371 MOV	%EAX,%ECX

0x430373 MOV	(%RDX),%EAX

0x430375 INC	%EAX

0x430377 SUB	%R14D,%EAX

0x43037a CLTD

0x43037b IDIV	%R13D

0x43037e CMP	%EDX,%ECX

0x430380 JL	43097f

0x430386 IMUL	%EAX,%ECX

0x430389 ADD	%ECX,%EDX

0x43038b ADD	%EDX,%EAX

0x43038d CMP	%EAX,%EDX

0x43038f JGE	430960

0x430395 MOV	(%R12),%RSI

0x430399 MOV	0x8(%R12),%RDI

0x43039e VMOVQ	0x40(%R12),%XMM13

0x4303a5 VMOVQ	0x50(%R12),%XMM14

0x4303ac ADD	%R14D,%EAX

0x4303af ADD	%R14D,%EDX

0x4303b2 VMOVQ	0x60(%R12),%XMM12

0x4303b9 VMOVQ	0x70(%R12),%XMM15

0x4303c0 MOVSXD	%EDX,%R13

0x4303c3 MOV	%EAX,0x2c(%RSP)

0x4303c7 VMOVQ	0x28(%R12),%XMM6

0x4303ce VMOVQ	0x30(%R12),%XMM7

0x4303d5 VMOVQ	0x38(%R12),%XMM8

0x4303dc MOV	0x20(%R12),%R15

0x4303e1 MOVSXD	(%RSI),%RSI

0x4303e4 MOV	(%RDI),%R14D

0x4303e7 VMOVQ	%XMM13,%R8

0x4303ec VMOVQ	%XMM14,%R9

0x4303f1 IMUL	%R13,%R8

0x4303f5 VMOVQ	%XMM12,%R11

0x4303fa VMOVQ	%XMM15,%RCX

0x4303ff IMUL	%R13,%R9

0x430403 IMUL	%R13,%R11

0x430407 MOV	%RSI,%R10

0x43040a VMOVQ	%RSI,%XMM5

0x43040f MOV	%ESI,0x1c(%RSP)

0x430413 ADD	0x48(%R12),%RSI

0x430418 IMUL	%RCX,%R13

0x43041c MOV	%R10,%RDI

0x43041f ADD	0x58(%R12),%RDI

0x430424 LEA	0x1(%R14),%EAX

0x430428 MOV	%R14D,0x28(%RSP)

0x43042d ADD	%R8,%RSI

0x430430 MOV	%R10,%R8

0x430433 ADD	0x68(%R12),%R8

0x430438 ADD	%R9,%RDI

0x43043b MOV	%R10,%R9

0x43043e ADD	0x78(%R12),%R9

0x430443 ADD	%R11,%R8

0x430446 ADD	%R13,%R9

0x430449 CMP	%R14D,%R10D

0x43044c MOV	%R10D,%R13D

0x43044f CMOVLE	%EAX,%R13D

0x430453 JG	430988

0x430459 SUB	%R10D,%R14D

0x43045c VMOVSD	0x72104(%RIP),%XMM11

0x430464 VMOVSD	0x725d4(%RIP),%XMM10

0x43046c VBROADCASTSD	%XMM11,%YMM17

0x430472 LEA	0x1(%R14),%R10D

0x430476 MOV	%R14D,0x38(%RSP)

0x43047b VBROADCASTSD	%XMM10,%YMM16

0x430481 VMOVQ	%XMM6,%R14

0x430486 MOV	%R10D,0x18(%RSP)

0x43048b SHR	$0x3,%R10D

0x43048f VMOVSD	0x725b1(%RIP),%XMM9

0x430497 MOV	%R13D,0x14(%RSP)

0x43049c MOV	%R12,0x8(%RSP)

0x4304a1 SAL	$0x6,%R10

0x4304a5 MOV	%R10,0x30(%RSP)

0x4304aa VMOVQ	%XMM7,%R10

0x4304af NOP

(212) 0x4304b0 CMPL	$0x6,0x38(%RSP)

(212) 0x4304b5 JBE	430970

(212) 0x4304bb MOV	0x30(%RSP),%RCX

(212) 0x4304c0 VMOVQ	%XMM8,%RAX

(212) 0x4304c5 VBROADCASTSD	0x72099(%RIP),%ZMM4

(212) 0x4304cf VBROADCASTSD	0x72567(%RIP),%ZMM3

(212) 0x4304d9 LEA	(%RAX,%R9,8),%RBX

(212) 0x4304dd XOR	%EAX,%EAX

(212) 0x4304df VBROADCASTSD	0x7255f(%RIP),%ZMM2

(212) 0x4304e9 LEA	(%R15,%RSI,8),%R11

(212) 0x4304ed LEA	(%R14,%RDI,8),%R13

(212) 0x4304f1 LEA	(%R10,%R8,8),%R12

(212) 0x4304f5 SUB	$0x40,%RCX

(212) 0x4304f9 SHR	$0x6,%RCX

(212) 0x4304fd INC	%RCX

(212) 0x430500 AND	$0x3,%ECX

(212) 0x430503 JE	430605

(212) 0x430509 CMP	$0x1,%RCX

(212) 0x43050d JE	4305ae

(212) 0x430513 CMP	$0x2,%RCX

(212) 0x430517 JE	430562

(212) 0x430519 VMOVUPD	(%R11),%ZMM18

(212) 0x43051f VMULPD	(%R13),%ZMM18,%ZMM20

(212) 0x430526 MOV	$0x40,%EAX

(212) 0x43052b VDIVPD	%ZMM18,%ZMM4,%ZMM19

(212) 0x430531 VMULPD	%ZMM3,%ZMM20,%ZMM21

(212) 0x430537 VMOVUPD	%ZMM21,(%R12)

(212) 0x43053e VMULPD	(%R11),%ZMM2,%ZMM0

(212) 0x430544 VMULPD	%ZMM19,%ZMM19,%ZMM22

(212) 0x43054a VMULPD	%ZMM21,%ZMM0,%ZMM1

(212) 0x430550 VMULPD	%ZMM22,%ZMM1,%ZMM6

(212) 0x430556 VSQRTPD	%ZMM6,%ZMM7

(212) 0x43055c VMOVUPD	%ZMM7,(%RBX)

(212) 0x430562 VMOVUPD	(%R11,%RAX,1),%ZMM23

(212) 0x430569 VMULPD	(%R13,%RAX,1),%ZMM23,%ZMM25

(212) 0x430571 VDIVPD	%ZMM23,%ZMM4,%ZMM24

(212) 0x430577 VMULPD	%ZMM3,%ZMM25,%ZMM26

(212) 0x43057d VMOVUPD	%ZMM26,(%R12,%RAX,1)

(212) 0x430584 VMULPD	(%R11,%RAX,1),%ZMM2,%ZMM0

(212) 0x43058b VMULPD	%ZMM24,%ZMM24,%ZMM27

(212) 0x430591 VMULPD	%ZMM26,%ZMM0,%ZMM1

(212) 0x430597 VMULPD	%ZMM27,%ZMM1,%ZMM6

(212) 0x43059d VSQRTPD	%ZMM6,%ZMM7

(212) 0x4305a3 VMOVUPD	%ZMM7,(%RBX,%RAX,1)

(212) 0x4305aa ADD	$0x40,%RAX

(212) 0x4305ae VMOVUPD	(%R11,%RAX,1),%ZMM28

(212) 0x4305b5 VMULPD	(%R13,%RAX,1),%ZMM28,%ZMM30

(212) 0x4305bd VDIVPD	%ZMM28,%ZMM4,%ZMM29

(212) 0x4305c3 VMULPD	%ZMM3,%ZMM30,%ZMM31

(212) 0x4305c9 VMOVUPD	%ZMM31,(%R12,%RAX,1)

(212) 0x4305d0 VMULPD	(%R11,%RAX,1),%ZMM2,%ZMM0

(212) 0x4305d7 VMULPD	%ZMM29,%ZMM29,%ZMM18

(212) 0x4305dd VMULPD	%ZMM31,%ZMM0,%ZMM1

(212) 0x4305e3 VMULPD	%ZMM18,%ZMM1,%ZMM6

(212) 0x4305e9 VSQRTPD	%ZMM6,%ZMM7

(212) 0x4305ef VMOVUPD	%ZMM7,(%RBX,%RAX,1)

(212) 0x4305f6 ADD	$0x40,%RAX

(212) 0x4305fa CMP	%RAX,0x30(%RSP)

(212) 0x4305ff JE	430742

  (213) 0x430605 VMOVUPD	(%R11,%RAX,1),%ZMM20

  (213) 0x43060c VMULPD	(%R13,%RAX,1),%ZMM20,%ZMM21

  (213) 0x430614 VDIVPD	%ZMM20,%ZMM4,%ZMM19

  (213) 0x43061a VMULPD	%ZMM3,%ZMM21,%ZMM22

  (213) 0x430620 VMOVUPD	%ZMM22,(%R12,%RAX,1)

  (213) 0x430627 VMULPD	(%R11,%RAX,1),%ZMM2,%ZMM0

  (213) 0x43062e VMULPD	%ZMM19,%ZMM19,%ZMM23

  (213) 0x430634 VMULPD	%ZMM22,%ZMM0,%ZMM1

  (213) 0x43063a VMULPD	%ZMM23,%ZMM1,%ZMM6

  (213) 0x430640 VSQRTPD	%ZMM6,%ZMM7

  (213) 0x430646 VMOVUPD	%ZMM7,(%RBX,%RAX,1)

  (213) 0x43064d VMOVUPD	0x40(%R11,%RAX,1),%ZMM24

  (213) 0x430655 VMULPD	0x40(%R13,%RAX,1),%ZMM24,%ZMM26

  (213) 0x43065d VDIVPD	%ZMM24,%ZMM4,%ZMM25

  (213) 0x430663 VMULPD	%ZMM3,%ZMM26,%ZMM27

  (213) 0x430669 VMOVUPD	%ZMM27,0x40(%R12,%RAX,1)

  (213) 0x430671 VMULPD	0x40(%R11,%RAX,1),%ZMM2,%ZMM0

  (213) 0x430679 VMULPD	%ZMM25,%ZMM25,%ZMM28

  (213) 0x43067f VMULPD	%ZMM27,%ZMM0,%ZMM1

  (213) 0x430685 VMULPD	%ZMM28,%ZMM1,%ZMM6

  (213) 0x43068b VSQRTPD	%ZMM6,%ZMM7

  (213) 0x430691 VMOVUPD	%ZMM7,0x40(%RBX,%RAX,1)

  (213) 0x430699 VMOVUPD	0x80(%R11,%RAX,1),%ZMM29

  (213) 0x4306a1 VMULPD	0x80(%R13,%RAX,1),%ZMM29,%ZMM31

  (213) 0x4306a9 VDIVPD	%ZMM29,%ZMM4,%ZMM30

  (213) 0x4306af VMULPD	%ZMM3,%ZMM31,%ZMM18

  (213) 0x4306b5 VMOVUPD	%ZMM18,0x80(%R12,%RAX,1)

  (213) 0x4306bd VMULPD	0x80(%R11,%RAX,1),%ZMM2,%ZMM0

  (213) 0x4306c5 VMULPD	%ZMM30,%ZMM30,%ZMM20

  (213) 0x4306cb VMULPD	%ZMM18,%ZMM0,%ZMM1

  (213) 0x4306d1 VMULPD	%ZMM20,%ZMM1,%ZMM6

  (213) 0x4306d7 VSQRTPD	%ZMM6,%ZMM7

  (213) 0x4306dd VMOVUPD	%ZMM7,0x80(%RBX,%RAX,1)

  (213) 0x4306e5 VMOVUPD	0xc0(%R11,%RAX,1),%ZMM0

  (213) 0x4306ed VMULPD	0xc0(%R13,%RAX,1),%ZMM0,%ZMM1

  (213) 0x4306f5 VDIVPD	%ZMM0,%ZMM4,%ZMM19

  (213) 0x4306fb VMULPD	%ZMM3,%ZMM1,%ZMM6

  (213) 0x430701 VMOVUPD	%ZMM6,0xc0(%R12,%RAX,1)

  (213) 0x430709 VMULPD	0xc0(%R11,%RAX,1),%ZMM2,%ZMM7

  (213) 0x430711 VMULPD	%ZMM19,%ZMM19,%ZMM21

  (213) 0x430717 VMULPD	%ZMM6,%ZMM7,%ZMM0

  (213) 0x43071d VMULPD	%ZMM21,%ZMM0,%ZMM1

  (213) 0x430723 VSQRTPD	%ZMM1,%ZMM6

  (213) 0x430729 VMOVUPD	%ZMM6,0xc0(%RBX,%RAX,1)

  (213) 0x430731 ADD	$0x100,%RAX

  (213) 0x430737 CMP	%RAX,0x30(%RSP)

  (213) 0x43073c JNE	430605

(212) 0x430742 MOV	0x18(%RSP),%R11D

(212) 0x430747 MOV	0x1c(%RSP),%R13D

(212) 0x43074c MOV	%R11D,%ECX

(212) 0x43074f AND	$-0x8,%ECX

(212) 0x430752 ADD	%ECX,%R13D

(212) 0x430755 AND	$0x7,%R11D

(212) 0x430759 MOV	%R13D,0x3c(%RSP)

(212) 0x43075e JE	43091c

(212) 0x430764 MOV	0x38(%RSP),%R12D

(212) 0x430769 SUB	%ECX,%R12D

(212) 0x43076c LEA	0x1(%R12),%EBX

(212) 0x430771 CMP	$0x2,%R12D

(212) 0x430775 JBE	4307e2

(212) 0x430777 LEA	(%RSI,%RCX,1),%RAX

(212) 0x43077b LEA	(%RDI,%RCX,1),%R13

(212) 0x43077f LEA	(%R9,%RCX,1),%R12

(212) 0x430783 ADD	%R8,%RCX

(212) 0x430786 LEA	(%R15,%RAX,8),%R11

(212) 0x43078a VBROADCASTSD	0x722b5(%RIP),%YMM0

(212) 0x430793 MOV	%EBX,%EAX

(212) 0x430795 VMOVUPD	(%R11),%YMM4

(212) 0x43079a VMULPD	(%R14,%R13,8),%YMM4,%YMM2

(212) 0x4307a0 AND	$-0x4,%EAX

(212) 0x4307a3 ADD	%EAX,0x3c(%RSP)

(212) 0x4307a7 AND	$0x3,%EBX

(212) 0x4307aa VDIVPD	%YMM4,%YMM17,%YMM3

(212) 0x4307b0 VMULPD	%YMM16,%YMM2,%YMM7

(212) 0x4307b6 VMOVUPD	%YMM7,(%R10,%RCX,8)

(212) 0x4307bc VMULPD	(%R11),%YMM0,%YMM1

(212) 0x4307c1 VMOVQ	%XMM8,%RCX

(212) 0x4307c6 VMULPD	%YMM7,%YMM1,%YMM6

(212) 0x4307ca VMULPD	%YMM3,%YMM3,%YMM4

(212) 0x4307ce VMULPD	%YMM4,%YMM6,%YMM3

(212) 0x4307d2 VSQRTPD	%YMM3,%YMM2

(212) 0x4307d6 VMOVUPD	%YMM2,(%RCX,%R12,8)

(212) 0x4307dc JE	43091c

(212) 0x4307e2 VMOVQ	%XMM5,%RBX

(212) 0x4307e7 MOV	%RSI,%R11

(212) 0x4307ea MOV	%RDI,%R12

(212) 0x4307ed VMOVQ	%XMM5,%RCX

(212) 0x4307f2 SUB	%RBX,%R11

(212) 0x4307f5 SUB	%RBX,%R12

(212) 0x4307f8 MOV	%R9,%R13

(212) 0x4307fb MOV	%R8,%RBX

(212) 0x4307fe SUB	%RCX,%R13

(212) 0x430801 SUB	%RCX,%RBX

(212) 0x430804 MOVSXD	0x3c(%RSP),%RCX

(212) 0x430809 MOV	%R13,0x20(%RSP)

(212) 0x43080e LEA	(%RCX,%R12,1),%RAX

(212) 0x430812 LEA	(%R11,%RCX,1),%R13

(212) 0x430816 VMOVSD	(%R15,%R13,8),%XMM7

(212) 0x43081c VMULSD	(%R14,%RAX,8),%XMM7,%XMM0

(212) 0x430822 LEA	(%RCX,%RBX,1),%RAX

(212) 0x430826 VMULSD	%XMM10,%XMM0,%XMM6

(212) 0x43082b VMOVSD	%XMM6,(%R10,%RAX,8)

(212) 0x430831 VMULSD	(%R15,%R13,8),%XMM9,%XMM4

(212) 0x430837 MOV	0x20(%RSP),%R13

(212) 0x43083c VMOVQ	%XMM8,%RAX

(212) 0x430841 VDIVSD	%XMM7,%XMM11,%XMM1

(212) 0x430845 VMULSD	%XMM6,%XMM4,%XMM2

(212) 0x430849 VMULSD	%XMM1,%XMM1,%XMM3

(212) 0x43084d VMULSD	%XMM3,%XMM2,%XMM7

(212) 0x430851 VSQRTSD	%XMM7,%XMM7,%XMM7

(212) 0x430855 ADD	%R13,%RCX

(212) 0x430858 VMOVSD	%XMM7,(%RAX,%RCX,8)

(212) 0x43085d MOV	0x3c(%RSP),%ECX

(212) 0x430861 LEA	0x1(%RCX),%EAX

(212) 0x430864 CMP	%EAX,0x28(%RSP)

(212) 0x430868 JL	43091c

(212) 0x43086e MOVSXD	%EAX,%RCX

(212) 0x430871 LEA	(%R11,%RCX,1),%RAX

(212) 0x430875 VMOVSD	(%R15,%RAX,8),%XMM0

(212) 0x43087b VMOVQ	%RAX,%XMM1

(212) 0x430880 LEA	(%R12,%RCX,1),%RAX

(212) 0x430884 VDIVSD	%XMM0,%XMM11,%XMM6

(212) 0x430888 VMULSD	(%R14,%RAX,8),%XMM0,%XMM4

(212) 0x43088e LEA	(%RBX,%RCX,1),%RAX

(212) 0x430892 VMULSD	%XMM10,%XMM4,%XMM2

(212) 0x430897 ADD	%R13,%RCX

(212) 0x43089a VMOVSD	%XMM2,(%R10,%RAX,8)

(212) 0x4308a0 VMOVQ	%XMM1,%RAX

(212) 0x4308a5 VMULSD	%XMM6,%XMM6,%XMM1

(212) 0x4308a9 VMULSD	(%R15,%RAX,8),%XMM9,%XMM3

(212) 0x4308af VMOVQ	%XMM8,%RAX

(212) 0x4308b4 VMULSD	%XMM2,%XMM3,%XMM7

(212) 0x4308b8 VMULSD	%XMM1,%XMM7,%XMM0

(212) 0x4308bc VSQRTSD	%XMM0,%XMM0,%XMM0

(212) 0x4308c0 VMOVSD	%XMM0,(%RAX,%RCX,8)

(212) 0x4308c5 MOV	0x3c(%RSP),%EAX

(212) 0x4308c9 ADD	$0x2,%EAX

(212) 0x4308cc CMP	%EAX,0x28(%RSP)

(212) 0x4308d0 JL	43091c

(212) 0x4308d2 CLTQ

(212) 0x4308d4 ADD	%RAX,%R11

(212) 0x4308d7 ADD	%RAX,%R12

(212) 0x4308da ADD	%RAX,%RBX

(212) 0x4308dd ADD	%RAX,%R13

(212) 0x4308e0 VMOVSD	(%R15,%R11,8),%XMM6

(212) 0x4308e6 VMULSD	(%R14,%R12,8),%XMM6,%XMM2

(212) 0x4308ec VMULSD	%XMM10,%XMM2,%XMM3

(212) 0x4308f1 VMOVSD	%XMM3,(%R10,%RBX,8)

(212) 0x4308f7 VMULSD	(%R15,%R11,8),%XMM9,%XMM7

(212) 0x4308fd VMOVQ	%XMM8,%R11

(212) 0x430902 VDIVSD	%XMM6,%XMM11,%XMM4

(212) 0x430906 VMULSD	%XMM3,%XMM7,%XMM1

(212) 0x43090a VMULSD	%XMM4,%XMM4,%XMM0

(212) 0x43090e VMULSD	%XMM0,%XMM1,%XMM6

(212) 0x430912 VSQRTSD	%XMM6,%XMM6,%XMM6

(212) 0x430916 VMOVSD	%XMM6,(%R11,%R13,8)

(212) 0x43091c VMOVQ	%XMM13,%R12

(212) 0x430921 VMOVQ	%XMM14,%RBX

(212) 0x430926 INC	%EDX

(212) 0x430928 VMOVQ	%XMM12,%RCX

(212) 0x43092d VMOVQ	%XMM15,%RAX

(212) 0x430932 ADD	%R12,%RSI

(212) 0x430935 ADD	%RBX,%RDI

(212) 0x430938 ADD	%RCX,%R8

(212) 0x43093b ADD	%RAX,%R9

(212) 0x43093e CMP	%EDX,0x2c(%RSP)

(212) 0x430942 JG	4304b0

0x430948 MOV	0x14(%RSP),%R13D

0x43094d MOV	0x8(%RSP),%R12

0x430952 VZEROUPPER

0x430955 MOV	%R13D,%EBX

0x430958 MOV	%EBX,0x80(%R12)

0x430960 LEA	-0x28(%RBP),%RSP

0x430964 POP	%RBX

0x430965 POP	%R12

0x430967 POP	%R13

0x430969 POP	%R14

0x43096b POP	%R15

0x43096d POP	%RBP

0x43096e RET

0x43096f NOP

(212) 0x430970 MOV	0x1c(%RSP),%EBX

(212) 0x430974 XOR	%ECX,%ECX

(212) 0x430976 MOV	%EBX,0x3c(%RSP)

(212) 0x43097a JMP	430764

0x43097f INC	%EAX

0x430981 XOR	%EDX,%EDX

0x430983 JMP	430386

0x430988 XOR	%ESI,%ESI

0x43098a NOPW	(%RAX,%RAX,1)

(211) 0x430990 INC	%EDX

(211) 0x430992 CMP	%R13D,%EAX

(211) 0x430995 JE	4309b1

(211) 0x430997 CMP	%EDX,0x2c(%RSP)

(211) 0x43099b JG	430990

0x43099d TEST	%SIL,%SIL

0x4309a0 JNE	430958

0x4309a2 LEA	-0x28(%RBP),%RSP

0x4309a6 POP	%RBX

0x4309a7 POP	%R12

0x4309a9 POP	%R13

0x4309ab POP	%R14

0x4309ad POP	%R15

0x4309af POP	%RBP

0x4309b0 RET

(211) 0x4309b1 CMP	%EDX,0x2c(%RSP)

(211) 0x4309b5 JLE	430955

(211) 0x4309b7 MOV	%EAX,%EBX

(211) 0x4309b9 MOV	$0x1,%ESI

(211) 0x4309be JMP	430990

Coverage (%)	Name	Source Location	Module
►95.70+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.70+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	ideal_gas_kernel	ideal_gas_kernel.f90:61	exec
○	ideal_gas	ideal_gas.f90:58	exec
○	timestep	timestep.f90:60	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec
►1.63+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	ideal_gas_kernel	ideal_gas_kernel.f90:61	exec
○	ideal_gas	ideal_gas.f90:58	exec
○	pdv	PdV.f90:124	exec
○	hydro	hydro.f90:56	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.88 to 3.25 cycles (4.58x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:48
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 180 bytes. The binary function is storing 44 bytes.

General properties

nb instructions	119
nb uops	119
loop length	445
used x86 registers	16
used mmx registers	0
used xmm registers	11
used ymm registers	2
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.88 cycles
front end	14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.17	8.17	8.17	8.17	8.17	8.17	9.00	9.00	9.00	9.00	0.00	1.00	1.00	0.00	3.00	3.00
cycles	8.17	8.17	8.17	8.17	8.17	8.17	9.00	9.00	9.00	9.00	0.00	1.00	1.00	0.00	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	14.88
Dispatch	9.00
DIV/SQRT	6.00
Overall L1	14.88

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	4%

Vector efficiency ratios

INT

all	10%
load	11%
store	7%
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	7%
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.88 cycles. At this rate:

4% of peak load performance is reached (12.10 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.88 to 9.00 cycles (1.65x speedup).

ASM code

In the binary file, the address of the function is: 430340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%R12),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 43097f <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x63f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 430960 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R12),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x40(%R12),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x50(%R12),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R14D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x60(%R12),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x70(%R12),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD %EDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ 0x28(%R12),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%R12),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x38(%R12),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R12),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVSXD (%RSI),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
VMOVQ %XMM12,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %R13,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %RSI,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD 0x48(%R12),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
IMUL %RCX,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV %R10,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD 0x58(%R12),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%R14),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
ADD 0x68(%R12),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
ADD 0x78(%R12),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R11,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R13,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R14D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R10D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMOVLE %EAX,%R13D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
JG 430988 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x648>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R10D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x72104(%RIP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x725d4(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM11,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R14),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBROADCASTSD %XMM10,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R10D,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SHR $0x3,%R10D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
VMOVSD 0x725b1(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R13D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R12,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x6,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R10,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM7,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x14(%RSP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x8(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %R13D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %EBX,0x80(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 430386 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x46>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
TEST %SIL,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 430958 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x618>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.88 to 3.25 cycles (4.58x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:48
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 180 bytes. The binary function is storing 44 bytes.

General properties

nb instructions	119
nb uops	119
loop length	445
used x86 registers	16
used mmx registers	0
used xmm registers	11
used ymm registers	2
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.88 cycles
front end	14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.17	8.17	8.17	8.17	8.17	8.17	9.00	9.00	9.00	9.00	0.00	1.00	1.00	0.00	3.00	3.00
cycles	8.17	8.17	8.17	8.17	8.17	8.17	9.00	9.00	9.00	9.00	0.00	1.00	1.00	0.00	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	14.88
Dispatch	9.00
DIV/SQRT	6.00
Overall L1	14.88

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	4%

Vector efficiency ratios

INT

all	10%
load	11%
store	7%
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	7%
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.88 cycles. At this rate:

4% of peak load performance is reached (12.10 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 430340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%R12),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 43097f <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x63f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 430960 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R12),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x40(%R12),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x50(%R12),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R14D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x60(%R12),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x70(%R12),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD %EDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ 0x28(%R12),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%R12),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x38(%R12),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R12),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVSXD (%RSI),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM13,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
VMOVQ %XMM12,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %R13,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %RSI,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD 0x48(%R12),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
IMUL %RCX,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV %R10,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD 0x58(%R12),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%R14),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
ADD 0x68(%R12),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
ADD 0x78(%R12),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R11,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R13,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R14D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R10D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMOVLE %EAX,%R13D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
JG 430988 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x648>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R10D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x72104(%RIP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x725d4(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM11,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R14),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBROADCASTSD %XMM10,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R10D,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SHR $0x3,%R10D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
VMOVSD 0x725b1(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R13D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R12,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x6,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R10,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM7,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x14(%RSP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x8(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %R13D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %EBX,0x80(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 430386 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x46>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
TEST %SIL,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 430958 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x618>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0–	5.56	2.05
▼Loop 212 - ideal_gas_kernel.f90:48-55 - exec–	0.01	0.01
○Loop 213 - ideal_gas_kernel.f90:50-55 - exec	5.55	2.04
○Loop 211 - ideal_gas_kernel.f90:45-48 - exec	0.00	0.00

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Type of elements and instruction set

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