OV - exec - Function __revert_kernel_module_MOD_revert_kernel._omp

	Function: __revert_kernel_module_MOD_revert_kernel._omp_fn.0	Module: exec	Source: revert_kernel.f90:41-48	Coverage (incl. loops): 2.62% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90: 41 - 48

--------------------------------------------------------------------------------

41:     !$OMP PARALLEL

42:

43:     !$OMP DO

44:     DO k=y_min,y_max

45:     !$OMP SIMD

46:       DO j=x_min,x_max

47:         density1(j,k)=density0(j,k)

48:         energy1(j,k)=energy0(j,k)

0x43cca0 PUSH	%RBP

0x43cca1 MOV	%RSP,%RBP

0x43cca4 PUSH	%R15

0x43cca6 PUSH	%R14

0x43cca8 PUSH	%R13

0x43ccaa PUSH	%R12

0x43ccac PUSH	%RBX

0x43ccad MOV	%RDI,%R12

0x43ccb0 AND	$-0x40,%RSP

0x43ccb4 SUB	$0x40,%RSP

0x43ccb8 MOV	0x10(%RDI),%RAX

0x43ccbc MOV	(%RAX),%R14D

0x43ccbf CALL	402370 <@plt_start@+0x350>

0x43ccc4 MOV	%EAX,%R13D

0x43ccc7 CALL	4022e0 <@plt_start@+0x2c0>

0x43cccc MOV	0x18(%R12),%RDX

0x43ccd1 MOV	%EAX,%ECX

0x43ccd3 MOV	(%RDX),%EAX

0x43ccd5 INC	%EAX

0x43ccd7 SUB	%R14D,%EAX

0x43ccda CLTD

0x43ccdb IDIV	%R13D

0x43ccde CMP	%EDX,%ECX

0x43cce0 JL	43d202

0x43cce6 IMUL	%EAX,%ECX

0x43cce9 ADD	%ECX,%EDX

0x43cceb ADD	%EDX,%EAX

0x43cced CMP	%EAX,%EDX

0x43ccef JGE	43d1e0

0x43ccf5 MOV	(%R12),%RSI

0x43ccf9 VMOVQ	0x40(%R12),%XMM8

0x43cd00 MOV	0x8(%R12),%RDI

0x43cd05 VMOVQ	0x50(%R12),%XMM9

0x43cd0c ADD	%R14D,%EAX

0x43cd0f ADD	%R14D,%EDX

0x43cd12 VMOVQ	0x60(%R12),%XMM7

0x43cd19 VMOVQ	0x70(%R12),%XMM6

0x43cd20 MOV	%EAX,0x2c(%RSP)

0x43cd24 MOVSXD	%EDX,%RAX

0x43cd27 VMOVQ	0x28(%R12),%XMM0

0x43cd2e VMOVQ	0x30(%R12),%XMM3

0x43cd35 VMOVQ	0x38(%R12),%XMM4

0x43cd3c MOV	0x20(%R12),%R15

0x43cd41 MOVSXD	(%RSI),%R10

0x43cd44 MOV	0x48(%R12),%RSI

0x43cd49 MOV	(%RDI),%R11D

0x43cd4c MOV	0x58(%R12),%RDI

0x43cd51 VMOVQ	%XMM8,%R8

0x43cd56 VMOVQ	%XMM9,%R9

0x43cd5b IMUL	%RAX,%R8

0x43cd5f VMOVQ	%XMM7,%R13

0x43cd64 IMUL	%RAX,%R9

0x43cd68 IMUL	%RAX,%R13

0x43cd6c ADD	%R10,%RSI

0x43cd6f ADD	%R10,%RDI

0x43cd72 LEA	0x1(%R11),%ECX

0x43cd76 MOV	%R10D,0x24(%RSP)

0x43cd7b ADD	%R8,%RSI

0x43cd7e MOV	0x68(%R12),%R8

0x43cd83 ADD	%R9,%RDI

0x43cd86 MOV	0x78(%R12),%R9

0x43cd8b MOV	%R11D,0x28(%RSP)

0x43cd90 ADD	%R10,%R8

0x43cd93 ADD	%R10,%R9

0x43cd96 ADD	%R13,%R8

0x43cd99 VMOVQ	%XMM6,%R13

0x43cd9e IMUL	%R13,%RAX

0x43cda2 ADD	%RAX,%R9

0x43cda5 CMP	%R11D,%R10D

0x43cda8 MOV	%R10D,%EAX

0x43cdab CMOVLE	%ECX,%EAX

0x43cdae JG	43d20b

0x43cdb4 SUB	%R10D,%R11D

0x43cdb7 VMOVQ	%R10,%XMM2

0x43cdbc MOV	%R15,%R10

0x43cdbf VMOVQ	%XMM0,%R15

0x43cdc4 LEA	0x1(%R11),%R14D

0x43cdc8 MOV	%R11D,0x38(%RSP)

0x43cdcd MOV	%EAX,0x18(%RSP)

0x43cdd1 MOV	%R12,0x10(%RSP)

0x43cdd6 MOV	%R14D,%EBX

0x43cdd9 MOV	%R14D,%R11D

0x43cddc AND	$0x7,%R14D

0x43cde0 SHR	$0x3,%EBX

0x43cde3 MOV	%R14D,0x1c(%RSP)

0x43cde8 VMOVQ	%XMM3,%R14

0x43cded SAL	$0x6,%RBX

0x43cdf1 AND	$-0x8,%R11D

0x43cdf5 MOV	%RBX,0x30(%RSP)

0x43cdfa MOV	%R11D,0x20(%RSP)

0x43cdff NOP

(310) 0x43ce00 CMPL	$0x6,0x38(%RSP)

(310) 0x43ce05 JBE	43d1f0

(310) 0x43ce0b MOV	0x30(%RSP),%RCX

(310) 0x43ce10 VMOVQ	%XMM4,%RAX

(310) 0x43ce15 LEA	(%R10,%RSI,8),%R13

(310) 0x43ce19 LEA	(%R15,%RDI,8),%R12

(310) 0x43ce1d LEA	(%RAX,%R9,8),%R11

(310) 0x43ce21 XOR	%EAX,%EAX

(310) 0x43ce23 LEA	(%R14,%R8,8),%RBX

(310) 0x43ce27 SUB	$0x40,%RCX

(310) 0x43ce2b SHR	$0x6,%RCX

(310) 0x43ce2f INC	%RCX

(310) 0x43ce32 AND	$0x7,%ECX

(310) 0x43ce35 JE	43cf5b

(310) 0x43ce3b CMP	$0x1,%RCX

(310) 0x43ce3f JE	43cf2f

(310) 0x43ce45 CMP	$0x2,%RCX

(310) 0x43ce49 JE	43cf0e

(310) 0x43ce4f CMP	$0x3,%RCX

(310) 0x43ce53 JE	43ceed

(310) 0x43ce59 CMP	$0x4,%RCX

(310) 0x43ce5d JE	43cecc

(310) 0x43ce5f CMP	$0x5,%RCX

(310) 0x43ce63 JE	43ceab

(310) 0x43ce65 CMP	$0x6,%RCX

(310) 0x43ce69 JE	43ce8a

(310) 0x43ce6b VMOVUPD	(%R13),%ZMM5

(310) 0x43ce72 MOV	$0x40,%EAX

(310) 0x43ce77 VMOVUPD	%ZMM5,(%R12)

(310) 0x43ce7e VMOVUPD	(%RBX),%ZMM1

(310) 0x43ce84 VMOVUPD	%ZMM1,(%R11)

(310) 0x43ce8a VMOVUPD	(%R13,%RAX,1),%ZMM10

(310) 0x43ce92 VMOVUPD	%ZMM10,(%R12,%RAX,1)

(310) 0x43ce99 VMOVUPD	(%RBX,%RAX,1),%ZMM11

(310) 0x43cea0 VMOVUPD	%ZMM11,(%R11,%RAX,1)

(310) 0x43cea7 ADD	$0x40,%RAX

(310) 0x43ceab VMOVUPD	(%R13,%RAX,1),%ZMM12

(310) 0x43ceb3 VMOVUPD	%ZMM12,(%R12,%RAX,1)

(310) 0x43ceba VMOVUPD	(%RBX,%RAX,1),%ZMM13

(310) 0x43cec1 VMOVUPD	%ZMM13,(%R11,%RAX,1)

(310) 0x43cec8 ADD	$0x40,%RAX

(310) 0x43cecc VMOVUPD	(%R13,%RAX,1),%ZMM14

(310) 0x43ced4 VMOVUPD	%ZMM14,(%R12,%RAX,1)

(310) 0x43cedb VMOVUPD	(%RBX,%RAX,1),%ZMM15

(310) 0x43cee2 VMOVUPD	%ZMM15,(%R11,%RAX,1)

(310) 0x43cee9 ADD	$0x40,%RAX

(310) 0x43ceed VMOVUPD	(%R13,%RAX,1),%ZMM0

(310) 0x43cef5 VMOVUPD	%ZMM0,(%R12,%RAX,1)

(310) 0x43cefc VMOVUPD	(%RBX,%RAX,1),%ZMM3

(310) 0x43cf03 VMOVUPD	%ZMM3,(%R11,%RAX,1)

(310) 0x43cf0a ADD	$0x40,%RAX

(310) 0x43cf0e VMOVUPD	(%R13,%RAX,1),%ZMM5

(310) 0x43cf16 VMOVUPD	%ZMM5,(%R12,%RAX,1)

(310) 0x43cf1d VMOVUPD	(%RBX,%RAX,1),%ZMM1

(310) 0x43cf24 VMOVUPD	%ZMM1,(%R11,%RAX,1)

(310) 0x43cf2b ADD	$0x40,%RAX

(310) 0x43cf2f VMOVUPD	(%R13,%RAX,1),%ZMM10

(310) 0x43cf37 VMOVUPD	%ZMM10,(%R12,%RAX,1)

(310) 0x43cf3e VMOVUPD	(%RBX,%RAX,1),%ZMM11

(310) 0x43cf45 VMOVUPD	%ZMM11,(%R11,%RAX,1)

(310) 0x43cf4c ADD	$0x40,%RAX

(310) 0x43cf50 CMP	%RAX,0x30(%RSP)

(310) 0x43cf55 JE	43d069

  (311) 0x43cf5b VMOVUPD	(%R13,%RAX,1),%ZMM12

  (311) 0x43cf63 VMOVUPD	%ZMM12,(%R12,%RAX,1)

  (311) 0x43cf6a VMOVUPD	(%RBX,%RAX,1),%ZMM13

  (311) 0x43cf71 VMOVUPD	%ZMM13,(%R11,%RAX,1)

  (311) 0x43cf78 VMOVUPD	0x40(%R13,%RAX,1),%ZMM14

  (311) 0x43cf80 VMOVUPD	%ZMM14,0x40(%R12,%RAX,1)

  (311) 0x43cf88 VMOVUPD	0x40(%RBX,%RAX,1),%ZMM15

  (311) 0x43cf90 VMOVUPD	%ZMM15,0x40(%R11,%RAX,1)

  (311) 0x43cf98 VMOVUPD	0x80(%R13,%RAX,1),%ZMM0

  (311) 0x43cfa0 VMOVUPD	%ZMM0,0x80(%R12,%RAX,1)

  (311) 0x43cfa8 VMOVUPD	0x80(%RBX,%RAX,1),%ZMM3

  (311) 0x43cfb0 VMOVUPD	%ZMM3,0x80(%R11,%RAX,1)

  (311) 0x43cfb8 VMOVUPD	0xc0(%R13,%RAX,1),%ZMM5

  (311) 0x43cfc0 VMOVUPD	%ZMM5,0xc0(%R12,%RAX,1)

  (311) 0x43cfc8 VMOVUPD	0xc0(%RBX,%RAX,1),%ZMM1

  (311) 0x43cfd0 VMOVUPD	%ZMM1,0xc0(%R11,%RAX,1)

  (311) 0x43cfd8 VMOVUPD	0x100(%R13,%RAX,1),%ZMM10

  (311) 0x43cfe0 VMOVUPD	%ZMM10,0x100(%R12,%RAX,1)

  (311) 0x43cfe8 VMOVUPD	0x100(%RBX,%RAX,1),%ZMM11

  (311) 0x43cff0 VMOVUPD	%ZMM11,0x100(%R11,%RAX,1)

  (311) 0x43cff8 VMOVUPD	0x140(%R13,%RAX,1),%ZMM12

  (311) 0x43d000 VMOVUPD	%ZMM12,0x140(%R12,%RAX,1)

  (311) 0x43d008 VMOVUPD	0x140(%RBX,%RAX,1),%ZMM13

  (311) 0x43d010 VMOVUPD	%ZMM13,0x140(%R11,%RAX,1)

  (311) 0x43d018 VMOVUPD	0x180(%R13,%RAX,1),%ZMM14

  (311) 0x43d020 VMOVUPD	%ZMM14,0x180(%R12,%RAX,1)

  (311) 0x43d028 VMOVUPD	0x180(%RBX,%RAX,1),%ZMM15

  (311) 0x43d030 VMOVUPD	%ZMM15,0x180(%R11,%RAX,1)

  (311) 0x43d038 VMOVUPD	0x1c0(%R13,%RAX,1),%ZMM0

  (311) 0x43d040 VMOVUPD	%ZMM0,0x1c0(%R12,%RAX,1)

  (311) 0x43d048 VMOVUPD	0x1c0(%RBX,%RAX,1),%ZMM3

  (311) 0x43d050 VMOVUPD	%ZMM3,0x1c0(%R11,%RAX,1)

  (311) 0x43d058 ADD	$0x200,%RAX

  (311) 0x43d05e CMP	%RAX,0x30(%RSP)

  (311) 0x43d063 JNE	43cf5b

(310) 0x43d069 MOV	0x20(%RSP),%R12D

(310) 0x43d06e MOV	0x24(%RSP),%EBX

(310) 0x43d072 MOV	0x1c(%RSP),%R11D

(310) 0x43d077 MOV	%R12D,%R13D

(310) 0x43d07a ADD	%EBX,%R12D

(310) 0x43d07d MOV	%R12D,0x3c(%RSP)

(310) 0x43d082 TEST	%R11D,%R11D

(310) 0x43d085 JE	43d19e

(310) 0x43d08b MOV	0x38(%RSP),%ECX

(310) 0x43d08f SUB	%R13D,%ECX

(310) 0x43d092 LEA	0x1(%RCX),%EAX

(310) 0x43d095 CMP	$0x2,%ECX

(310) 0x43d098 JBE	43d0db

(310) 0x43d09a LEA	(%RSI,%R13,1),%R12

(310) 0x43d09e LEA	(%RDI,%R13,1),%RBX

(310) 0x43d0a2 LEA	(%R8,%R13,1),%R11

(310) 0x43d0a6 VMOVQ	%XMM4,%RCX

(310) 0x43d0ab VMOVUPD	(%R10,%R12,8),%YMM5

(310) 0x43d0b1 ADD	%R9,%R13

(310) 0x43d0b4 VMOVUPD	%YMM5,(%R15,%RBX,8)

(310) 0x43d0ba VMOVUPD	(%R14,%R11,8),%YMM1

(310) 0x43d0c0 VMOVUPD	%YMM1,(%RCX,%R13,8)

(310) 0x43d0c6 MOV	%EAX,%R13D

(310) 0x43d0c9 AND	$-0x4,%R13D

(310) 0x43d0cd ADD	%R13D,0x3c(%RSP)

(310) 0x43d0d2 AND	$0x3,%EAX

(310) 0x43d0d5 JE	43d19e

(310) 0x43d0db MOVSXD	0x3c(%RSP),%RCX

(310) 0x43d0e0 VMOVQ	%XMM2,%RAX

(310) 0x43d0e5 MOV	%RSI,%R13

(310) 0x43d0e8 MOV	%RDI,%R12

(310) 0x43d0eb SUB	%RAX,%R13

(310) 0x43d0ee MOV	%R8,%RBX

(310) 0x43d0f1 MOV	%R9,%R11

(310) 0x43d0f4 SUB	%RAX,%R12

(310) 0x43d0f7 SUB	%RAX,%RBX

(310) 0x43d0fa SUB	%RAX,%R11

(310) 0x43d0fd LEA	(%R13,%RCX,1),%RAX

(310) 0x43d102 VMOVSD	(%R10,%RAX,8),%XMM10

(310) 0x43d108 LEA	(%RCX,%R12,1),%RAX

(310) 0x43d10c VMOVSD	%XMM10,(%R15,%RAX,8)

(310) 0x43d112 LEA	(%RCX,%RBX,1),%RAX

(310) 0x43d116 ADD	%R11,%RCX

(310) 0x43d119 VMOVSD	(%R14,%RAX,8),%XMM11

(310) 0x43d11f VMOVQ	%XMM4,%RAX

(310) 0x43d124 VMOVSD	%XMM11,(%RAX,%RCX,8)

(310) 0x43d129 MOV	0x3c(%RSP),%ECX

(310) 0x43d12d LEA	0x1(%RCX),%EAX

(310) 0x43d130 CMP	%EAX,0x28(%RSP)

(310) 0x43d134 JL	43d19e

(310) 0x43d136 MOVSXD	%EAX,%RCX

(310) 0x43d139 LEA	(%R13,%RCX,1),%RAX

(310) 0x43d13e VMOVSD	(%R10,%RAX,8),%XMM12

(310) 0x43d144 LEA	(%R12,%RCX,1),%RAX

(310) 0x43d148 VMOVSD	%XMM12,(%R15,%RAX,8)

(310) 0x43d14e LEA	(%RBX,%RCX,1),%RAX

(310) 0x43d152 ADD	%R11,%RCX

(310) 0x43d155 VMOVSD	(%R14,%RAX,8),%XMM13

(310) 0x43d15b VMOVQ	%XMM4,%RAX

(310) 0x43d160 VMOVSD	%XMM13,(%RAX,%RCX,8)

(310) 0x43d165 MOV	0x3c(%RSP),%EAX

(310) 0x43d169 ADD	$0x2,%EAX

(310) 0x43d16c CMP	%EAX,0x28(%RSP)

(310) 0x43d170 JL	43d19e

(310) 0x43d172 CLTQ

(310) 0x43d174 ADD	%RAX,%R13

(310) 0x43d177 ADD	%RAX,%R12

(310) 0x43d17a ADD	%RAX,%RBX

(310) 0x43d17d ADD	%RAX,%R11

(310) 0x43d180 VMOVSD	(%R10,%R13,8),%XMM14

(310) 0x43d186 VMOVQ	%XMM4,%R13

(310) 0x43d18b VMOVSD	%XMM14,(%R15,%R12,8)

(310) 0x43d191 VMOVSD	(%R14,%RBX,8),%XMM15

(310) 0x43d197 VMOVSD	%XMM15,(%R13,%R11,8)

(310) 0x43d19e VMOVQ	%XMM8,%R12

(310) 0x43d1a3 VMOVQ	%XMM9,%RBX

(310) 0x43d1a8 INC	%EDX

(310) 0x43d1aa VMOVQ	%XMM7,%R11

(310) 0x43d1af VMOVQ	%XMM6,%RCX

(310) 0x43d1b4 ADD	%R12,%RSI

(310) 0x43d1b7 ADD	%RBX,%RDI

(310) 0x43d1ba ADD	%R11,%R8

(310) 0x43d1bd ADD	%RCX,%R9

(310) 0x43d1c0 CMP	%EDX,0x2c(%RSP)

(310) 0x43d1c4 JG	43ce00

0x43d1ca MOV	0x18(%RSP),%EAX

0x43d1ce MOV	0x10(%RSP),%R12

0x43d1d3 VZEROUPPER

0x43d1d6 MOV	%EAX,%EBX

0x43d1d8 MOV	%EBX,0x80(%R12)

0x43d1e0 LEA	-0x28(%RBP),%RSP

0x43d1e4 POP	%RBX

0x43d1e5 POP	%R12

0x43d1e7 POP	%R13

0x43d1e9 POP	%R14

0x43d1eb POP	%R15

0x43d1ed POP	%RBP

0x43d1ee RET

0x43d1ef NOP

(310) 0x43d1f0 MOV	0x24(%RSP),%R12D

(310) 0x43d1f5 XOR	%R13D,%R13D

(310) 0x43d1f8 MOV	%R12D,0x3c(%RSP)

(310) 0x43d1fd JMP	43d08b

0x43d202 INC	%EAX

0x43d204 XOR	%EDX,%EDX

0x43d206 JMP	43cce6

0x43d20b XOR	%R10D,%R10D

0x43d20e XCHG	%AX,%AX

(309) 0x43d210 INC	%EDX

(309) 0x43d212 CMP	%EAX,%ECX

(309) 0x43d214 JE	43d230

(309) 0x43d216 CMP	%EDX,0x2c(%RSP)

(309) 0x43d21a JG	43d210

0x43d21c TEST	%R10B,%R10B

0x43d21f JNE	43d1d8

0x43d221 LEA	-0x28(%RBP),%RSP

0x43d225 POP	%RBX

0x43d226 POP	%R12

0x43d228 POP	%R13

0x43d22a POP	%R14

0x43d22c POP	%R15

0x43d22e POP	%RBP

0x43d22f RET

(309) 0x43d230 CMP	%EDX,0x2c(%RSP)

(309) 0x43d234 JLE	43d1d6

(309) 0x43d236 MOV	%ECX,%EBX

(309) 0x43d238 MOV	$0x1,%R10D

(309) 0x43d23e JMP	43d210

Coverage (%)	Name	Source Location	Module
►95.60+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.51+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	revert_kernel	revert_kernel.f90:55	exec
○	revert	revert.f90:37	exec
○	pdv	PdV.f90:137	exec
○	hydro	hydro.f90:56	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	revert_kernel.f90:41-48
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:41-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 3.00 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 1.12 cycles (13.43x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:45
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 156 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	120
nb uops	120
loop length	424
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	3.00	3.00
cycles	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	15.00
Dispatch	8.50
DIV/SQRT	6.00
Overall L1	15.00

Vectorization ratios

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	5%

Vector efficiency ratios

all	10%
load	11%
store	7%
mul	10%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

4% of peak load performance is reached (10.40 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 8.50 cycles (1.76x speedup).

ASM code

In the binary file, the address of the function is: 43cca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%R12),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 43d202 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x562>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43d1e0 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x540>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R12),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x40(%R12),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x50(%R12),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R14D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x60(%R12),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x70(%R12),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %EAX,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVSXD %EDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x28(%R12),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%R12),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x38(%R12),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R12),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVSXD (%RSI),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x48(%R12),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %RAX,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
VMOVQ %XMM7,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %RAX,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %RAX,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %R10,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R10,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%R11),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R10D,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%R12),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R11D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD %R10,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R10,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R13,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVQ %XMM6,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R11D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMOVLE %ECX,%EAX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JG 43d20b <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x56b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %R10,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM0,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x1(%R11),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R12,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R14D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x3,%EBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOV %R14D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ %XMM3,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x6,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
AND $-0x8,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11D,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x18(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %EBX,0x80(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43cce6 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x46>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
TEST %R10B,%R10B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 43d1d8 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x538>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	revert_kernel.f90:41-48
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 3.00 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:45
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 156 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	120
nb uops	120
loop length	424
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	3.00	3.00
cycles	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	15.00
Dispatch	8.50
DIV/SQRT	6.00
Overall L1	15.00

Vectorization ratios

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	5%

Vector efficiency ratios

all	10%
load	11%
store	7%
mul	10%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

4% of peak load performance is reached (10.40 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 43cca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%R12),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 43d202 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x562>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43d1e0 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x540>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R12),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x40(%R12),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x50(%R12),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R14D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x60(%R12),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x70(%R12),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %EAX,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVSXD %EDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x28(%R12),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%R12),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x38(%R12),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R12),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVSXD (%RSI),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x48(%R12),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %RAX,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
VMOVQ %XMM7,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %RAX,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %RAX,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %R10,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R10,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%R11),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R10D,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%R12),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R11D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD %R10,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R10,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R13,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVQ %XMM6,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R11D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMOVLE %ECX,%EAX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JG 43d20b <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x56b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %R10,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM0,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x1(%R11),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R12,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R14D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x3,%EBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOV %R14D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ %XMM3,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x6,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
AND $-0x8,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11D,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x18(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %EBX,0x80(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43cce6 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x46>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
TEST %R10B,%R10B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 43d1d8 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x538>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼__revert_kernel_module_MOD_revert_kernel._omp_fn.0–	2.62	0.97
▼Loop 310 - revert_kernel.f90:45-48 - exec–	0.00	0.00
○Loop 311 - revert_kernel.f90:47-48 - exec	2.62	0.96
○Loop 309 - revert_kernel.f90:41-45 - exec	0.00	0.00

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