OV - exec - Loop 197

	Loop Id: 197	Module: exec	Source: field_summary_kernel.f90:62-72	Coverage: 0.10%

0x42aa90 MOV	%RBX,%RAX

0x42aa93 SUB	-0xd8(%RBP),%RAX

0x42aa9a XORPD	%XMM7,%XMM7

0x42aa9e MOV	-0xe0(%RBP),%RDI

0x42aaa5 MOV	%R13,%R15

0x42aaa8 MOV	%RSI,%R14

0x42aaab NOPL	(%RAX,%RAX,1)

  (196) 0x42aab0 MOVUPD	(%R15),%XMM8

  (196) 0x42aab5 MULPD	%XMM8,%XMM8

  (196) 0x42aaba MOVUPD	(%R14),%XMM9

  (196) 0x42aabf MULPD	%XMM9,%XMM9

  (196) 0x42aac4 ADDPD	%XMM8,%XMM9

  (196) 0x42aac9 MULPD	%XMM5,%XMM9

  (196) 0x42aace MOVAPD	%XMM9,%XMM8

  (196) 0x42aad3 UNPCKHPD	%XMM9,%XMM8

  (196) 0x42aad8 ADDSD	%XMM9,%XMM8

  (196) 0x42aadd ADDSD	%XMM8,%XMM7

  (196) 0x42aae2 ADD	%R8,%R14

  (196) 0x42aae5 ADD	%RDX,%R15

  (196) 0x42aae8 INC	%RDI

  (196) 0x42aaeb CMP	%R11,%RDI

  (196) 0x42aaee JLE	42aab0

0x42aaf0 MOVSD	(%RCX,%RAX,8),%XMM8

0x42aaf6 MOVSD	(%R12,%RAX,8),%XMM9

0x42aafc MULSD	%XMM8,%XMM9

0x42ab01 ADDSD	%XMM8,%XMM0

0x42ab06 ADDSD	%XMM9,%XMM1

0x42ab0b MOVSD	(%R10,%RAX,8),%XMM10

0x42ab11 MULSD	%XMM9,%XMM10

0x42ab16 ADDSD	%XMM10,%XMM3

0x42ab1b MULSD	%XMM6,%XMM7

0x42ab1f MULSD	%XMM9,%XMM7

0x42ab24 ADDSD	%XMM7,%XMM4

0x42ab28 MULSD	(%R9,%RAX,8),%XMM8

0x42ab2e ADDSD	%XMM8,%XMM2

0x42ab33 INC	%RBX

0x42ab36 ADD	$0x8,%RSI

0x42ab3a ADD	$0x8,%R13

0x42ab3e CMP	%EBX,-0x3c(%RBP)

0x42ab41 JNE	42aa90

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 62 - 72

--------------------------------------------------------------------------------

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

72:       ENDDO

Coverage (%)	Name	Source Location	Module
►53.21+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►35.75+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►4.27+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
►2.72+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	field_summary_kernel	field_summary_kernel.f90:77	exec
○	field_summary	field_summary.f90:70	exec
○	hydro	hydro.f90:81	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.72+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.15
CQA speedup if FP arith vectorized	2.19
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	micro-operation queue,
Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source	field_summary_kernel.f90:62-62,field_summary_kernel.f90:65-72
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.88
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	1.31
CQA cycles if fully vectorized	0.36
Front-end cycles	2.88
P0 cycles	0.83
P1 cycles	0.83
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	2.50
P13 cycles	2.50
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	23.00
Nb loads	7.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	3.48
Nb FLOP add-sub	5.00
Nb FLOP mul	5.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.09
Bytes prefetched	0.00
Bytes loaded	52.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	5.26
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	13.16
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.15
CQA speedup if FP arith vectorized	2.19
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	micro-operation queue,
Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source	field_summary_kernel.f90:62-62,field_summary_kernel.f90:65-72
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.88
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	1.31
CQA cycles if fully vectorized	0.36
Front-end cycles	2.88
P0 cycles	0.83
P1 cycles	0.83
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	2.50
P13 cycles	2.50
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	23.00
Nb loads	7.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	3.48
Nb FLOP add-sub	5.00
Nb FLOP mul	5.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.09
Bytes prefetched	0.00
Bytes loaded	52.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	5.26
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	13.16
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	field_summary_kernel.f90:62-72
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:62-72.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:62,65-72.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.88 to 2.50 cycles (1.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.88 to 0.36 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- use the vec-report option to understand why your loop was not vectorized. If "existence of vector dependences", try the IVDEP directive. If, using IVDEP, "vectorization possible but seems inefficient", try the VECTOR ALWAYS directive.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use axHost or xHost
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

10 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

5: addition or subtraction
5: multiply

The binary loop is loading 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	25
nb uops	23
loop length	119
used x86 registers	12
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.88 cycles
front end	2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.83	0.83	0.83	0.83	0.83	0.83	1.75	1.75	1.75	1.75	2.50	2.50	2.50	2.50	0.00	0.00
cycles	0.83	0.83	0.83	0.83	0.83	0.83	1.75	1.75	1.75	1.75	2.50	2.50	2.50	2.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.88
Dispatch	2.50
Data deps.	2.00
Overall L1	2.88

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	7%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	5%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.88 cycles. At this rate:

7% of peak load performance is reached (18.09 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.88 to 2.50 cycles (1.15x speedup).

ASM code

In the binary file, the address of the loop is: 42aa90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB -0xd8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XORPD %XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV -0xe0(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOVSD (%RCX,%RAX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD (%R12,%RAX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ADDSD %XMM9,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOVSD (%R10,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MULSD %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MULSD %XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM7,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MULSD (%R9,%RAX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %EBX,-0x3c(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 42aa90 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x380>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	field_summary_kernel.f90:62-72
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.88 to 2.50 cycles (1.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- use the vec-report option to understand why your loop was not vectorized. If "existence of vector dependences", try the IVDEP directive. If, using IVDEP, "vectorization possible but seems inefficient", try the VECTOR ALWAYS directive.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use axHost or xHost
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

10 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

5: addition or subtraction
5: multiply

The binary loop is loading 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	25
nb uops	23
loop length	119
used x86 registers	12
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.88 cycles
front end	2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.83	0.83	0.83	0.83	0.83	0.83	1.75	1.75	1.75	1.75	2.50	2.50	2.50	2.50	0.00	0.00
cycles	0.83	0.83	0.83	0.83	0.83	0.83	1.75	1.75	1.75	1.75	2.50	2.50	2.50	2.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.88
Dispatch	2.50
Data deps.	2.00
Overall L1	2.88

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	7%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	5%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.88 cycles. At this rate:

7% of peak load performance is reached (18.09 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 42aa90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB -0xd8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XORPD %XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV -0xe0(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOVSD (%RCX,%RAX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD (%R12,%RAX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ADDSD %XMM9,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOVSD (%R10,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MULSD %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MULSD %XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM7,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MULSD (%R9,%RAX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %EBX,-0x3c(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 42aa90 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x380>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code