OV - exec - Loop 61

	Loop Id: 61	Module: exec	Source: advec_cell_kernel.f90:204-248 [...]	Coverage: 3.51%

0x226c20 VADDSD	%XMM14,%XMM13,%XMM9

0x226c25 INC	%R9

0x226c28 VMULSD	%XMM8,%XMM9,%XMM8

0x226c2d VMOVSD	%XMM8,(%RBX,%RAX,8)    [8]

0x226c32 INC	%RAX

0x226c35 CMP	%RAX,0x30(%RSP)    [4]

0x226c3a JE	226b80

0x226c40 VMOVSD	(%R8,%RAX,8),%XMM8    [6]

0x226c46 LEA	(%RDI,%RAX,1),%RSI

0x226c4a VUCOMISD	%XMM8,%XMM0

0x226c4f JB	226c80

0x226c51 MOV	0x70(%RSP),%R10    [4]

0x226c56 MOV	0x38(%RSP),%RDX    [4]

0x226c5b MOV	0x48(%RSP),%R12    [4]

0x226c60 MOV	(%R10),%R11D    [5]

0x226c63 LEA	(%R14,%R9,1),%R10

0x226c67 ADD	$0x2,%R11D

0x226c6b CMP	%R11D,%EDX

0x226c6e CMOVL	%EDX,%R11D

0x226c72 MOV	%R11D,%R13D

0x226c75 JMP	226c9c

0x226c80 MOV	0x50(%RSP),%RDX    [4]

0x226c85 MOV	0xf0(%RSP),%R12    [4]

0x226c8d MOV	0x58(%RSP),%R11D    [4]

0x226c92 MOV	%RSI,%R10

0x226c95 LEA	(%R14,%R9,1),%RSI

0x226c99 MOV	%EDX,%R13D

0x226c9c ADD	0x28(%RSP),%R12    [4]

0x226ca1 MOV	0x10(%RSP),%RDX    [4]

0x226ca6 VANDPD	%XMM1,%XMM8,%XMM10

0x226caa MOVSXD	%R11D,%R11

0x226cad VMOVSD	(%RBP,%RSI,8),%XMM12    [9]

0x226cb3 VMOVSD	(%RBP,%R10,8),%XMM13    [9]

0x226cba ADD	%RAX,%R12

0x226cbd VMOVSD	(%RDX,%R12,8),%XMM9    [3]

0x226cc3 MOVSXD	%R13D,%R12

0x226cc6 SUB	(%RSP),%R12    [4]

0x226cca MOV	0x20(%RSP),%RDX    [4]

0x226ccf MOV	0x8(%RSP),%R13    [4]

0x226cd4 VSUBSD	%XMM12,%XMM13,%XMM15

0x226cd9 VXORPD	%XMM13,%XMM13,%XMM13

0x226cde IMUL	%R13,%R11

0x226ce2 VDIVSD	%XMM9,%XMM10,%XMM14

0x226ce7 VMOVAPD	%XMM7,%XMM10

0x226ceb VFMADD213SD	%XMM7,%XMM14,%XMM10

0x226cf0 VDIVSD	(%RDX,%R12,8),%XMM10,%XMM11    [2]

0x226cf6 MOV	0x18(%RSP),%R12    [4]

0x226cfb VSUBSD	%XMM14,%XMM2,%XMM10

0x226d00 ADD	%RAX,%R12

0x226d03 ADD	%R12,%R11

0x226d06 VSUBSD	(%RBP,%R11,8),%XMM12,%XMM16    [9]

0x226d0e VMULSD	%XMM16,%XMM15,%XMM17

0x226d14 VUCOMISD	%XMM13,%XMM17

0x226d1a VXORPD	%XMM17,%XMM17,%XMM17

0x226d20 JBE	226d6a

0x226d22 VANDPD	%XMM3,%XMM16,%XMM16

0x226d28 VANDPD	%XMM3,%XMM15,%XMM17

0x226d2e VSUBSD	%XMM14,%XMM5,%XMM14

0x226d33 VCMPSD	$0x1,%XMM15,%XMM0,%K1

0x226d3a VMULSD	%XMM11,%XMM16,%XMM18

0x226d40 VMINSD	%XMM16,%XMM17,%XMM16

0x226d46 VFMADD231SD	%XMM10,%XMM17,%XMM18

0x226d4c VXORPD	%XMM6,%XMM14,%XMM17

0x226d52 VMOVSD	%XMM14,%XMM17,%XMM17{%K1}

0x226d58 VMULSD	%XMM4,%XMM18,%XMM18

0x226d5e VMINSD	%XMM16,%XMM18,%XMM16

0x226d64 VMULSD	%XMM17,%XMM16,%XMM17

0x226d6a VADDSD	%XMM12,%XMM17,%XMM14

0x226d70 VMULSD	%XMM8,%XMM14,%XMM8

0x226d75 VMOVSD	%XMM8,(%RCX,%RAX,8)    [1]

0x226d7a VMOVSD	(%R15,%RSI,8),%XMM14    [7]

0x226d80 VMOVSD	(%R15,%R10,8),%XMM15    [7]

0x226d86 VSUBSD	(%R15,%R11,8),%XMM14,%XMM16    [7]

0x226d8d VSUBSD	%XMM14,%XMM15,%XMM15

0x226d92 VMULSD	%XMM16,%XMM15,%XMM17

0x226d98 VUCOMISD	%XMM13,%XMM17

0x226d9e JBE	226c20

0x226da4 VMULSD	%XMM9,%XMM12,%XMM9

0x226da9 VANDPD	%XMM3,%XMM8,%XMM13

0x226dad VANDPD	%XMM3,%XMM15,%XMM12

0x226db1 VCMPSD	$0x1,%XMM15,%XMM0,%K1

0x226db8 VDIVSD	%XMM9,%XMM13,%XMM9

0x226dbd VANDPD	%XMM3,%XMM16,%XMM13

0x226dc3 VMULSD	%XMM11,%XMM13,%XMM11

0x226dc8 VFMADD213SD	%XMM11,%XMM12,%XMM10

0x226dcd VMINSD	%XMM13,%XMM12,%XMM11

0x226dd2 VMULSD	%XMM4,%XMM10,%XMM10

0x226dd6 VMINSD	%XMM11,%XMM10,%XMM10

0x226ddb VSUBSD	%XMM9,%XMM5,%XMM9

0x226de0 VXORPD	%XMM6,%XMM9,%XMM11

0x226de4 VMOVSD	%XMM9,%XMM11,%XMM11{%K1}

0x226dea VMULSD	%XMM11,%XMM10,%XMM13

0x226def JMP	226c20

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 204 - 248

--------------------------------------------------------------------------------

204:           IF(vol_flux_y(j,k).GT.0.0)THEN

[...]

210:             upwind   =MIN(k+1,y_max+2)

[...]

216:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

217:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

218:           sigma4=2.0_8-sigmat

219:

220:           sigma=sigmat

221:           sigmav=sigmat

222:

223:           diffuw=density1(j,donor)-density1(j,upwind)

224:           diffdw=density1(j,downwind)-density1(j,donor)

225:           wind=1.0_8

226:           IF(diffdw.LE.0.0) wind=-1.0_8

227:           IF(diffuw*diffdw.GT.0.0)THEN

228:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

229:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

230:           ELSE

231:             limiter=0.0

232:           ENDIF

233:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

234:

235:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

236:           diffuw=energy1(j,donor)-energy1(j,upwind)

237:           diffdw=energy1(j,downwind)-energy1(j,donor)

238:           wind=1.0_8

239:           IF(diffdw.LE.0.0) wind=-1.0_8

240:           IF(diffuw*diffdw.GT.0.0)THEN

241:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

242:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

243:           ELSE

244:             limiter=0.0

245:           ENDIF

246:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

247:

248:         ENDDO

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.01
CQA speedup if FP arith vectorized	2.98
CQA speedup if fully vectorized	8.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1
Source	advec_cell_kernel.f90:204-204,advec_cell_kernel.f90:210-210,advec_cell_kernel.f90:216-248
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.13
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	4.06
CQA cycles if fully vectorized	1.50
Front-end cycles	12.13
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	11.25
P11 cycles	11.25
P12 cycles	11.25
P13 cycles	11.25
P14 cycles	2.50
P15 cycles	2.50
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	97.00
Nb loads	23.00
Nb stores	2.00
Nb stack references	13.00
FLOP/cycle	2.39
Nb FLOP add-sub	9.00
Nb FLOP mul	11.00
Nb FLOP fma	3.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.84
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	18.03
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	42.31
Vector-efficiency ratio all	14.45
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.07

Metric	Value
CQA speedup if no scalar integer	1.01
CQA speedup if FP arith vectorized	2.98
CQA speedup if fully vectorized	8.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1
Source	advec_cell_kernel.f90:204-204,advec_cell_kernel.f90:210-210,advec_cell_kernel.f90:216-248
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.13
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	4.06
CQA cycles if fully vectorized	1.50
Front-end cycles	12.13
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	11.25
P11 cycles	11.25
P12 cycles	11.25
P13 cycles	11.25
P14 cycles	2.50
P15 cycles	2.50
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	97.00
Nb loads	23.00
Nb stores	2.00
Nb stack references	13.00
FLOP/cycle	2.39
Nb FLOP add-sub	9.00
Nb FLOP mul	11.00
Nb FLOP fma	3.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.84
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	18.03
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	42.31
Vector-efficiency ratio all	14.45
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.07

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1
Source file and lines	advec_cell_kernel.f90:204-248
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:204,210,216-248.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.13 to 1.50 cycles (8.08x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:210
VUCOMISD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:204
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:227
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:240

Type of elements and instruction set

35 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

12: addition or subtraction (3 inside FMA instructions)
14: multiply (3 inside FMA instructions)
3: divide

The binary loop is loading 176 bytes (22 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually.

General properties

nb instructions	93
nb uops	97
loop length	459
used x86 registers	16
used mmx registers	0
used xmm registers	19
used ymm registers	0
used zmm registers	0
nb stack references	13
ADD-SUB / MUL ratio	0.82

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.13 cycles
front end	12.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	6.25	6.25	6.25	6.25	11.25	11.25	11.25	11.25	2.50	2.50
cycles	4.00	4.00	4.00	4.00	4.00	4.00	6.25	6.25	6.25	6.25	11.25	11.25	11.25	11.25	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.13
Dispatch	11.25
DIV/SQRT	12.00
Overall L1	12.13

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	19%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

INT+FP

all	18%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	42%

Vector efficiency ratios

INT

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.13 cycles. At this rate:

5% of peak load performance is reached (14.52 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.32 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 226c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VADDSD %XMM14,%XMM13,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD %XMM8,%XMM9,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM8,(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,0x30(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 226b80 <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1a90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R8,%RAX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RAX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VUCOMISD %XMM8,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 226c80 <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1b90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x70(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R10),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R14,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x2,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EDX,%R11D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R11D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 226c9c <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1bac>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xf0(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%R9,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD 0x28(%RSP),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x10(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VANDPD %XMM1,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVSXD %R11D,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RBP,%RSI,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RBP,%R10,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX,%R12,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD %R13D,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB (%RSP),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x20(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VSUBSD %XMM12,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
IMUL %R13,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VDIVSD %XMM9,%XMM10,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMOVAPD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD %XMM7,%XMM14,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD (%RDX,%R12,8),%XMM10,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOV 0x18(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VSUBSD %XMM14,%XMM2,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADD %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R12,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSUBSD (%RBP,%R11,8),%XMM12,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM16,%XMM15,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM13,%XMM17	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JBE 226d6a <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1c7a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VANDPD %XMM3,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM3,%XMM15,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSUBSD %XMM14,%XMM5,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VCMPSD $0x1,%XMM15,%XMM0,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM11,%XMM16,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM16,%XMM17,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231SD %XMM10,%XMM17,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %XMM6,%XMM14,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVSD %XMM14,%XMM17,%XMM17{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD %XMM4,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM16,%XMM18,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM17,%XMM16,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM17,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM8,%XMM14,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM8,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15,%RSI,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R15,%R10,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD (%R15,%R11,8),%XMM14,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM14,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM16,%XMM15,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM13,%XMM17	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 226c20 <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1b30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD %XMM9,%XMM12,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM3,%XMM8,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM3,%XMM15,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCMPSD $0x1,%XMM15,%XMM0,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM9,%XMM13,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VANDPD %XMM3,%XMM16,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULSD %XMM11,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM11,%XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM13,%XMM12,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM4,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM11,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM9,%XMM5,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VXORPD %XMM6,%XMM9,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVSD %XMM9,%XMM11,%XMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD %XMM11,%XMM10,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 226c20 <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1b30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1
Source file and lines	advec_cell_kernel.f90:204-248
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:210
VUCOMISD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:204
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:227
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:240

Type of elements and instruction set

35 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

12: addition or subtraction (3 inside FMA instructions)
14: multiply (3 inside FMA instructions)
3: divide

The binary loop is loading 176 bytes (22 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually.

General properties

nb instructions	93
nb uops	97
loop length	459
used x86 registers	16
used mmx registers	0
used xmm registers	19
used ymm registers	0
used zmm registers	0
nb stack references	13
ADD-SUB / MUL ratio	0.82

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.13 cycles
front end	12.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	6.25	6.25	6.25	6.25	11.25	11.25	11.25	11.25	2.50	2.50
cycles	4.00	4.00	4.00	4.00	4.00	4.00	6.25	6.25	6.25	6.25	11.25	11.25	11.25	11.25	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.13
Dispatch	11.25
DIV/SQRT	12.00
Overall L1	12.13

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	19%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

INT+FP

all	18%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	42%

Vector efficiency ratios

INT

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.13 cycles. At this rate:

5% of peak load performance is reached (14.52 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.32 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 226c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VADDSD %XMM14,%XMM13,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD %XMM8,%XMM9,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM8,(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,0x30(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 226b80 <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1a90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R8,%RAX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RAX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VUCOMISD %XMM8,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 226c80 <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1b90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x70(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R10),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R14,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x2,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EDX,%R11D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R11D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 226c9c <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1bac>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xf0(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%R9,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD 0x28(%RSP),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x10(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VANDPD %XMM1,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVSXD %R11D,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RBP,%RSI,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RBP,%R10,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX,%R12,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD %R13D,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB (%RSP),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x20(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VSUBSD %XMM12,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
IMUL %R13,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VDIVSD %XMM9,%XMM10,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMOVAPD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD %XMM7,%XMM14,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD (%RDX,%R12,8),%XMM10,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOV 0x18(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VSUBSD %XMM14,%XMM2,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADD %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R12,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSUBSD (%RBP,%R11,8),%XMM12,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM16,%XMM15,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM13,%XMM17	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JBE 226d6a <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1c7a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VANDPD %XMM3,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM3,%XMM15,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSUBSD %XMM14,%XMM5,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VCMPSD $0x1,%XMM15,%XMM0,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM11,%XMM16,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM16,%XMM17,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231SD %XMM10,%XMM17,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %XMM6,%XMM14,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVSD %XMM14,%XMM17,%XMM17{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD %XMM4,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM16,%XMM18,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM17,%XMM16,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM17,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM8,%XMM14,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM8,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15,%RSI,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R15,%R10,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD (%R15,%R11,8),%XMM14,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM14,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM16,%XMM15,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM13,%XMM17	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 226c20 <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1b30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD %XMM9,%XMM12,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM3,%XMM8,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM3,%XMM15,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCMPSD $0x1,%XMM15,%XMM0,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM9,%XMM13,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VANDPD %XMM3,%XMM16,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULSD %XMM11,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD213SD %XMM11,%XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMINSD %XMM13,%XMM12,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM4,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM11,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM9,%XMM5,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VXORPD %XMM6,%XMM9,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVSD %XMM9,%XMM11,%XMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD %XMM11,%XMM10,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 226c20 <__nv_advec_cell_kernel_module_advec_cell_kernel__PARALLEL_F2L81_1_+0x1b30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

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ASM code

Vectorization

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Execution units bottlenecks

Masked instructions

Details

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FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code