OV - exec - Loop 209

	Loop Id: 209	Module: exec	Source: calc_dt_kernel.f90:107-131	Coverage: 3.43%

0x230220 MOV	0x130(%R14),%RAX    [12]

0x230227 VMOVSD	(%RAX),%XMM14    [5]

0x23022b VMOVSD	0x8(%RCX,%RDX,8),%XMM16    [3]

0x230233 VMOVSD	0x8(%R8,%RDX,8),%XMM15    [1]

0x23023a VMULSD	%XMM3,%XMM13,%XMM13

0x23023e VANDPD	%XMM1,%XMM11,%XMM11

0x230242 VANDPD	%XMM1,%XMM9,%XMM9

0x230246 VANDPD	%XMM1,%XMM10,%XMM10

0x23024a VMAXSD	%XMM9,%XMM11,%XMM9

0x23024f VANDPD	%XMM1,%XMM12,%XMM11

0x230253 VMAXSD	%XMM10,%XMM11,%XMM10

0x230258 VMAXSD	%XMM9,%XMM13,%XMM9

0x23025d VMAXSD	%XMM10,%XMM13,%XMM10

0x230262 VADDSD	%XMM16,%XMM16,%XMM16

0x230268 VDIVSD	0x8(%R15,%RDX,8),%XMM16,%XMM16    [14]

0x230270 VFMADD231SD	%XMM15,%XMM15,%XMM16

0x230276 VSQRTSD	%XMM16,%XMM16,%XMM15

0x23027c VMINSD	0x8(%R10,%RDX,8),%XMM2,%XMM16    [4]

0x230284 INC	%RDX

0x230287 VMULSD	%XMM16,%XMM4,%XMM16

0x23028d VMAXSD	%XMM15,%XMM3,%XMM15

0x230292 VDIVSD	%XMM15,%XMM16,%XMM15

0x230298 VMINSD	%XMM17,%XMM15,%XMM15

0x23029e VMULSD	%XMM5,%XMM8,%XMM17

0x2302a4 VMULSD	%XMM6,%XMM8,%XMM8

0x2302a8 VDIVSD	%XMM9,%XMM17,%XMM9

0x2302ae VDIVSD	%XMM10,%XMM8,%XMM8

0x2302b3 VMINSD	%XMM15,%XMM9,%XMM9

0x2302b8 VMINSD	%XMM9,%XMM8,%XMM8

0x2302bd VMINSD	%XMM8,%XMM14,%XMM17

0x2302c3 CMP	%RDX,0x10(%RSP)    [15]

0x2302c8 JE	2300a0

0x2302ce VMOVSD	(%RBP,%RDX,8),%XMM8    [9]

0x2302d4 VMOVSD	0x8(%RBP,%RDX,8),%XMM10    [9]

0x2302da VMOVSD	(%RBX,%RDX,8),%XMM12    [16]

0x2302df VMOVSD	0x8(%R11,%RDX,8),%XMM13    [7]

0x2302e6 VADDSD	(%RDI,%RDX,8),%XMM8,%XMM8    [13]

0x2302eb VADDSD	0x8(%RBX,%RDX,8),%XMM12,%XMM12    [16]

0x2302f1 VMULSD	(%R13,%RDX,8),%XMM8,%XMM9    [11]

0x2302f8 VADDSD	0x8(%RDI,%RDX,8),%XMM10,%XMM8    [13]

0x2302fe VMOVSD	(%R12,%RDX,8),%XMM10    [10]

0x230304 VMULSD	0x8(%RSI,%RDX,8),%XMM12,%XMM12    [8]

0x23030a VADDSD	0x8(%R12,%RDX,8),%XMM10,%XMM10    [10]

0x230311 VMULSD	0x8(%R13,%RDX,8),%XMM8,%XMM11    [11]

0x230318 VMULSD	0x8(%R9,%RDX,8),%XMM10,%XMM10    [2]

0x23031f VADDSD	%XMM13,%XMM13,%XMM8

0x230324 VADDSD	%XMM10,%XMM9,%XMM14

0x230329 VSUBSD	%XMM14,%XMM11,%XMM14

0x23032e VADDSD	%XMM12,%XMM14,%XMM14

0x230333 VDIVSD	%XMM8,%XMM14,%XMM14

0x230338 VUCOMISD	%XMM7,%XMM14

0x23033c JAE	230220

0x230342 MOV	0x128(%R14),%RAX    [12]

0x230349 VMOVSD	(%RAX),%XMM15    [6]

0x23034d VXORPD	%XMM0,%XMM15,%XMM15

0x230351 VDIVSD	%XMM14,%XMM15,%XMM14

0x230356 JMP	23022b

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 107 - 131

--------------------------------------------------------------------------------

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

130:

131:       ENDDO

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	5.03
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.01
Bottlenecks
Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source	calc_dt_kernel.f90:107-131
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	30.50
CQA cycles if no scalar integer	30.50
CQA cycles if FP arith vectorized	6.06
CQA cycles if fully vectorized	3.81
Front-end cycles	6.81
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.83
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	9.88
P11 cycles	9.88
P12 cycles	10.13
P13 cycles	10.13
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	30.50
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.50
Nb uops	54.50
Nb loads	20.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.84
Nb FLOP add-sub	9.00
Nb FLOP mul	8.00
Nb FLOP fma	1.00
Nb FLOP div	5.50
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.27
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	9.36
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	28.96
Vector-efficiency ratio all	13.67
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	16.12

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	5.36
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.17
Bottlenecks	P10, P11,
Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source	calc_dt_kernel.f90:107-131
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	6.06
CQA cycles if fully vectorized	4.06
Front-end cycles	7.00
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	10.25
P11 cycles	10.25
P12 cycles	10.25
P13 cycles	10.25
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	32.50
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	56.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.80
Nb FLOP add-sub	9.00
Nb FLOP mul	8.00
Nb FLOP fma	1.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.92
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	10.20
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	31.25
Vector-efficiency ratio all	13.78
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	16.41

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	4.70
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.85
Bottlenecks	P10, P11,
Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source	calc_dt_kernel.f90:107-131
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	6.06
CQA cycles if fully vectorized	3.56
Front-end cycles	6.63
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	9.50
P11 cycles	9.50
P12 cycles	10.00
P13 cycles	10.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	28.50
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	53.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.88
Nb FLOP add-sub	9.00
Nb FLOP mul	8.00
Nb FLOP fma	1.00
Nb FLOP div	5.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.61
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	8.51
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	26.67
Vector-efficiency ratio all	13.56
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source file and lines	calc_dt_kernel.f90:107-131
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:107-131.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 30.50 to 3.81 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 30.50 to 13.25 cycles (2.30x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

35 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25.5 FP arithmetical operations:

10: addition or subtraction (1 inside FMA instructions)
9: multiply (1 inside FMA instructions)
5.50: divide
1: square root

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	53.50
nb uops	54.50
loop length	297
used x86 registers	16
used mmx registers	0
used xmm registers	17.50
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	6.81 cycles
front end	6.81 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.83	0.83	0.83	5.00	5.00	5.00	5.00	9.88	9.88	10.13	10.13	0.50	0.50
cycles	0.67	0.67	0.67	0.83	0.83	0.83	5.00	5.00	5.00	5.00	9.88	9.88	10.13	10.13	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	30.50
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	6.81
Dispatch	10.13
DIV/SQRT	30.50
Data deps.	8.00
Overall L1	30.50

Vectorization ratios

all	9%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	28%

Vector efficiency ratios

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.50 cycles. At this rate:

2% of peak load performance is reached (5.27 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source file and lines	calc_dt_kernel.f90:107-131
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 32.50 to 10.25 cycles (3.17x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.50 to 13.50 cycles (2.41x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:123

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

36 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 26 FP arithmetical operations:

10: addition or subtraction (1 inside FMA instructions)
9: multiply (1 inside FMA instructions)
6: divide
1: square root

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	55
nb uops	56
loop length	304
used x86 registers	16
used mmx registers	0
used xmm registers	18
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	1.00	1.00	1.00	5.00	5.00	5.00	5.00	10.25	10.25	10.25	10.25	0.50	0.50
cycles	0.67	0.67	0.67	1.00	1.00	1.00	5.00	5.00	5.00	5.00	10.25	10.25	10.25	10.25	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	32.50
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	7.00
Dispatch	10.25
DIV/SQRT	32.50
Data deps.	8.00
Overall L1	32.50

Vectorization ratios

all	10%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	31%

Vector efficiency ratios

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.50 cycles. At this rate:

1% of peak load performance is reached (4.92 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2302ce

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD 0x8(%RCX,%RDX,8),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R8,%RDX,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM3,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM1,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM1,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM1,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMAXSD %XMM9,%XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VANDPD %XMM1,%XMM12,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMAXSD %XMM10,%XMM11,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM9,%XMM13,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM10,%XMM13,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD 0x8(%R15,%RDX,8),%XMM16,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VFMADD231SD %XMM15,%XMM15,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM16,%XMM16,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
VMINSD 0x8(%R10,%RDX,8),%XMM2,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD %XMM16,%XMM4,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMAXSD %XMM15,%XMM3,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM15,%XMM16,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMINSD %XMM17,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM5,%XMM8,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM6,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM9,%XMM17,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM10,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMINSD %XMM15,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD %XMM9,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD %XMM8,%XMM14,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RDX,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 2300a0 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x130>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RBP,%RDX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RBP,%RDX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RBX,%RDX,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R11,%RDX,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RDI,%RDX,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD 0x8(%RBX,%RDX,8),%XMM12,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD (%R13,%RDX,8),%XMM8,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD 0x8(%RDI,%RDX,8),%XMM10,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD (%R12,%RDX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD 0x8(%RSI,%RDX,8),%XMM12,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD 0x8(%R12,%RDX,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD 0x8(%R13,%RDX,8),%XMM8,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD 0x8(%R9,%RDX,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM13,%XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM10,%XMM9,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM14,%XMM11,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM12,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM8,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VUCOMISD %XMM7,%XMM14	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 230220 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x128(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VXORPD %XMM0,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VDIVSD %XMM14,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
JMP 23022b <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x2bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source file and lines	calc_dt_kernel.f90:107-131
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.50 to 13.00 cycles (2.19x speedup).

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:123

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

35 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

10: addition or subtraction (1 inside FMA instructions)
9: multiply (1 inside FMA instructions)
5: divide
1: square root

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	52
nb uops	53
loop length	290
used x86 registers	16
used mmx registers	0
used xmm registers	17
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.63 cycles
front end	6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	5.00	5.00	5.00	5.00	9.50	9.50	10.00	10.00	0.50	0.50
cycles	0.67	0.67	0.67	0.67	0.67	0.67	5.00	5.00	5.00	5.00	9.50	9.50	10.00	10.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	28.50
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	6.63
Dispatch	10.00
DIV/SQRT	28.50
Data deps.	8.00
Overall L1	28.50

Vectorization ratios

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	26%

Vector efficiency ratios

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

2% of peak load performance is reached (5.61 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2302ce

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x130(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RCX,%RDX,8),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R8,%RDX,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM3,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM1,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM1,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM1,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMAXSD %XMM9,%XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VANDPD %XMM1,%XMM12,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMAXSD %XMM10,%XMM11,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM9,%XMM13,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM10,%XMM13,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD 0x8(%R15,%RDX,8),%XMM16,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VFMADD231SD %XMM15,%XMM15,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM16,%XMM16,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
VMINSD 0x8(%R10,%RDX,8),%XMM2,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD %XMM16,%XMM4,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMAXSD %XMM15,%XMM3,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM15,%XMM16,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMINSD %XMM17,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM5,%XMM8,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM6,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM9,%XMM17,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM10,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMINSD %XMM15,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD %XMM9,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD %XMM8,%XMM14,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RDX,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 2300a0 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x130>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RBP,%RDX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RBP,%RDX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RBX,%RDX,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R11,%RDX,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RDI,%RDX,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD 0x8(%RBX,%RDX,8),%XMM12,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD (%R13,%RDX,8),%XMM8,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD 0x8(%RDI,%RDX,8),%XMM10,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD (%R12,%RDX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD 0x8(%RSI,%RDX,8),%XMM12,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD 0x8(%R12,%RDX,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD 0x8(%R13,%RDX,8),%XMM8,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD 0x8(%R9,%RDX,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM13,%XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM10,%XMM9,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM14,%XMM11,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM12,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM8,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VUCOMISD %XMM7,%XMM14	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 230220 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

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Matching between your loop (in the source code) and the binary loop

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Expensive FP math instructions/calls

FMA

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Complex instructions

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Slow data structures access

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

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Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code