OV - exec - Loop 117

	Loop Id: 117	Module: exec	Source: advec_mom_kernel.f90:215-241 [...]	Coverage: 4.33%

0x22c070 VSUBSD	%XMM8,%XMM1,%XMM8

0x22c075 VFMADD213SD	%XMM9,%XMM10,%XMM8

0x22c07a VMULSD	%XMM7,%XMM8,%XMM7

0x22c07e VMOVSD	%XMM7,(%RBX,%R15,8)    [3]

0x22c084 INC	%R15

0x22c087 CMP	%R15,0x10(%RSP)    [1]

0x22c08c JE	22c030

0x22c08e VMOVSD	(%R11,%R15,8),%XMM7    [5]

0x22c094 VXORPD	%XMM10,%XMM10,%XMM10

0x22c099 LEA	(%R10,%R15,1),%RCX

0x22c09d LEA	(%R12,%R15,1),%R13

0x22c0a1 MOV	0x8(%RSP),%RDX    [1]

0x22c0a6 MOV	%RCX,%R8

0x22c0a9 VUCOMISD	%XMM7,%XMM10

0x22c0ad VANDPD	%XMM0,%XMM7,%XMM8

0x22c0b1 CMOVBE	%R13,%R8

0x22c0b5 CMOVBE	%RCX,%R13

0x22c0b9 MOV	(%RSP),%ECX    [1]

0x22c0bc VDIVSD	(%RDX,%R13,8),%XMM8,%XMM8    [8]

0x22c0c2 LEA	(%RSI,%R15,1),%RDX

0x22c0c6 VMOVSD	(%R9,%R13,8),%XMM9    [2]

0x22c0cc VMOVSD	(%R9,%R8,8),%XMM11    [2]

0x22c0d2 CMOVBE	%EBP,%ECX

0x22c0d5 MOVSXD	%ECX,%RCX

0x22c0d8 IMUL	%RDI,%RCX

0x22c0dc VSUBSD	%XMM9,%XMM11,%XMM11

0x22c0e1 ADD	%RDX,%RCX

0x22c0e4 VSUBSD	(%R9,%RCX,8),%XMM9,%XMM12    [2]

0x22c0ea VMULSD	%XMM12,%XMM11,%XMM13

0x22c0ef VUCOMISD	%XMM10,%XMM13

0x22c0f4 JBE	22c070

0x22c0fa MOV	0x140(%R14),%R8    [4]

0x22c101 VUCOMISD	%XMM7,%XMM2

0x22c105 MOV	0x138(%R14),%RDX    [4]

0x22c10c MOV	0x20(%RSP),%RCX    [1]

0x22c111 MOV	%RAX,%R13

0x22c114 VANDPD	%XMM3,%XMM12,%XMM12

0x22c118 VSUBSD	%XMM8,%XMM4,%XMM15

0x22c11d VANDPD	%XMM3,%XMM11,%XMM13

0x22c121 VCMPSD	$0x1,%XMM11,%XMM2,%K1

0x22c128 VMOVAPD	%XMM12,%XMM14

0x22c12d VFMADD213SD	%XMM12,%XMM8,%XMM14

0x22c132 VMULSD	%XMM15,%XMM13,%XMM15

0x22c137 CMOVBE	%EBP,%ECX

0x22c13a MOV	(%R8),%R8    [6]

0x22c13d MOVSXD	%ECX,%RCX

0x22c140 SUB	%R8,%R13

0x22c143 SUB	%R8,%RCX

0x22c146 VMOVSD	(%RDX,%R13,8),%XMM10    [7]

0x22c14c VDIVSD	(%RDX,%RCX,8),%XMM14,%XMM14    [7]

0x22c151 VDIVSD	%XMM10,%XMM15,%XMM15

0x22c156 VMULSD	%XMM5,%XMM10,%XMM10

0x22c15a VADDSD	%XMM15,%XMM14,%XMM14

0x22c15f VMULSD	%XMM14,%XMM10,%XMM10

0x22c164 VMINSD	%XMM10,%XMM12,%XMM10

0x22c169 VMINSD	%XMM10,%XMM13,%XMM12

0x22c16e VXORPD	%XMM6,%XMM12,%XMM10

0x22c172 VMOVSD	%XMM12,%XMM10,%XMM10{%K1}

0x22c178 JMP	22c070

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 215 - 241

--------------------------------------------------------------------------------

215:           IF(node_flux(j,k).LT.0.0)THEN

[...]

227:           sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor))

228:           width=celldy(k)

229:           vdiffuw=vel1(j,donor)-vel1(j,upwind)

230:           vdiffdw=vel1(j,downwind)-vel1(j,donor)

231:           limiter=0.0

232:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

233:             auw=ABS(vdiffuw)

234:             adw=ABS(vdiffdw)

235:             wind=1.0_8

236:             IF(vdiffdw.LE.0.0) wind=-1.0_8

237:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw)

238:           ENDIF

239:           advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter

240:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

241:         ENDDO

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	3.57
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks
Function	__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1
Source	advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	2.31
CQA cycles if fully vectorized	1.03
Front-end cycles	6.38
P0 cycles	3.17
P1 cycles	3.17
P2 cycles	3.17
P3 cycles	3.17
P4 cycles	3.17
P5 cycles	3.17
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	4.50
P13 cycles	4.50
P14 cycles	1.75
P15 cycles	1.75
DIV/SQRT cycles	8.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	51.00
Nb loads	11.00
Nb stores	1.00
Nb stack references	3.50
FLOP/cycle	1.52
Nb FLOP add-sub	4.00
Nb FLOP mul	3.50
Nb FLOP fma	1.50
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.39
Bytes prefetched	0.00
Bytes loaded	84.00
Bytes stored	8.00
Stride 0	1.50
Stride 1	2.00
Stride n	0.00
Stride unknown	0.50
Stride indirect	2.50
Vectorization ratio all	15.07
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	41.43
Vector-efficiency ratio all	14.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.68

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	4.27
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P10, P11,
Function	__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1
Source	advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	2.81
CQA cycles if fully vectorized	1.50
Front-end cycles	8.25
P0 cycles	3.67
P1 cycles	3.67
P2 cycles	3.67
P3 cycles	3.67
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.75
P7 cycles	3.75
P8 cycles	3.75
P9 cycles	3.75
P10 cycles	6.50
P11 cycles	6.50
P12 cycles	6.50
P13 cycles	6.50
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	66.00
Nb loads	14.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	1.42
Nb FLOP add-sub	5.00
Nb FLOP mul	5.00
Nb FLOP fma	2.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.67
Bytes prefetched	0.00
Bytes loaded	108.00
Bytes stored	8.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	3.00
Vectorization ratio all	17.65
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	14.71
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.86

Metric	Value
CQA speedup if no scalar integer	1.13
CQA speedup if FP arith vectorized	2.48
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1
Source	advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	1.81
CQA cycles if fully vectorized	0.56
Front-end cycles	4.50
P0 cycles	2.67
P1 cycles	2.67
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	2.50
P13 cycles	2.50
P14 cycles	1.50
P15 cycles	1.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	36.00
Nb loads	8.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	1.78
Nb FLOP add-sub	3.00
Nb FLOP mul	2.00
Nb FLOP fma	1.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.11
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	8.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	12.50
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	40.00
Vector-efficiency ratio all	14.06
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1
Source file and lines	advec_mom_kernel.f90:215-241
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215,227-241.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.25 to 1.03 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.25 to 6.38 cycles (1.29x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 1.50 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 0 occurrences
VUCOMISD: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 0 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

15 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12.5 FP arithmetical operations:

5.50: addition or subtraction (1 inside FMA instructions)
5: multiply (1 inside FMA instructions)
2: divide

The binary loop is loading 84 bytes (10 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	45
nb uops	51
loop length	203.50
used x86 registers	15
used mmx registers	0
used xmm registers	12.50
used ymm registers	0
used zmm registers	0
nb stack references	3.50
ADD-SUB / MUL ratio	1.25

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.17	3.17	3.17	3.17	3.17	3.17	3.00	3.00	3.00	3.00	4.50	4.50	4.50	4.50	1.75	1.75
cycles	3.17	3.17	3.17	3.17	3.17	3.17	3.00	3.00	3.00	3.00	4.50	4.50	4.50	4.50	1.75	1.75

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.38
Dispatch	4.58
DIV/SQRT	8.00
Data deps.	0.00
Overall L1	8.25

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	15%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	48%

INT+FP

all	15%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	41%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

4% of peak load performance is reached (11.17 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1
Source file and lines	advec_mom_kernel.f90:215-241
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 8.25 cycles (1.45x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 8.25 cycles (1.45x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:237
VUCOMISD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 17 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)
3: divide

The binary loop is loading 108 bytes (13 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	59
nb uops	66
loop length	269
used x86 registers	16
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	4
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.67	3.67	3.67	3.67	3.67	3.67	3.75	3.75	3.75	3.75	6.50	6.50	6.50	6.50	2.00	2.00
cycles	3.67	3.67	3.67	3.67	3.67	3.67	3.75	3.75	3.75	3.75	6.50	6.50	6.50	6.50	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	12.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.25
Dispatch	6.50
DIV/SQRT	12.00
Data deps.	0.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	18%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	46%

INT+FP

all	17%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	42%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

3% of peak load performance is reached (9.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 22c08e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VSUBSD %XMM8,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD %XMM9,%XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM7,%XMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%RBX,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 22c030 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2730>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R11,%R15,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%R10,%R15,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%R15,1),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x8(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VUCOMISD %XMM7,%XMM10	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VANDPD %XMM0,%XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
CMOVBE %R13,%R8	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMOVBE %RCX,%R13	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV (%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VDIVSD (%RDX,%R13,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
LEA (%RSI,%R15,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R9,%R13,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R9,%R8,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMOVBE %EBP,%ECX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOVSXD %ECX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VSUBSD %XMM9,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSUBSD (%R9,%RCX,8),%XMM9,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM12,%XMM11,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM10,%XMM13	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 22c070 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2770>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x140(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD %XMM7,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
MOV 0x138(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VANDPD %XMM3,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSUBSD %XMM8,%XMM4,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VANDPD %XMM3,%XMM11,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCMPSD $0x1,%XMM11,%XMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVAPD %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD %XMM12,%XMM8,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM15,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
CMOVBE %EBP,%ECX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV (%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %ECX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RDX,%R13,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VDIVSD (%RDX,%RCX,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM10,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM5,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM14,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM10,%XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD %XMM10,%XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VXORPD %XMM6,%XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVSD %XMM12,%XMM10,%XMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JMP 22c070 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2770>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1
Source file and lines	advec_mom_kernel.f90:215-241
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.50 to 4.00 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:227
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:230
VUCOMISD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:215
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:232

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

9 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (1 inside FMA instructions)
3: multiply (1 inside FMA instructions)
1: divide

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually.

General properties

nb instructions	31
nb uops	36
loop length	138
used x86 registers	14
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.50 cycles
front end	4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.67	2.67	2.67	2.67	2.67	2.67	2.25	2.25	2.25	2.25	2.50	2.50	2.50	2.50	1.50	1.50
cycles	2.67	2.67	2.67	2.67	2.67	2.67	2.25	2.25	2.25	2.25	2.50	2.50	2.50	2.50	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.50
Dispatch	2.67
DIV/SQRT	4.00
Data deps.	0.00
Overall L1	4.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	13%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

INT+FP

all	12%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	40%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

5% of peak load performance is reached (13.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.78 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 22c08e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VSUBSD %XMM8,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD %XMM9,%XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM7,%XMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%RBX,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 22c030 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2730>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R11,%R15,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%R10,%R15,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%R15,1),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x8(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VUCOMISD %XMM7,%XMM10	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VANDPD %XMM0,%XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
CMOVBE %R13,%R8	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMOVBE %RCX,%R13	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV (%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VDIVSD (%RDX,%R13,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
LEA (%RSI,%R15,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R9,%R13,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R9,%R8,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMOVBE %EBP,%ECX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOVSXD %ECX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VSUBSD %XMM9,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSUBSD (%R9,%RCX,8),%XMM9,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM12,%XMM11,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM10,%XMM13	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 22c070 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2770>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

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Vectorization

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Expensive FP math instructions/calls

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FMA

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Complex instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

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Vectorization

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Execution units bottlenecks

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Expensive FP math instructions/calls

Masked instructions

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FMA

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Complex instructions

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Slow data structures access

Details

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

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Vectorization

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Execution units bottlenecks

FMA

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Complex instructions

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Slow data structures access

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

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General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code