OV - exec - Function __nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155

	Function: __nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3	Module: exec	Source: pack_kernel.f90:155-162	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 155 - 162

--------------------------------------------------------------------------------

155:     !$OMP PARALLEL DO PRIVATE(index)

156:     DO k=y_min-depth,y_max+y_inc+depth

157:     !$OMP SIMD

158:       DO j=1,depth

159:         index= buffer_offset + j+(k+depth-1)*depth

160:         right_snd_buffer(index)=field(x_max+1-j,k)

161:       ENDDO

162:     ENDDO

0x238230 PUSH	%RBP

0x238231 PUSH	%R15

0x238233 PUSH	%R14

0x238235 PUSH	%R13

0x238237 PUSH	%R12

0x238239 PUSH	%RBX

0x23823a SUB	$0x68,%RSP

0x23823e MOV	%RDX,%R14

0x238241 MOV	(%RDX),%RAX

0x238244 MOV	0x8(%RDX),%RBX

0x238248 MOV	0x10(%RDX),%RDX

0x23824c MOVL	$0,0x24(%RSP)

0x238254 MOV	(%RDI),%ESI

0x238256 MOV	0x18(%R14),%RDI

0x23825a MOV	(%RBX),%ECX

0x23825c MOV	(%RDX),%EBP

0x23825e MOV	(%RAX),%EAX

0x238260 ADD	%ECX,%EBP

0x238262 ADD	(%RDI),%EBP

0x238264 SUB	%ECX,%EAX

0x238266 MOVL	$0x1,0x20(%RSP)

0x23826e MOV	%EAX,0x4(%RSP)

0x238272 MOV	%EBP,(%RSP)

0x238275 SUB	$0x8,%RSP

0x238279 LEA	0x28(%RSP),%RAX

0x23827e LEA	0x2c(%RSP),%RCX

0x238283 LEA	0xc(%RSP),%R8

0x238288 LEA	0x8(%RSP),%R9

0x23828d XOR	%EDI,%EDI

0x23828f MOV	%ESI,0x18(%RSP)

0x238293 MOV	$0x22,%EDX

0x238298 PUSH	$0x1

0x23829a PUSH	$0x1

0x23829c PUSH	%RAX

0x23829d CALL	27ccb0 <@plt_start@+0xa0>

0x2382a2 ADD	$0x20,%RSP

0x2382a6 MOVSXD	0x4(%RSP),%RAX

0x2382ab CMP	%EBP,%EAX

0x2382ad JG	23853d

0x2382b3 MOVSXD	(%RSP),%RCX

0x2382b7 MOV	%RCX,0x60(%RSP)

0x2382bc CMP	%EAX,%ECX

0x2382be JL	23853d

0x2382c4 MOV	(%RBX),%EDX

0x2382c6 TEST	%EDX,%EDX

0x2382c8 JLE	23853d

0x2382ce MOV	0x80(%R14),%R9

0x2382d5 MOV	0x20(%R14),%RCX

0x2382d9 VMOVAPD	-0x2a8a3(%RIP),%ZMM0

0x2382e3 MOV	0x28(%R14),%RSI

0x2382e7 MOV	0x50(%R14),%R8

0x2382eb LEA	0x1(%RDX),%R15

0x2382ef XOR	%R12D,%R12D

0x2382f2 MOV	%R15,0x48(%RSP)

0x2382f7 MOV	(%R9),%R9

0x2382fa MOV	(%RCX),%EDI

0x2382fc MOV	0xa0(%R14),%RCX

0x238303 MOV	%R9,0x58(%RSP)

0x238308 MOV	0x98(%R14),%R9

0x23830f MOV	(%RCX),%ECX

0x238311 MOV	(%R9),%R10

0x238314 MOV	0x48(%R14),%R9

0x238318 LEA	-0x1(%RDX),%R14

0x23831c MOV	%R14,0x50(%RSP)

0x238321 MOV	(%R9),%R11

0x238324 LEA	-0x1(%RDX,%RAX,1),%R9D

0x238329 IMUL	%EDX,%R9D

0x23832d LEA	(%RDI,%R9,1),%EBP

0x238331 LEA	0x1(%RDI,%R9,1),%EDI

0x238336 MOV	%ECX,%R9D

0x238339 SUB	%R14D,%R9D

0x23833c MOV	%R9D,0x14(%RSP)

0x238341 MOV	%EDX,%R9D

0x238344 AND	$-0x20,%R9D

0x238348 MOV	%R9,0x8(%RSP)

0x23834d INC	%R9

0x238350 MOV	%EDI,%R15D

0x238353 MOV	%EDI,0x18(%RSP)

0x238357 MOV	%R9,0x28(%RSP)

0x23835c MOV	%EDX,%R9D

0x23835f AND	$-0x4,%R9D

0x238363 LEA	0x1(%R9),%RBX

0x238367 MOV	%R9,0x40(%RSP)

0x23836c NEG	%R9

0x23836f MOV	%RBX,0x38(%RSP)

0x238374 LEA	0x1(%RCX),%EBX

0x238377 MOV	%R9,0x30(%RSP)

0x23837c MOV	%EBX,0x1c(%RSP)

0x238380 JMP	2383af

0x238382 NOPW	%CS:(%RAX,%RAX,1)

(340) 0x238390 MOV	0x50(%RSP),%R14

(340) 0x238395 LEA	0x1(%RAX),%RDI

(340) 0x238399 INC	%R12D

(340) 0x23839c ADD	%EDX,%R15D

(340) 0x23839f ADD	%EDX,%EBP

(340) 0x2383a1 CMP	0x60(%RSP),%RAX

(340) 0x2383a6 MOV	%RDI,%RAX

(340) 0x2383a9 JE	23853d

(340) 0x2383af MOV	0x58(%RSP),%R9

(340) 0x2383b4 MOV	$0x1,%EBX

(340) 0x2383b9 IMUL	%RAX,%R9

(340) 0x2383bd CMP	$0x4,%EDX

(340) 0x2383c0 JB	238500

(340) 0x2383c6 MOV	%R14,%RDI

(340) 0x2383c9 SHR	$0x20,%RDI

(340) 0x2383cd JNE	238500

(340) 0x2383d3 MOV	%EDX,%EDI

(340) 0x2383d5 IMUL	%R12D,%EDI

(340) 0x2383d9 ADD	0x18(%RSP),%EDI

(340) 0x2383dd LEA	(%RDI,%R14,1),%R13D

(340) 0x2383e1 CMP	%EDI,%R13D

(340) 0x2383e4 JL	238500

(340) 0x2383ea CMP	%ECX,0x14(%RSP)

(340) 0x2383ee JG	238500

(340) 0x2383f4 CMP	$0x20,%EDX

(340) 0x2383f7 JAE	238401

(340) 0x2383f9 XOR	%R13D,%R13D

(340) 0x2383fc JMP	238494

(340) 0x238401 MOV	0x8(%RSP),%RDI

(340) 0x238406 MOV	%ECX,%EBX

(340) 0x238408 MOV	%R15D,%R13D

(340) 0x23840b NOPL	(%RAX,%RAX,1)

  (341) 0x238410 MOVSXD	%EBX,%RBX

  (341) 0x238413 MOVSXD	%R13D,%R13

  (341) 0x238416 LEA	(%R9,%RBX,1),%R14

  (341) 0x23841a ADD	$-0x20,%EBX

  (341) 0x23841d ADD	%R10,%R14

  (341) 0x238420 VPERMPD	-0x40(%R8,%R14,8),%ZMM0,%ZMM1

  (341) 0x238428 VPERMPD	-0x80(%R8,%R14,8),%ZMM0,%ZMM2

  (341) 0x238430 VPERMPD	-0xc0(%R8,%R14,8),%ZMM0,%ZMM3

  (341) 0x238438 VPERMPD	-0x100(%R8,%R14,8),%ZMM0,%ZMM4

  (341) 0x238440 LEA	(%R11,%R13,1),%R14

  (341) 0x238444 ADD	$0x20,%R13D

  (341) 0x238448 ADD	$-0x20,%RDI

  (341) 0x23844c VMOVUPD	%ZMM1,-0x8(%RSI,%R14,8)

  (341) 0x238457 VMOVUPD	%ZMM2,0x38(%RSI,%R14,8)

  (341) 0x238462 VMOVUPD	%ZMM3,0x78(%RSI,%R14,8)

  (341) 0x23846d VMOVUPD	%ZMM4,0xb8(%RSI,%R14,8)

  (341) 0x238478 JNE	238410

(340) 0x23847a CMP	%RDX,0x8(%RSP)

(340) 0x23847f JE	238390

(340) 0x238485 MOV	0x8(%RSP),%R13

(340) 0x23848a MOV	0x28(%RSP),%RBX

(340) 0x23848f TEST	$0x1c,%DL

(340) 0x238492 JE	238500

(340) 0x238494 MOV	%ECX,%EDI

(340) 0x238496 LEA	(%R15,%R13,1),%EBX

(340) 0x23849a SUB	%R13D,%EDI

(340) 0x23849d ADD	0x30(%RSP),%R13

(340) 0x2384a2 NOPW	%CS:(%RAX,%RAX,1)

  (342) 0x2384b0 MOVSXD	%EDI,%RDI

  (342) 0x2384b3 MOVSXD	%EBX,%RBX

  (342) 0x2384b6 LEA	(%R9,%RDI,1),%R14

  (342) 0x2384ba ADD	$-0x4,%EDI

  (342) 0x2384bd ADD	%R10,%R14

  (342) 0x2384c0 VPERMILPD	$0x1,-0x20(%R8,%R14,8),%XMM1

  (342) 0x2384c8 VPERMILPD	$0x1,-0x10(%R8,%R14,8),%XMM2

  (342) 0x2384d0 LEA	(%R11,%RBX,1),%R14

  (342) 0x2384d4 ADD	$0x4,%EBX

  (342) 0x2384d7 ADD	$0x4,%R13

  (342) 0x2384db VMOVUPD	%XMM1,0x8(%RSI,%R14,8)

  (342) 0x2384e2 VMOVUPD	%XMM2,-0x8(%RSI,%R14,8)

  (342) 0x2384e9 JNE	2384b0

(340) 0x2384eb MOV	0x38(%RSP),%RBX

(340) 0x2384f0 CMP	%RDX,0x40(%RSP)

(340) 0x2384f5 JE	238390

(340) 0x2384fb NOPL	(%RAX,%RAX,1)

(340) 0x238500 MOV	0x48(%RSP),%R13

(340) 0x238505 MOV	0x1c(%RSP),%EDI

(340) 0x238509 SUB	%EBX,%EDI

(340) 0x23850b SUB	%RBX,%R13

(340) 0x23850e ADD	%EBP,%EBX

  (339) 0x238510 MOVSXD	%EDI,%RDI

  (339) 0x238513 MOVSXD	%EBX,%RBX

  (339) 0x238516 LEA	(%R9,%RDI,1),%R14

  (339) 0x23851a DEC	%EDI

  (339) 0x23851c ADD	%R10,%R14

  (339) 0x23851f VMOVSD	-0x8(%R8,%R14,8),%XMM1

  (339) 0x238526 LEA	(%R11,%RBX,1),%R14

  (339) 0x23852a INC	%EBX

  (339) 0x23852c DEC	%R13

  (339) 0x23852f VMOVSD	%XMM1,-0x8(%RSI,%R14,8)

  (339) 0x238536 JNE	238510

(340) 0x238538 JMP	238390

0x23853d MOV	0x10(%RSP),%ESI

0x238541 XOR	%EDI,%EDI

0x238543 VZEROUPPER

0x238546 CALL	27ccc0 <@plt_start@+0xb0>

0x23854b ADD	$0x68,%RSP

0x23854f POP	%RBX

0x238550 POP	%R12

0x238552 POP	%R13

0x238554 POP	%R14

0x238556 POP	%R15

0x238558 POP	%RBP

0x238559 RET

0x23855a NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_10

Source file and lines	pack_kernel.f90:155-162
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:155-162.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.13 to 1.50 cycles (8.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.13 to 9.67 cycles (1.36x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:156
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:162

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:161
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:161

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	103
nb uops	105
loop length	387
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	1
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.13 cycles
front end	13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.17	6.17	6.17	6.17	6.17	6.17	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.17	6.17	6.17	6.17	6.17	6.17	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.13
Dispatch	11.75
Overall L1	13.13

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	19%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.13 cycles. At this rate:

6% of peak load performance is reached (16.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.13 to 11.75 cycles (1.12x speedup).

ASM code

In the binary file, the address of the function is: 238230

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVL $0,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%RAX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %ECX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD (%RDI),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
SUB %ECX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVL $0x1,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EAX,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EBP,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x28(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x2c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xc(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x8(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 27ccb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD 0x4(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
CMP %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JG 23853d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOVSXD (%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %RCX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JL 23853d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EDX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 23853d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x80(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVAPD -0x2a8a3(%RIP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV 0x28(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x50(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA 0x1(%RDX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %R15,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0xa0(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x98(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x48(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R14,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R9),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA -0x1(%RDX,%RAX,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
IMUL %EDX,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDI,%R9,1),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x1(%RDI,%R9,1),%EDI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R14D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %EDI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R9,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%R9),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
NEG %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0x1(%RCX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EBX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
JMP 2383af <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x17f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x10(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 27ccc0 <@plt_start@+0xb0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_10

Source file and lines	pack_kernel.f90:155-162
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.13 to 1.50 cycles (8.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:156
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:162

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:161
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:161

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	103
nb uops	105
loop length	387
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	1
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.13 cycles
front end	13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.17	6.17	6.17	6.17	6.17	6.17	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.17	6.17	6.17	6.17	6.17	6.17	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.13
Dispatch	11.75
Overall L1	13.13

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	19%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.13 cycles. At this rate:

6% of peak load performance is reached (16.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 238230

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVL $0,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%RAX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %ECX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD (%RDI),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
SUB %ECX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVL $0x1,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EAX,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EBP,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x28(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x2c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xc(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x8(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 27ccb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD 0x4(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
CMP %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JG 23853d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOVSXD (%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %RCX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JL 23853d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EDX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 23853d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x80(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVAPD -0x2a8a3(%RIP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV 0x28(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x50(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA 0x1(%RDX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %R15,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0xa0(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x98(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x48(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R14,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R9),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA -0x1(%RDX,%RAX,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
IMUL %EDX,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDI,%R9,1),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x1(%RDI,%R9,1),%EDI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R14D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %EDI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R9,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%R9),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
NEG %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0x1(%RCX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EBX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
JMP 2383af <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x17f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x10(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 27ccc0 <@plt_start@+0xb0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3–	0.01	0.00
▼Loop 340 - pack_kernel.f90:160-162 - exec–	0.00	0.00
○Loop 339 - pack_kernel.f90:160-161 - exec	0.01	0.01
○Loop 341 - pack_kernel.f90:160-160 - exec	0.00	0.00
○Loop 342 - pack_kernel.f90:160-160 - exec	0.00	0.00

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