OV - exec - Function __nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89

	Function: __nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1	Module: exec	Source: calc_dt_kernel.f90:89-135 [...]	Coverage (incl. loops): 3.43% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 135

--------------------------------------------------------------------------------

89:     !$OMP PARALLEL

90:

91:     !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val)

92:     DO k=y_min,y_max

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

[...]

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

130:

131:       ENDDO

132:     ENDDO

133:     !$OMP END DO

134:

135:     !$OMP END PARALLEL

0x22ff70 PUSH	%RBP

0x22ff71 PUSH	%R15

0x22ff73 PUSH	%R14

0x22ff75 PUSH	%R13

0x22ff77 PUSH	%R12

0x22ff79 PUSH	%RBX

0x22ff7a SUB	$0x68,%RSP

0x22ff7e MOV	0x8(%RDX),%RAX

0x22ff82 MOV	0x10(%RDX),%RCX

0x22ff86 MOVL	$0,0x2c(%RSP)

0x22ff8e MOV	(%RDI),%ESI

0x22ff90 MOV	%RDX,%R14

0x22ff93 MOV	(%RAX),%EAX

0x22ff95 MOV	(%RCX),%EBX

0x22ff97 MOVL	$0x1,0x28(%RSP)

0x22ff9f MOV	%EAX,0xc(%RSP)

0x22ffa3 MOV	%EBX,0x8(%RSP)

0x22ffa7 SUB	$0x8,%RSP

0x22ffab LEA	0x30(%RSP),%RAX

0x22ffb0 LEA	0x34(%RSP),%RCX

0x22ffb5 LEA	0x14(%RSP),%R8

0x22ffba LEA	0x10(%RSP),%R9

0x22ffbf XOR	%EDI,%EDI

0x22ffc1 MOV	%ESI,0x2c(%RSP)

0x22ffc5 MOV	$0x22,%EDX

0x22ffca PUSH	$0x1

0x22ffcc PUSH	$0x1

0x22ffce PUSH	%RAX

0x22ffcf CALL	27ccb0 <@plt_start@+0xa0>

0x22ffd4 ADD	$0x20,%RSP

0x22ffd8 VMOVSD	-0x2e21a(%RIP),%XMM17

0x22ffe2 MOVSXD	0xc(%RSP),%RAX

0x22ffe7 CMP	%EBX,%EAX

0x22ffe9 JG	22fff4

0x22ffeb MOVSXD	0x8(%RSP),%RSI

0x22fff0 CMP	%EAX,%ESI

0x22fff2 JGE	230046

0x22fff4 MOV	0x24(%RSP),%EBX

0x22fff8 VMOVSD	%XMM17,0x10(%RSP)

0x230000 XOR	%EDI,%EDI

0x230002 MOV	%EBX,%ESI

0x230004 CALL	27ccc0 <@plt_start@+0xb0>

0x230009 CALL	27ceb0 <@plt_start@+0x2a0>

0x23000e CALL	27ceb0 <@plt_start@+0x2a0>

0x230013 MOV	(%R14),%RAX

0x230016 VMOVSD	0x10(%RSP),%XMM0

0x23001c VMINSD	(%RAX),%XMM0,%XMM0

0x230020 VMOVSD	%XMM0,(%RAX)

0x230024 CALL	27cec0 <@plt_start@+0x2b0>

0x230029 CALL	27cec0 <@plt_start@+0x2b0>

0x23002e XOR	%EDI,%EDI

0x230030 MOV	%EBX,%ESI

0x230032 CALL	27ccd0 <@plt_start@+0xc0>

0x230037 ADD	$0x68,%RSP

0x23003b POP	%RBX

0x23003c POP	%R12

0x23003e POP	%R13

0x230040 POP	%R14

0x230042 POP	%R15

0x230044 POP	%RBP

0x230045 RET

0x230046 MOV	0x20(%R14),%RDX

0x23004a MOV	0x18(%R14),%RCX

0x23004e VMOVSD	-0x2e290(%RIP),%XMM17

0x230058 VMOVDDUP	-0x2e238(%RIP),%XMM0

0x230060 VMOVDDUP	-0x2e268(%RIP),%XMM1

0x230068 LEA	(,%RAX,8),%R12

0x230070 MOV	%RSI,0x40(%RSP)

0x230075 MOVSXD	(%RDX),%RDX

0x230078 MOVSXD	(%RCX),%RCX

0x23007b MOV	%RDX,0x10(%RSP)

0x230080 LEA	0x8(,%RAX,8),%RDX

0x230088 MOV	%RCX,%RDI

0x23008b DEC	%RDI

0x23008e MOV	%RCX,0x38(%RSP)

0x230093 MOV	%RDI,0x30(%RSP)

0x230098 JMP	2300d2

0x23009a NOPW	(%RAX,%RAX,1)

(208) 0x2300a0 MOV	0x60(%RSP),%RAX

(208) 0x2300a5 MOV	0x40(%RSP),%RSI

(208) 0x2300aa MOV	0x38(%RSP),%RCX

(208) 0x2300af MOV	0x58(%RSP),%R12

(208) 0x2300b4 MOV	0x18(%RSP),%RDX

(208) 0x2300b9 MOV	0x50(%RSP),%RDI

(208) 0x2300be ADD	$0x8,%R12

(208) 0x2300c2 ADD	$0x8,%RDX

(208) 0x2300c6 CMP	%RSI,%RAX

(208) 0x2300c9 MOV	%RDI,%RAX

(208) 0x2300cc JE	22fff4

(208) 0x2300d2 CMP	%ECX,0x10(%RSP)

(208) 0x2300d6 JGE	2300e0

(208) 0x2300d8 LEA	0x1(%RAX),%RDI

(208) 0x2300dc JMP	2300be

0x2300de XCHG	%AX,%AX

(208) 0x2300e0 MOV	0x40(%R14),%RCX

(208) 0x2300e4 MOV	%RDX,0x18(%RSP)

(208) 0x2300e9 MOV	%RAX,%RDI

(208) 0x2300ec MOV	0xe0(%R14),%R9

(208) 0x2300f3 MOV	0x28(%R14),%R10

(208) 0x2300f7 MOV	0xf8(%R14),%RBX

(208) 0x2300fe MOV	%RAX,0x60(%RSP)

(208) 0x230103 INC	%RAX

(208) 0x230106 MOV	0xe8(%R14),%R11

(208) 0x23010d MOV	0x120(%R14),%R15

(208) 0x230114 MOV	%RAX,0x50(%RSP)

(208) 0x230119 MOV	0x110(%R14),%RAX

(208) 0x230120 MOV	(%RCX),%RSI

(208) 0x230123 MOV	0x88(%R14),%RCX

(208) 0x23012a MOV	(%R9),%R9

(208) 0x23012d VMOVSD	(%RBX),%XMM5

(208) 0x230131 MOV	0x108(%R14),%RBX

(208) 0x230138 VMOVSD	(%R15),%XMM6

(208) 0x23013d MOV	0x98(%R14),%R15

(208) 0x230144 MOV	%RAX,0x48(%RSP)

(208) 0x230149 MOV	%R12,%RAX

(208) 0x23014c MOV	%RAX,0x58(%RSP)

(208) 0x230151 MOV	(%RCX),%RDX

(208) 0x230154 MOV	0x48(%R14),%RCX

(208) 0x230158 SAL	$0x3,%R9

(208) 0x23015c MOV	(%RCX),%R8

(208) 0x23015f MOV	0x70(%R14),%RCX

(208) 0x230163 SAL	$0x3,%RDX

(208) 0x230167 SUB	(%RCX),%RDI

(208) 0x23016a MOV	0x50(%R14),%RCX

(208) 0x23016e SAL	$0x3,%R8

(208) 0x230172 SUB	%R8,%R10

(208) 0x230175 VMOVSD	(%RCX,%RDI,8),%XMM2

(208) 0x23017a MOV	0xc0(%R14),%RDI

(208) 0x230181 MOV	0xa0(%R14),%RCX

(208) 0x230188 MOV	(%RDI),%RDI

(208) 0x23018b VMOVSD	(%RCX),%XMM3

(208) 0x23018f MOV	0xa8(%R14),%RCX

(208) 0x230196 MOV	%RDI,%R8

(208) 0x230199 IMUL	0x18(%RSP),%RDI

(208) 0x23019f IMUL	%R12,%R8

(208) 0x2301a3 VMOVSD	(%RCX),%XMM4

(208) 0x2301a7 MOV	0xb0(%R14),%RCX

(208) 0x2301ae SUB	%R9,%R8

(208) 0x2301b1 VXORPD	%XMM0,%XMM3,%XMM7

(208) 0x2301b5 LEA	0x8(%R11,%R8,1),%R13

(208) 0x2301ba MOV	%RSI,%R11

(208) 0x2301bd IMUL	0x18(%RSP),%RSI

(208) 0x2301c3 IMUL	%RAX,%R11

(208) 0x2301c7 LEA	0x8(%RBX,%R8,1),%R12

(208) 0x2301cc MOV	0x48(%RSP),%RAX

(208) 0x2301d1 LEA	0x8(%RCX,%R8,1),%RBP

(208) 0x2301d6 MOV	0x78(%R14),%R8

(208) 0x2301da SUB	%R9,%RDI

(208) 0x2301dd SUB	%RDX,%R11

(208) 0x2301e0 LEA	0x8(%RBX,%RDI,1),%RBX

(208) 0x2301e5 LEA	0x8(%RCX,%RDI,1),%RDI

(208) 0x2301ea MOV	0x90(%R14),%RCX

(208) 0x2301f1 ADD	%R11,%R15

(208) 0x2301f4 LEA	(%RAX,%R11,1),%R9

(208) 0x2301f8 ADD	%R11,%R8

(208) 0x2301fb SUB	%RDX,%RSI

(208) 0x2301fe MOV	0x30(%RSP),%RDX

(208) 0x230203 ADD	%RAX,%RSI

(208) 0x230206 ADD	%R11,%RCX

(208) 0x230209 ADD	0x100(%R14),%R11

(208) 0x230210 JMP	2302ce

0x230215 NOPW	%CS:(%RAX,%RAX,1)

  (209) 0x230220 MOV	0x130(%R14),%RAX

  (209) 0x230227 VMOVSD	(%RAX),%XMM14

  (209) 0x23022b VMOVSD	0x8(%RCX,%RDX,8),%XMM16

  (209) 0x230233 VMOVSD	0x8(%R8,%RDX,8),%XMM15

  (209) 0x23023a VMULSD	%XMM3,%XMM13,%XMM13

  (209) 0x23023e VANDPD	%XMM1,%XMM11,%XMM11

  (209) 0x230242 VANDPD	%XMM1,%XMM9,%XMM9

  (209) 0x230246 VANDPD	%XMM1,%XMM10,%XMM10

  (209) 0x23024a VMAXSD	%XMM9,%XMM11,%XMM9

  (209) 0x23024f VANDPD	%XMM1,%XMM12,%XMM11

  (209) 0x230253 VMAXSD	%XMM10,%XMM11,%XMM10

  (209) 0x230258 VMAXSD	%XMM9,%XMM13,%XMM9

  (209) 0x23025d VMAXSD	%XMM10,%XMM13,%XMM10

  (209) 0x230262 VADDSD	%XMM16,%XMM16,%XMM16

  (209) 0x230268 VDIVSD	0x8(%R15,%RDX,8),%XMM16,%XMM16

  (209) 0x230270 VFMADD231SD	%XMM15,%XMM15,%XMM16

  (209) 0x230276 VSQRTSD	%XMM16,%XMM16,%XMM15

  (209) 0x23027c VMINSD	0x8(%R10,%RDX,8),%XMM2,%XMM16

  (209) 0x230284 INC	%RDX

  (209) 0x230287 VMULSD	%XMM16,%XMM4,%XMM16

  (209) 0x23028d VMAXSD	%XMM15,%XMM3,%XMM15

  (209) 0x230292 VDIVSD	%XMM15,%XMM16,%XMM15

  (209) 0x230298 VMINSD	%XMM17,%XMM15,%XMM15

  (209) 0x23029e VMULSD	%XMM5,%XMM8,%XMM17

  (209) 0x2302a4 VMULSD	%XMM6,%XMM8,%XMM8

  (209) 0x2302a8 VDIVSD	%XMM9,%XMM17,%XMM9

  (209) 0x2302ae VDIVSD	%XMM10,%XMM8,%XMM8

  (209) 0x2302b3 VMINSD	%XMM15,%XMM9,%XMM9

  (209) 0x2302b8 VMINSD	%XMM9,%XMM8,%XMM8

  (209) 0x2302bd VMINSD	%XMM8,%XMM14,%XMM17

  (209) 0x2302c3 CMP	%RDX,0x10(%RSP)

  (209) 0x2302c8 JE	2300a0

  (209) 0x2302ce VMOVSD	(%RBP,%RDX,8),%XMM8

  (209) 0x2302d4 VMOVSD	0x8(%RBP,%RDX,8),%XMM10

  (209) 0x2302da VMOVSD	(%RBX,%RDX,8),%XMM12

  (209) 0x2302df VMOVSD	0x8(%R11,%RDX,8),%XMM13

  (209) 0x2302e6 VADDSD	(%RDI,%RDX,8),%XMM8,%XMM8

  (209) 0x2302eb VADDSD	0x8(%RBX,%RDX,8),%XMM12,%XMM12

  (209) 0x2302f1 VMULSD	(%R13,%RDX,8),%XMM8,%XMM9

  (209) 0x2302f8 VADDSD	0x8(%RDI,%RDX,8),%XMM10,%XMM8

  (209) 0x2302fe VMOVSD	(%R12,%RDX,8),%XMM10

  (209) 0x230304 VMULSD	0x8(%RSI,%RDX,8),%XMM12,%XMM12

  (209) 0x23030a VADDSD	0x8(%R12,%RDX,8),%XMM10,%XMM10

  (209) 0x230311 VMULSD	0x8(%R13,%RDX,8),%XMM8,%XMM11

  (209) 0x230318 VMULSD	0x8(%R9,%RDX,8),%XMM10,%XMM10

  (209) 0x23031f VADDSD	%XMM13,%XMM13,%XMM8

  (209) 0x230324 VADDSD	%XMM10,%XMM9,%XMM14

  (209) 0x230329 VSUBSD	%XMM14,%XMM11,%XMM14

  (209) 0x23032e VADDSD	%XMM12,%XMM14,%XMM14

  (209) 0x230333 VDIVSD	%XMM8,%XMM14,%XMM14

  (209) 0x230338 VUCOMISD	%XMM7,%XMM14

  (209) 0x23033c JAE	230220

  (209) 0x230342 MOV	0x128(%R14),%RAX

  (209) 0x230349 VMOVSD	(%RAX),%XMM15

  (209) 0x23034d VXORPD	%XMM0,%XMM15,%XMM15

  (209) 0x230351 VDIVSD	%XMM14,%XMM15,%XMM14

  (209) 0x230356 JMP	23022b

0x23035b INT	$0x3

0x23035c INT	$0x3

0x23035d INT	$0x3

0x23035e INT	$0x3

0x23035f INT	$0x3

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_10

Source file and lines	calc_dt_kernel.f90:89-135
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-99,107-135.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.50 to 3.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 10.50 to 0.77 cycles (13.71x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 120 bytes (15 double precision FP elements). The binary function is storing 68 bytes (8 double precision FP elements).

General properties

nb instructions	85
nb uops	84
loop length	322
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	9.25	9.25	9.25	9.25	0.75	0.75	0.75	0.75	1.00	1.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	9.25	9.25	9.25	9.25	0.75	0.75	0.75	0.75	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.50
Dispatch	9.25
Overall L1	10.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.50 cycles. At this rate:

4% of peak load performance is reached (11.43 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.50 to 9.25 cycles (1.14x speedup).

ASM code

In the binary file, the address of the function is: 22ff70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RAX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVL $0x1,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EBX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x30(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x34(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x14(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x10(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 27ccb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD -0x2e21a(%RIP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD 0xc(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 22fff4 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x84>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0x8(%RSP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP %EAX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 230046 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0xd6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x24(%RSP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
VMOVSD %XMM17,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 27ccc0 <@plt_start@+0xb0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 27ceb0 <@plt_start@+0x2a0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 27ceb0 <@plt_start@+0x2a0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV (%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x10(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMINSD (%RAX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 27cec0 <@plt_start@+0x2b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 27cec0 <@plt_start@+0x2b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 27ccd0 <@plt_start@+0xc0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x20(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x2e290(%RIP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2e238(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2e268(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
LEA (,%RAX,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD (%RDX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVSXD (%RCX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x8(,%RAX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DEC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 2300d2 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x162>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_10

Source file and lines	calc_dt_kernel.f90:89-135
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.50 to 3.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

General properties

nb instructions	85
nb uops	84
loop length	322
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	9.25	9.25	9.25	9.25	0.75	0.75	0.75	0.75	1.00	1.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	9.25	9.25	9.25	9.25	0.75	0.75	0.75	0.75	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.50
Dispatch	9.25
Overall L1	10.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.50 cycles. At this rate:

4% of peak load performance is reached (11.43 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 22ff70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RAX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVL $0x1,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EBX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x30(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x34(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x14(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x10(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 27ccb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD -0x2e21a(%RIP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD 0xc(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 22fff4 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x84>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0x8(%RSP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP %EAX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 230046 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0xd6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x24(%RSP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
VMOVSD %XMM17,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 27ccc0 <@plt_start@+0xb0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 27ceb0 <@plt_start@+0x2a0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 27ceb0 <@plt_start@+0x2a0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV (%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x10(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMINSD (%RAX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 27cec0 <@plt_start@+0x2b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 27cec0 <@plt_start@+0x2b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 27ccd0 <@plt_start@+0xc0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x20(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x2e290(%RIP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2e238(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2e268(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
LEA (,%RAX,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD (%RDX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVSXD (%RCX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x8(,%RAX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DEC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 2300d2 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x162>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

Name	Coverage (%)	Time (s)
▼__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1–	3.43	1.28
▼Loop 208 - calc_dt_kernel.f90:94-132 - exec–	0.00	0.01
○Loop 209 - calc_dt_kernel.f90:107-131 - exec	3.43	1.28

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