OV - exec - Loop 894

	Loop Id: 894	Module: exec	Source: viscosity_kernel.f90:54-89	Coverage: 2.26%

0x47dbc0 LEA	0x1(%RAX),%R12

0x47dbc4 MOVQ	$0,(%R11,%RAX,8)    [8]

0x47dbcc CMP	%RAX,%RBX

0x47dbcf JE	47ddb0

0x47dbd5 MOV	%R12,%RAX

0x47dbd8 VMOVSD	0x8(%R9,%RAX,8),%XMM27    [3]

0x47dbe0 VMOVSD	(%R9,%RAX,8),%XMM28    [3]

0x47dbe7 VMOVSD	(%R8,%RAX,8),%XMM29    [1]

0x47dbee VMOVSD	(%RDI,%RAX,8),%XMM24    [11]

0x47dbf5 VADDSD	%XMM29,%XMM28,%XMM3

0x47dbfb VMOVSD	(%RSI,%RAX,8),%XMM25    [7]

0x47dc02 VMOVSD	0x8(%RSI,%RAX,8),%XMM26    [7]

0x47dc0a VMOVSD	(%R13,%RAX,8),%XMM2    [10]

0x47dc11 VADDSD	%XMM26,%XMM25,%XMM30

0x47dc17 VMOVSD	(%R15,%RDX,8),%XMM8    [13]

0x47dc1d VMOVSD	0x8(%R8,%RAX,8),%XMM1    [1]

0x47dc24 VMOVSD	0x8(%RDI,%RAX,8),%XMM0    [11]

0x47dc2a VADDSD	%XMM1,%XMM27,%XMM5

0x47dc30 VADDSD	%XMM0,%XMM24,%XMM4

0x47dc36 VSUBSD	%XMM3,%XMM5,%XMM7

0x47dc3a VADDSD	%XMM29,%XMM1,%XMM1

0x47dc40 VSUBSD	%XMM30,%XMM4,%XMM3

0x47dc46 VSUBSD	%XMM28,%XMM1,%XMM5

0x47dc4c VADDSD	%XMM26,%XMM0,%XMM0

0x47dc52 VSUBSD	%XMM27,%XMM5,%XMM4

0x47dc58 VMOVSD	0x8(%RCX,%RAX,8),%XMM31    [4]

0x47dc60 VMULSD	%XMM6,%XMM4,%XMM1

0x47dc64 VSUBSD	-0x8(%RCX,%RAX,8),%XMM31,%XMM27    [4]

0x47dc6c VSUBSD	%XMM25,%XMM0,%XMM4

0x47dc72 VDIVSD	%XMM8,%XMM1,%XMM5

0x47dc77 VADDSD	0x8(%R15,%RDX,8),%XMM8,%XMM28    [13]

0x47dc7f VSUBSD	%XMM24,%XMM4,%XMM1

0x47dc85 VMULSD	%XMM6,%XMM7,%XMM31

0x47dc8b VMULSD	%XMM6,%XMM1,%XMM0

0x47dc8f VADDSD	0x8(%R13,%RAX,8),%XMM2,%XMM1    [10]

0x47dc96 VDIVSD	%XMM2,%XMM0,%XMM4

0x47dc9a VDIVSD	%XMM1,%XMM27,%XMM24

0x47dca0 VADDSD	%XMM4,%XMM5,%XMM5

0x47dca4 VMOVSD	(%R10,%RAX,8),%XMM0    [2]

0x47dcaa VMULSD	%XMM24,%XMM24,%XMM30

0x47dcb0 VSUBSD	(%R14,%RAX,8),%XMM0,%XMM4    [6]

0x47dcb6 VDIVSD	%XMM2,%XMM31,%XMM27

0x47dcbc VDIVSD	%XMM28,%XMM4,%XMM1

0x47dcc2 VMULSD	%XMM6,%XMM3,%XMM28

0x47dcc8 VMULSD	%XMM1,%XMM1,%XMM29

0x47dcce VADDSD	%XMM29,%XMM30,%XMM25

0x47dcd4 VMAXSD	%XMM10,%XMM25,%XMM26

0x47dcda VDIVSD	%XMM8,%XMM28,%XMM25

0x47dce0 VMULSD	%XMM29,%XMM25,%XMM29

0x47dce6 VFMADD132SD	%XMM27,%XMM29,%XMM30

0x47dcec VMULSD	%XMM24,%XMM5,%XMM5

0x47dcf2 VFMADD132SD	%XMM1,%XMM30,%XMM5

0x47dcf8 VDIVSD	%XMM26,%XMM5,%XMM0

0x47dcfe VCOMISD	%XMM9,%XMM0

0x47dd03 JA	47dbc0

0x47dd09 VMULSD	%XMM7,%XMM2,%XMM7

0x47dd0d VFMADD132SD	%XMM8,%XMM7,%XMM3

0x47dd12 VCOMISD	%XMM9,%XMM3

0x47dd17 JAE	47dbc0

0x47dd1d VANDPD	%XMM11,%XMM24,%XMM3

0x47dd23 VCOMISD	%XMM24,%XMM9

0x47dd29 VMAXSD	%XMM10,%XMM3,%XMM4

0x47dd2e JA	47de20

0x47dd34 VMOVAPD	%XMM22,%XMM24

0x47dd3a VANDPD	%XMM11,%XMM1,%XMM1

0x47dd3f MOV	-0x38(%RBP),%R12    [9]

0x47dd43 VMAXSD	%XMM10,%XMM1,%XMM7

0x47dd48 VMULSD	%XMM7,%XMM24,%XMM30

0x47dd4e VMULSD	%XMM30,%XMM30,%XMM3

0x47dd54 VFMADD231SD	%XMM4,%XMM4,%XMM3

0x47dd59 VSQRTSD	%XMM3,%XMM3,%XMM3

0x47dd5d VMULSD	%XMM3,%XMM2,%XMM2

0x47dd61 VMULSD	%XMM3,%XMM8,%XMM8

0x47dd65 VDIVSD	%XMM4,%XMM2,%XMM4

0x47dd69 VDIVSD	%XMM30,%XMM8,%XMM1

0x47dd6f VANDPD	%XMM11,%XMM4,%XMM5

0x47dd74 VANDPD	%XMM11,%XMM1,%XMM7

0x47dd79 VMOVSD	(%R12,%RAX,8),%XMM2    [5]

0x47dd7f VMINSD	%XMM7,%XMM5,%XMM3

0x47dd83 VADDSD	%XMM2,%XMM2,%XMM4

0x47dd87 VMULSD	%XMM3,%XMM3,%XMM5

0x47dd8b LEA	0x1(%RAX),%R12

0x47dd8f VMULSD	%XMM5,%XMM4,%XMM8

0x47dd93 VMULSD	%XMM0,%XMM8,%XMM1

0x47dd97 VMULSD	%XMM0,%XMM1,%XMM0

0x47dd9b VMOVSD	%XMM0,(%R11,%RAX,8)    [8]

0x47dda1 CMP	%RAX,%RBX

0x47dda4 JNE	47dbd5

0x47de20 VXORPD	%XMM23,%XMM4,%XMM5

0x47de26 VCOMISD	%XMM9,%XMM4

0x47de2b VMOVAPD	%XMM5,%XMM4

0x47de2f JBE	47de6d

0x47de31 VMOVSD	0x24af5(%RIP),%XMM24    [12]

0x47de3b JMP	47dd3a

0x47de6d VMOVSD	0x24aa9(%RIP),%XMM24    [12]

0x47de77 JMP	47dd3a

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 54 - 89

--------------------------------------------------------------------------------

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Coverage (%)	Name	Source Location	Module
►95.67+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►4.15+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:98	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	8.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.83
Bottlenecks	P10, P11,
Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:54-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	44.50
CQA cycles if no scalar integer	44.50
CQA cycles if FP arith vectorized	5.56
CQA cycles if fully vectorized	5.56
Front-end cycles	12.50
P0 cycles	1.33
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	2.67
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	5.50
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	15.75
P11 cycles	15.75
P12 cycles	15.75
P13 cycles	15.75
P14 cycles	2.50
P15 cycles	2.50
DIV/SQRT cycles	44.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	96.00
Nb uops	100.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	1.00
FLOP/cycle	1.21
Nb FLOP add-sub	19.00
Nb FLOP mul	17.00
Nb FLOP fma	4.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.96
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.43
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	43.75
Vector-efficiency ratio all	13.48
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.97

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	8.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.83
Bottlenecks	P10, P11,
Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:54-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	44.50
CQA cycles if no scalar integer	44.50
CQA cycles if FP arith vectorized	5.56
CQA cycles if fully vectorized	5.56
Front-end cycles	12.50
P0 cycles	1.33
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	2.67
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	5.50
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	15.75
P11 cycles	15.75
P12 cycles	15.75
P13 cycles	15.75
P14 cycles	2.50
P15 cycles	2.50
DIV/SQRT cycles	44.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	96.00
Nb uops	100.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	1.00
FLOP/cycle	1.21
Nb FLOP add-sub	19.00
Nb FLOP mul	17.00
Nb FLOP fma	4.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.96
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.43
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	43.75
Vector-efficiency ratio all	13.48
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.97

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:54-89
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:54-89.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 44.50 to 5.56 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 44.50 to 15.75 cycles (2.83x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 44.50 to 18.50 cycles (2.41x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:78
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:81

Type of elements and instruction set

58 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 54 FP arithmetical operations:

23: addition or subtraction (4 inside FMA instructions)
21: multiply (4 inside FMA instructions)
9: divide
1: square root

The binary loop is loading 160 bytes (20 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	100
loop length	537
used x86 registers	15
used mmx registers	0
used xmm registers	22
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	2.67	2.67	2.67	5.50	5.50	5.50	5.50	15.75	15.75	15.75	15.75	2.50	2.50
cycles	1.33	1.33	1.33	2.67	2.67	2.67	5.50	5.50	5.50	5.50	15.75	15.75	15.75	15.75	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

44.50

Cycles summary

Front-end	12.50
Dispatch	15.75
DIV/SQRT	44.50
Overall L1	44.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	46%

INT+FP

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	43%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	13%
load	12%
store	9%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.50 cycles. At this rate:

1% of peak load performance is reached (3.60 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 47dbd8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
LEA 0x1(%RAX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVQ $0,(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47ddb0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x4a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%R9,%RAX,8),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R9,%RAX,8),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R8,%RAX,8),%XMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM29,%XMM28,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD (%RSI,%RAX,8),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RSI,%RAX,8),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R13,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM26,%XMM25,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD (%R15,%RDX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R8,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM1,%XMM27,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM0,%XMM24,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM5,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM29,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM30,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM28,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM26,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM27,%XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD 0x8(%RCX,%RAX,8),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM6,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD -0x8(%RCX,%RAX,8),%XMM31,%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM25,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM8,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VADDSD 0x8(%R15,%RDX,8),%XMM8,%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM24,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM6,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD 0x8(%R13,%RAX,8),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM2,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM1,%XMM27,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VADDSD %XMM4,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD (%R10,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM24,%XMM24,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD (%R14,%RAX,8),%XMM0,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM2,%XMM31,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM28,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM6,%XMM3,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM29,%XMM30,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM10,%XMM25,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM8,%XMM28,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM29,%XMM25,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM27,%XMM29,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM24,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM1,%XMM30,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM26,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VCOMISD %XMM9,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JA 47dbc0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD %XMM7,%XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM8,%XMM7,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM9,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 47dbc0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VANDPD %XMM11,%XMM24,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCOMISD %XMM24,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VMAXSD %XMM10,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
JA 47de20 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x510>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVAPD %XMM22,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VANDPD %XMM11,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV -0x38(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMAXSD %XMM10,%XMM1,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM7,%XMM24,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM30,%XMM30,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM4,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
VMULSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM4,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM30,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VANDPD %XMM11,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM11,%XMM1,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVSD (%R12,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMINSD %XMM7,%XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM2,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
LEA 0x1(%RAX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD %XMM5,%XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 47dbd5 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x2c5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPD %XMM23,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCOMISD %XMM9,%XMM4	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JBE 47de6d <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x55d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD 0x24af5(%RIP),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 47dd3a <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x42a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSD 0x24aa9(%RIP),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 47dd3a <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x42a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:54-89
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 44.50 to 18.50 cycles (2.41x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:78
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:81

Type of elements and instruction set

58 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 54 FP arithmetical operations:

23: addition or subtraction (4 inside FMA instructions)
21: multiply (4 inside FMA instructions)
9: divide
1: square root

The binary loop is loading 160 bytes (20 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	100
loop length	537
used x86 registers	15
used mmx registers	0
used xmm registers	22
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	2.67	2.67	2.67	5.50	5.50	5.50	5.50	15.75	15.75	15.75	15.75	2.50	2.50
cycles	1.33	1.33	1.33	2.67	2.67	2.67	5.50	5.50	5.50	5.50	15.75	15.75	15.75	15.75	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

44.50

Cycles summary

Front-end	12.50
Dispatch	15.75
DIV/SQRT	44.50
Overall L1	44.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	46%

INT+FP

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	43%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	13%
load	12%
store	9%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.50 cycles. At this rate:

1% of peak load performance is reached (3.60 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 47dbd8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
LEA 0x1(%RAX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVQ $0,(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 47ddb0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x4a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%R9,%RAX,8),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R9,%RAX,8),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R8,%RAX,8),%XMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM29,%XMM28,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD (%RSI,%RAX,8),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RSI,%RAX,8),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R13,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM26,%XMM25,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD (%R15,%RDX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R8,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM1,%XMM27,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM0,%XMM24,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM5,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM29,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM30,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM28,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM26,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM27,%XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD 0x8(%RCX,%RAX,8),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM6,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD -0x8(%RCX,%RAX,8),%XMM31,%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM25,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM8,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VADDSD 0x8(%R15,%RDX,8),%XMM8,%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM24,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM6,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD 0x8(%R13,%RAX,8),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM2,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM1,%XMM27,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VADDSD %XMM4,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD (%R10,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM24,%XMM24,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD (%R14,%RAX,8),%XMM0,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM2,%XMM31,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM28,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM6,%XMM3,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM29,%XMM30,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM10,%XMM25,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM8,%XMM28,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM29,%XMM25,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM27,%XMM29,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM24,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM1,%XMM30,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VDIVSD %XMM26,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VCOMISD %XMM9,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JA 47dbc0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD %XMM7,%XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM8,%XMM7,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM9,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 47dbc0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VANDPD %XMM11,%XMM24,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCOMISD %XMM24,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VMAXSD %XMM10,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
JA 47de20 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x510>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVAPD %XMM22,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VANDPD %XMM11,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV -0x38(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMAXSD %XMM10,%XMM1,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM7,%XMM24,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM30,%XMM30,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM4,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
VMULSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM4,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM30,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VANDPD %XMM11,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM11,%XMM1,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVSD (%R12,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMINSD %XMM7,%XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM2,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM3,%XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
LEA 0x1(%RAX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD %XMM5,%XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 47dbd5 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x2c5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPD %XMM23,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCOMISD %XMM9,%XMM4	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JBE 47de6d <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x55d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD 0x24af5(%RIP),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 47dd3a <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x42a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSD 0x24aa9(%RIP),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 47dd3a <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x42a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

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Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code