OV - exec - Loop 70

	Loop Id: 70	Module: exec	Source: accelerate_kernel.f90:67-76	Coverage: 5.28%

0x418570 VMOVQ	%XMM14,%R10

0x418575 VMOVQ	%XMM13,%R8

0x41857a VMOVUPD	(%R10,%RAX,1),%ZMM0    [6]

0x418581 VMULPD	(%R8,%RAX,1),%ZMM0,%ZMM1    [20]

0x418588 VMOVQ	%XMM25,%R10

0x41858e VMOVQ	%XMM26,%R8

0x418594 VMOVUPD	(%R10,%RAX,1),%ZMM4    [5]

0x41859b VMOVQ	%XMM11,%R10

0x4185a0 VFMADD231PD	(%R8,%RAX,1),%ZMM4,%ZMM1    [19]

0x4185a7 VMOVQ	%XMM12,%R8

0x4185ac VMOVUPD	(%R8,%RAX,1),%ZMM3    [17]

0x4185b3 VMOVQ	%XMM10,%R8

0x4185b8 VFMADD231PD	(%R10,%RAX,1),%ZMM3,%ZMM1    [4]

0x4185bf VMOVQ	%XMM9,%R10

0x4185c4 VMOVUPD	(%R8,%RAX,1),%ZMM7    [16]

0x4185cb VFMADD231PD	(%R10,%RAX,1),%ZMM7,%ZMM1    [3]

0x4185d2 VMULPD	%ZMM5,%ZMM1,%ZMM0

0x4185d8 MOV	0x2a8(%RSP),%R10    [24]

0x4185e0 VMOVQ	%XMM8,%R8

0x4185e5 VMOVUPD	(%RBX,%RAX,1),%ZMM1    [25]

0x4185ec VSUBPD	(%R11,%RAX,1),%ZMM1,%ZMM3    [21]

0x4185f3 VMOVUPD	(%R8,%RAX,1),%ZMM24    [15]

0x4185fa MOV	0x2b8(%RSP),%R8    [24]

0x418602 VDIVPD	%ZMM0,%ZMM6,%ZMM4

0x418608 VSUBPD	(%R10,%RAX,1),%ZMM24,%ZMM24    [2]

0x41860f VMULPD	(%RSI,%RAX,1),%ZMM24,%ZMM24    [9]

0x418616 VFMADD132PD	(%RDI,%RAX,1),%ZMM24,%ZMM3    [14]

0x41861d VFNMADD213PD	(%R8,%RAX,1),%ZMM4,%ZMM3    [12]

0x418624 VMOVUPD	%ZMM3,(%RCX,%RAX,1)    [8]

0x41862b VMOVUPD	(%R11,%RAX,1),%ZMM24    [21]

0x418632 VSUBPD	(%R10,%RAX,1),%ZMM24,%ZMM24    [2]

0x418639 MOV	0x2b0(%RSP),%R10    [24]

0x418641 VMULPD	(%R15,%RAX,1),%ZMM24,%ZMM24    [23]

0x418648 VMOVQ	%XMM8,%R8

0x41864d VMOVUPD	(%RBX,%RAX,1),%ZMM7    [25]

0x418654 VSUBPD	(%R8,%RAX,1),%ZMM7,%ZMM0    [11]

0x41865b VMOVQ	%XMM2,%R8

0x418660 VFMADD132PD	(%R14,%RAX,1),%ZMM24,%ZMM0    [22]

0x418667 VFNMADD213PD	(%R10,%RAX,1),%ZMM4,%ZMM0    [1]

0x41866e VMOVUPD	%ZMM0,(%RDX,%RAX,1)    [26]

0x418675 VMOVUPD	(%R9,%RAX,1),%ZMM24    [7]

0x41867c VSUBPD	(%R8,%RAX,1),%ZMM24,%ZMM24    [10]

0x418683 VMULPD	(%RSI,%RAX,1),%ZMM24,%ZMM24    [9]

0x41868a VMOVUPD	(%R12,%RAX,1),%ZMM1    [18]

0x418691 VSUBPD	(%R13,%RAX,1),%ZMM1,%ZMM3    [13]

0x418699 VFMADD132PD	(%RDI,%RAX,1),%ZMM24,%ZMM3    [14]

0x4186a0 MOV	0x2a0(%RSP),%R10    [24]

0x4186a8 VFNMADD213PD	(%RCX,%RAX,1),%ZMM4,%ZMM3    [8]

0x4186af VMOVUPD	%ZMM3,(%RCX,%RAX,1)    [8]

0x4186b6 VMOVUPD	(%R13,%RAX,1),%ZMM24    [13]

0x4186be VSUBPD	(%R8,%RAX,1),%ZMM24,%ZMM24    [10]

0x4186c5 VMOVUPD	(%R12,%RAX,1),%ZMM7    [18]

0x4186cc VMULPD	(%R15,%RAX,1),%ZMM24,%ZMM24    [23]

0x4186d3 VSUBPD	(%R9,%RAX,1),%ZMM7,%ZMM0    [7]

0x4186da VFMADD132PD	(%R14,%RAX,1),%ZMM24,%ZMM0    [22]

0x4186e1 VFNMADD213PD	(%RDX,%RAX,1),%ZMM0,%ZMM4    [26]

0x4186e8 VMOVUPD	%ZMM4,(%RDX,%RAX,1)    [26]

0x4186ef ADD	$0x40,%RAX

0x4186f3 CMP	%R10,%RAX

0x4186f6 JNE	418570

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 67 - 76

--------------------------------------------------------------------------------

67:           *0.25_8)

68:

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

76:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

Coverage (%)	Name	Source Location	Module
►95.65+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►4.18+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	accelerate_kernel	accelerate_kernel.f90:83	exec
○	accelerate	accelerate.f90:41	exec
○	hydro	hydro.f90:58	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P6, P7, P8, P9,
Function	__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0
Source	accelerate_kernel.f90:67-76
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	11.00
CQA cycles if no scalar integer	10.75
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	11.00
Front-end cycles	7.38
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	11.00
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	9.00
P11 cycles	9.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	7.50
P15 cycles	7.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	59.00
Nb loads	40.00
Nb stores	4.00
Nb stack references	4.00
FLOP/cycle	26.91
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	88.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	235.64
Bytes prefetched	0.00
Bytes loaded	2336.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	25.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	79.25
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	81.84
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P6, P7, P8, P9,
Function	__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0
Source	accelerate_kernel.f90:67-76
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	11.00
CQA cycles if no scalar integer	10.75
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	11.00
Front-end cycles	7.38
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	11.00
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	9.00
P11 cycles	9.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	7.50
P15 cycles	7.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	59.00
Nb loads	40.00
Nb stores	4.00
Nb stack references	4.00
FLOP/cycle	26.91
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	88.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	235.64
Bytes prefetched	0.00
Bytes loaded	2336.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	25.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	79.25
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	81.84
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0
Source file and lines	accelerate_kernel.f90:67-76
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67-76.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 81% of vector register length is used (average across all SSE/AVX instructions).

Details

79% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 11.00 to 9.00 cycles (1.22x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 88 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Vector unaligned load/store instructions

Detected 16 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 16 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:70
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:70
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:70
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:72
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:72
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:72
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:76
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:76
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:76

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

26 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 296 FP arithmetical operations:

152: addition or subtraction (88 inside FMA instructions)
136: multiply (88 inside FMA instructions)
8: divide

The binary loop is loading 2336 bytes (292 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	59
loop length	396
used x86 registers	15
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	8
nb stack references	4
ADD-SUB / MUL ratio	1.33

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.38 cycles
front end	7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	11.00	11.00	11.00	11.00	9.00	9.00	4.00	4.00	7.50	7.50
cycles	0.33	0.33	0.33	0.33	0.33	0.33	11.00	11.00	11.00	11.00	9.00	9.00	4.00	4.00	7.50	7.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.38
Dispatch	11.00
DIV/SQRT	4.00
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	79%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	81%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

82% of peak load performance is reached (212.36 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (23.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 418570

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVQ %XMM14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM13,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%R10,%RAX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD (%R8,%RAX,1),%ZMM0,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM25,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM26,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%R10,%RAX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFMADD231PD (%R8,%RAX,1),%ZMM4,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVQ %XMM12,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%R8,%RAX,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFMADD231PD (%R10,%RAX,1),%ZMM3,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVQ %XMM9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%R8,%RAX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD (%R10,%RAX,1),%ZMM7,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x2a8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%RBX,%RAX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R11,%RAX,1),%ZMM1,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R8,%RAX,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x2b8(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VDIVPD %ZMM0,%ZMM6,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VSUBPD (%R10,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD (%RSI,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD (%RDI,%RAX,1),%ZMM24,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFNMADD213PD (%R8,%RAX,1),%ZMM4,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%RCX,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%R11,%RAX,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R10,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOV 0x2b0(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULPD (%R15,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%RBX,%RAX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R8,%RAX,1),%ZMM7,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVQ %XMM2,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFMADD132PD (%R14,%RAX,1),%ZMM24,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFNMADD213PD (%R10,%RAX,1),%ZMM4,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%RDX,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%R9,%RAX,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R8,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD (%RSI,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R13,%RAX,1),%ZMM1,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD132PD (%RDI,%RAX,1),%ZMM24,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x2a0(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFNMADD213PD (%RCX,%RAX,1),%ZMM4,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%RCX,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%R13,%RAX,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R8,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD (%R15,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R9,%RAX,1),%ZMM7,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD132PD (%R14,%RAX,1),%ZMM24,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFNMADD213PD (%RDX,%RAX,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%RDX,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x40,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 418570 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x990>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0
Source file and lines	accelerate_kernel.f90:67-76
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 81% of vector register length is used (average across all SSE/AVX instructions).

Details

79% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 11.00 to 9.00 cycles (1.22x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 88 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Vector unaligned load/store instructions

Detected 16 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 16 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:67
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:70
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:70
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:70
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:72
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:72
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:72
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:76
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:76
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:76

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

26 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 296 FP arithmetical operations:

152: addition or subtraction (88 inside FMA instructions)
136: multiply (88 inside FMA instructions)
8: divide

The binary loop is loading 2336 bytes (292 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	59
loop length	396
used x86 registers	15
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	8
nb stack references	4
ADD-SUB / MUL ratio	1.33

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.38 cycles
front end	7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	11.00	11.00	11.00	11.00	9.00	9.00	4.00	4.00	7.50	7.50
cycles	0.33	0.33	0.33	0.33	0.33	0.33	11.00	11.00	11.00	11.00	9.00	9.00	4.00	4.00	7.50	7.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.38
Dispatch	11.00
DIV/SQRT	4.00
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	79%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	81%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

82% of peak load performance is reached (212.36 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (23.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 418570

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVQ %XMM14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM13,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%R10,%RAX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD (%R8,%RAX,1),%ZMM0,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM25,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM26,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%R10,%RAX,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFMADD231PD (%R8,%RAX,1),%ZMM4,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVQ %XMM12,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%R8,%RAX,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFMADD231PD (%R10,%RAX,1),%ZMM3,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVQ %XMM9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%R8,%RAX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD (%R10,%RAX,1),%ZMM7,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x2a8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%RBX,%RAX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R11,%RAX,1),%ZMM1,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R8,%RAX,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x2b8(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VDIVPD %ZMM0,%ZMM6,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VSUBPD (%R10,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD (%RSI,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD (%RDI,%RAX,1),%ZMM24,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFNMADD213PD (%R8,%RAX,1),%ZMM4,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%RCX,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%R11,%RAX,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R10,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOV 0x2b0(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULPD (%R15,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVUPD (%RBX,%RAX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R8,%RAX,1),%ZMM7,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVQ %XMM2,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFMADD132PD (%R14,%RAX,1),%ZMM24,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFNMADD213PD (%R10,%RAX,1),%ZMM4,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%RDX,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%R9,%RAX,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R8,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD (%RSI,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R13,%RAX,1),%ZMM1,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD132PD (%RDI,%RAX,1),%ZMM24,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x2a0(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFNMADD213PD (%RCX,%RAX,1),%ZMM4,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%RCX,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%R13,%RAX,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R8,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R12,%RAX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD (%R15,%RAX,1),%ZMM24,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD (%R9,%RAX,1),%ZMM7,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD132PD (%R14,%RAX,1),%ZMM24,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFNMADD213PD (%RDX,%RAX,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%RDX,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x40,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 418570 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x990>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code