OV - exec - Loop 189

0x4307d4 VBROADCASTSD	(%R13),%ZMM9    [2]

0x4307db ADD	$0x200,%RAX

0x4307e1 VMOVUPD	%ZMM9,-0x200(%RAX)    [1]

0x4307e8 VBROADCASTSD	(%R13),%ZMM10    [2]

0x4307ef VMOVUPD	%ZMM10,-0x1c0(%RAX)    [1]

0x4307f6 VBROADCASTSD	(%R13),%ZMM11    [2]

0x4307fd VMOVUPD	%ZMM11,-0x180(%RAX)    [1]

0x430804 VBROADCASTSD	(%R13),%ZMM12    [2]

0x43080b VMOVUPD	%ZMM12,-0x140(%RAX)    [1]

0x430812 VBROADCASTSD	(%R13),%ZMM13    [2]

0x430819 VMOVUPD	%ZMM13,-0x100(%RAX)    [1]

0x430820 VBROADCASTSD	(%R13),%ZMM14    [2]

0x430827 VMOVUPD	%ZMM14,-0xc0(%RAX)    [1]

0x43082e VBROADCASTSD	(%R13),%ZMM15    [2]

0x430835 VMOVUPD	%ZMM15,-0x80(%RAX)    [1]

0x43083c VBROADCASTSD	(%R13),%ZMM2    [2]

0x430843 VMOVUPD	%ZMM2,-0x40(%RAX)    [1]

0x43084a CMP	%RDI,%RAX

0x43084d JNE	4307d4

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 114 - 114

--------------------------------------------------------------------------------

114:         yvel0(j,k)=state_yvel(1)

Coverage (%)	Name	Source Location	Module
►96.23+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.77+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:85	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P6, P7, P8, P9, P14, P15,
Function	__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0
Source	generate_chunk_kernel.f90:114-114
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	4.00
Front-end cycles	2.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	18.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	144.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	50.00
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	56.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P6, P7, P8, P9, P14, P15,
Function	__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0
Source	generate_chunk_kernel.f90:114-114
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	4.00
Front-end cycles	2.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	18.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	144.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	50.00
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	56.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0
Source file and lines	generate_chunk_kernel.f90:114-114
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 56% of vector register length is used (average across all SSE/AVX instructions).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Vector unaligned load/store instructions

Detected 8 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 512 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	19
nb uops	18
loop length	123
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	8
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	50%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	56%
load	12%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

6% of peak load performance is reached (16.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
100% of peak store performance is reached (128.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4307d4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
VBROADCASTSD (%R13),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
ADD $0x200,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM9,-0x200(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM10,-0x1c0(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM11,-0x180(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM12,-0x140(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM13,-0x100(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM14,-0xc0(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM15,-0x80(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM2,-0x40(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
CMP %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 4307d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1354>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0
Source file and lines	generate_chunk_kernel.f90:114-114
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 56% of vector register length is used (average across all SSE/AVX instructions).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Vector unaligned load/store instructions

Detected 8 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:114

Workaround

Use vector aligned instructions:

The GNU Fortran compiler does not support allocation alignment and does not feature directives to benefit from aligned data.
Use another compiler or locally use C code (for instance via libraries)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 512 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: !GCC$ unroll N

General properties

nb instructions	19
nb uops	18
loop length	123
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	8
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	50%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	56%
load	12%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

6% of peak load performance is reached (16.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
100% of peak store performance is reached (128.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4307d4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
VBROADCASTSD (%R13),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
ADD $0x200,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %ZMM9,-0x200(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM10,-0x1c0(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM11,-0x180(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM12,-0x140(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM13,-0x100(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM14,-0xc0(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM15,-0x80(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD (%R13),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVUPD %ZMM2,-0x40(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	1	vect (100.0%)
CMP %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 4307d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1354>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

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Vector unaligned load/store instructions

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Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code