OV - exec - Function __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp

	Function: __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0	Module: exec	Source: ideal_gas_kernel.f90:45-55	Coverage (incl. loops): 5.45% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90: 45 - 55

--------------------------------------------------------------------------------

45:     !$OMP PARALLEL

46:     !$OMP DO PRIVATE(v,pressurebyenergy,pressurebyvolume,sound_speed_squared)

47:     DO k=y_min,y_max

48:     !$OMP SIMD

49:       DO j=x_min,x_max

50:         v=1.0_8/density(j,k)

51:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

52:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

53:         pressurebyvolume=-density(j,k)*pressure(j,k)

54:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

55:         soundspeed(j,k)=SQRT(sound_speed_squared)

0x4331d0 PUSH	%RBP

0x4331d1 MOV	%RSP,%RBP

0x4331d4 PUSH	%R15

0x4331d6 PUSH	%R14

0x4331d8 PUSH	%R13

0x4331da PUSH	%R12

0x4331dc PUSH	%RBX

0x4331dd MOV	%RDI,%RBX

0x4331e0 AND	$-0x40,%RSP

0x4331e4 SUB	$0x40,%RSP

0x4331e8 MOV	0x10(%RDI),%RAX

0x4331ec MOV	(%RAX),%R14D

0x4331ef CALL	402380 <@plt_start@+0x360>

0x4331f4 MOV	%EAX,%R13D

0x4331f7 CALL	4022f0 <@plt_start@+0x2d0>

0x4331fc MOV	0x18(%RBX),%RDX

0x433200 MOV	%EAX,%ECX

0x433202 MOV	(%RDX),%EAX

0x433204 INC	%EAX

0x433206 SUB	%R14D,%EAX

0x433209 CLTD

0x43320a IDIV	%R13D

0x43320d CMP	%EDX,%ECX

0x43320f JL	43389f

0x433215 IMUL	%EAX,%ECX

0x433218 ADD	%ECX,%EDX

0x43321a ADD	%EDX,%EAX

0x43321c CMP	%EAX,%EDX

0x43321e JGE	433872

0x433224 MOV	(%RBX),%RSI

0x433227 VMOVQ	0x40(%RBX),%XMM12

0x43322c MOV	0x8(%RBX),%RDI

0x433230 VMOVQ	0x50(%RBX),%XMM13

0x433235 ADD	%R14D,%EDX

0x433238 VMOVQ	0x60(%RBX),%XMM11

0x43323d VMOVQ	0x70(%RBX),%XMM14

0x433242 ADD	%R14D,%EAX

0x433245 MOVSXD	%EDX,%R13

0x433248 MOV	%EAX,0x2c(%RSP)

0x43324c VMOVQ	0x28(%RBX),%XMM5

0x433251 VMOVQ	0x30(%RBX),%XMM6

0x433256 VMOVQ	0x38(%RBX),%XMM7

0x43325b MOV	0x20(%RBX),%R15

0x43325f MOV	(%RSI),%R10D

0x433262 MOV	(%RDI),%R14D

0x433265 VMOVQ	%XMM12,%R9

0x43326a VMOVQ	%XMM13,%R11

0x43326f IMUL	%R13,%R9

0x433273 VMOVQ	%XMM11,%RAX

0x433278 IMUL	%R13,%R11

0x43327c IMUL	%R13,%RAX

0x433280 MOVSXD	%R10D,%R8

0x433283 LEA	0x1(%R14),%ECX

0x433287 MOV	%R10D,0x1c(%RSP)

0x43328c MOV	%R14D,0x28(%RSP)

0x433291 MOV	%R8,%RSI

0x433294 ADD	0x48(%RBX),%RSI

0x433298 MOV	%R8,%RDI

0x43329b ADD	0x58(%RBX),%RDI

0x43329f VMOVQ	%R8,%XMM4

0x4332a4 ADD	0x68(%RBX),%R8

0x4332a8 ADD	%R9,%RSI

0x4332ab VMOVQ	%XMM4,%R9

0x4332b0 ADD	0x78(%RBX),%R9

0x4332b4 ADD	%R11,%RDI

0x4332b7 VMOVQ	%XMM14,%R11

0x4332bc ADD	%RAX,%R8

0x4332bf IMUL	%R11,%R13

0x4332c3 ADD	%R13,%R9

0x4332c6 MOV	%R14D,%R13D

0x4332c9 SUB	%R10D,%R13D

0x4332cc CMP	%R14D,%R10D

0x4332cf LEA	0x1(%R13),%R11D

0x4332d3 CMOVLE	%ECX,%R10D

0x4332d7 MOV	%R13D,0x38(%RSP)

0x4332dc MOV	%R10D,%EAX

0x4332df MOV	%R11D,0x18(%RSP)

0x4332e4 JG	4338a8

0x4332ea MOV	%R11D,%R12D

0x4332ed VMOVSD	0x6f62b(%RIP),%XMM10

0x4332f5 VMOVSD	0x6f7f3(%RIP),%XMM8

0x4332fd AND	$-0x8,%R11D

0x433301 SHR	$0x3,%R12D

0x433305 MOV	%R10D,0x10(%RSP)

0x43330a MOV	%R11D,0x14(%RSP)

0x43330f MOV	%RBX,0x8(%RSP)

0x433314 VBROADCASTSD	%XMM10,%YMM15

0x433319 VBROADCASTSD	%XMM8,%YMM9

0x43331e VBROADCASTSD	%XMM10,%ZMM2

0x433324 VBROADCASTSD	%XMM8,%ZMM1

0x43332a SAL	$0x6,%R12

0x43332e VMOVQ	%XMM6,%R10

0x433333 MOV	%R15,%R14

0x433336 VMOVQ	%XMM5,%R15

0x43333b MOV	%R12,0x30(%RSP)

(229) 0x433340 CMPL	$0x6,0x38(%RSP)

(229) 0x433345 JBE	433890

(229) 0x43334b MOV	0x30(%RSP),%RCX

(229) 0x433350 VMOVQ	%XMM7,%RAX

(229) 0x433355 LEA	(%R14,%RSI,8),%R11

(229) 0x433359 LEA	(%R15,%RDI,8),%R13

(229) 0x43335d LEA	(%RAX,%R9,8),%RBX

(229) 0x433361 XOR	%EAX,%EAX

(229) 0x433363 LEA	(%R10,%R8,8),%R12

(229) 0x433367 SUB	$0x40,%RCX

(229) 0x43336b SHR	$0x6,%RCX

(229) 0x43336f INC	%RCX

(229) 0x433372 AND	$0x3,%ECX

(229) 0x433375 JE	43349b

(229) 0x43337b CMP	$0x1,%RCX

(229) 0x43337f JE	433438

(229) 0x433385 CMP	$0x2,%RCX

(229) 0x433389 JE	4333e0

(229) 0x43338b VMOVUPD	(%R11),%ZMM0

(229) 0x433391 MOV	$0x40,%EAX

(229) 0x433396 VMULPD	%ZMM1,%ZMM0,%ZMM3

(229) 0x43339c VMULPD	(%R13),%ZMM3,%ZMM5

(229) 0x4333a3 VDIVPD	%ZMM0,%ZMM2,%ZMM16

(229) 0x4333a9 VMOVUPD	%ZMM5,(%R12)

(229) 0x4333b0 VMOVUPD	(%R11),%ZMM18

(229) 0x4333b6 VMULPD	%ZMM16,%ZMM16,%ZMM19

(229) 0x4333bc VMULPD	%ZMM1,%ZMM18,%ZMM17

(229) 0x4333c2 VMULPD	%ZMM5,%ZMM17,%ZMM20

(229) 0x4333c8 VFMADD132PD	%ZMM18,%ZMM20,%ZMM5

(229) 0x4333ce VMULPD	%ZMM5,%ZMM19,%ZMM6

(229) 0x4333d4 VSQRTPD	%ZMM6,%ZMM0

(229) 0x4333da VMOVUPD	%ZMM0,(%RBX)

(229) 0x4333e0 VMOVUPD	(%R11,%RAX,1),%ZMM3

(229) 0x4333e7 VMULPD	%ZMM1,%ZMM3,%ZMM5

(229) 0x4333ed VMULPD	(%R13,%RAX,1),%ZMM5,%ZMM6

(229) 0x4333f5 VDIVPD	%ZMM3,%ZMM2,%ZMM21

(229) 0x4333fb VMOVUPD	%ZMM6,(%R12,%RAX,1)

(229) 0x433402 VMOVUPD	(%R11,%RAX,1),%ZMM22

(229) 0x433409 VMULPD	%ZMM21,%ZMM21,%ZMM23

(229) 0x43340f VMULPD	%ZMM1,%ZMM22,%ZMM24

(229) 0x433415 VMULPD	%ZMM6,%ZMM24,%ZMM25

(229) 0x43341b VFMADD132PD	%ZMM22,%ZMM25,%ZMM6

(229) 0x433421 VMULPD	%ZMM6,%ZMM23,%ZMM26

(229) 0x433427 VSQRTPD	%ZMM26,%ZMM27

(229) 0x43342d VMOVUPD	%ZMM27,(%RBX,%RAX,1)

(229) 0x433434 ADD	$0x40,%RAX

(229) 0x433438 VMOVUPD	(%R11,%RAX,1),%ZMM0

(229) 0x43343f VMULPD	%ZMM1,%ZMM0,%ZMM3

(229) 0x433445 VMULPD	(%R13,%RAX,1),%ZMM3,%ZMM5

(229) 0x43344d VDIVPD	%ZMM0,%ZMM2,%ZMM28

(229) 0x433453 VMOVUPD	%ZMM5,(%R12,%RAX,1)

(229) 0x43345a VMOVUPD	(%R11,%RAX,1),%ZMM29

(229) 0x433461 VMULPD	%ZMM28,%ZMM28,%ZMM30

(229) 0x433467 VMULPD	%ZMM1,%ZMM29,%ZMM31

(229) 0x43346d VMULPD	%ZMM5,%ZMM31,%ZMM16

(229) 0x433473 VFMADD132PD	%ZMM29,%ZMM16,%ZMM5

(229) 0x433479 VMULPD	%ZMM5,%ZMM30,%ZMM18

(229) 0x43347f VSQRTPD	%ZMM18,%ZMM19

(229) 0x433485 VMOVUPD	%ZMM19,(%RBX,%RAX,1)

(229) 0x43348c ADD	$0x40,%RAX

(229) 0x433490 CMP	%RAX,0x30(%RSP)

(229) 0x433495 JE	433608

  (230) 0x43349b VMOVUPD	(%R11,%RAX,1),%ZMM6

  (230) 0x4334a2 VMULPD	%ZMM1,%ZMM6,%ZMM0

  (230) 0x4334a8 VMULPD	(%R13,%RAX,1),%ZMM0,%ZMM3

  (230) 0x4334b0 VDIVPD	%ZMM6,%ZMM2,%ZMM17

  (230) 0x4334b6 VMOVUPD	%ZMM3,(%R12,%RAX,1)

  (230) 0x4334bd VMOVUPD	(%R11,%RAX,1),%ZMM20

  (230) 0x4334c4 VMULPD	%ZMM17,%ZMM17,%ZMM21

  (230) 0x4334ca VMULPD	%ZMM1,%ZMM20,%ZMM22

  (230) 0x4334d0 VMULPD	%ZMM3,%ZMM22,%ZMM23

  (230) 0x4334d6 VFMADD132PD	%ZMM20,%ZMM23,%ZMM3

  (230) 0x4334dc VMULPD	%ZMM3,%ZMM21,%ZMM24

  (230) 0x4334e2 VSQRTPD	%ZMM24,%ZMM25

  (230) 0x4334e8 VMOVUPD	%ZMM25,(%RBX,%RAX,1)

  (230) 0x4334ef VMOVUPD	0x40(%R11,%RAX,1),%ZMM5

  (230) 0x4334f7 VMULPD	%ZMM1,%ZMM5,%ZMM6

  (230) 0x4334fd VMULPD	0x40(%R13,%RAX,1),%ZMM6,%ZMM0

  (230) 0x433505 VDIVPD	%ZMM5,%ZMM2,%ZMM26

  (230) 0x43350b VMOVUPD	%ZMM0,0x40(%R12,%RAX,1)

  (230) 0x433513 VMOVUPD	0x40(%R11,%RAX,1),%ZMM27

  (230) 0x43351b VMULPD	%ZMM26,%ZMM26,%ZMM28

  (230) 0x433521 VMULPD	%ZMM1,%ZMM27,%ZMM29

  (230) 0x433527 VMULPD	%ZMM0,%ZMM29,%ZMM30

  (230) 0x43352d VFMADD132PD	%ZMM27,%ZMM30,%ZMM0

  (230) 0x433533 VMULPD	%ZMM0,%ZMM28,%ZMM31

  (230) 0x433539 VSQRTPD	%ZMM31,%ZMM16

  (230) 0x43353f VMOVUPD	%ZMM16,0x40(%RBX,%RAX,1)

  (230) 0x433547 VMOVUPD	0x80(%R11,%RAX,1),%ZMM3

  (230) 0x43354f VMULPD	%ZMM1,%ZMM3,%ZMM5

  (230) 0x433555 VMULPD	0x80(%R13,%RAX,1),%ZMM5,%ZMM6

  (230) 0x43355d VDIVPD	%ZMM3,%ZMM2,%ZMM19

  (230) 0x433563 VMOVUPD	%ZMM6,0x80(%R12,%RAX,1)

  (230) 0x43356b VMOVUPD	0x80(%R11,%RAX,1),%ZMM18

  (230) 0x433573 VMULPD	%ZMM19,%ZMM19,%ZMM20

  (230) 0x433579 VMULPD	%ZMM1,%ZMM18,%ZMM17

  (230) 0x43357f VMULPD	%ZMM6,%ZMM17,%ZMM21

  (230) 0x433585 VFMADD132PD	%ZMM18,%ZMM21,%ZMM6

  (230) 0x43358b VMULPD	%ZMM6,%ZMM20,%ZMM22

  (230) 0x433591 VSQRTPD	%ZMM22,%ZMM23

  (230) 0x433597 VMOVUPD	%ZMM23,0x80(%RBX,%RAX,1)

  (230) 0x43359f VMOVUPD	0xc0(%R11,%RAX,1),%ZMM0

  (230) 0x4335a7 VMULPD	%ZMM1,%ZMM0,%ZMM3

  (230) 0x4335ad VMULPD	0xc0(%R13,%RAX,1),%ZMM3,%ZMM5

  (230) 0x4335b5 VDIVPD	%ZMM0,%ZMM2,%ZMM24

  (230) 0x4335bb VMOVUPD	%ZMM5,0xc0(%R12,%RAX,1)

  (230) 0x4335c3 VMOVUPD	0xc0(%R11,%RAX,1),%ZMM25

  (230) 0x4335cb VMULPD	%ZMM24,%ZMM24,%ZMM26

  (230) 0x4335d1 VMULPD	%ZMM1,%ZMM25,%ZMM27

  (230) 0x4335d7 VMULPD	%ZMM5,%ZMM27,%ZMM28

  (230) 0x4335dd VFMADD132PD	%ZMM25,%ZMM28,%ZMM5

  (230) 0x4335e3 VMULPD	%ZMM5,%ZMM26,%ZMM29

  (230) 0x4335e9 VSQRTPD	%ZMM29,%ZMM30

  (230) 0x4335ef VMOVUPD	%ZMM30,0xc0(%RBX,%RAX,1)

  (230) 0x4335f7 ADD	$0x100,%RAX

  (230) 0x4335fd CMP	%RAX,0x30(%RSP)

  (230) 0x433602 JNE	43349b

(229) 0x433608 MOV	0x14(%RSP),%R11D

(229) 0x43360d MOV	0x1c(%RSP),%R13D

(229) 0x433612 MOV	%R11D,%ECX

(229) 0x433615 ADD	%R13D,%R11D

(229) 0x433618 MOV	%R11D,0x3c(%RSP)

(229) 0x43361d TESTB	$0x7,0x18(%RSP)

(229) 0x433622 JE	433830

(229) 0x433628 MOV	0x38(%RSP),%R12D

(229) 0x43362d SUB	%ECX,%R12D

(229) 0x433630 LEA	0x1(%R12),%EBX

(229) 0x433635 CMP	$0x2,%R12D

(229) 0x433639 JBE	4336b2

(229) 0x43363b LEA	(%RCX,%RSI,1),%RAX

(229) 0x43363f LEA	(%RCX,%RDI,1),%R13

(229) 0x433643 LEA	(%RCX,%R9,1),%R12

(229) 0x433647 ADD	%R8,%RCX

(229) 0x43364a LEA	(%R14,%RAX,8),%R11

(229) 0x43364e MOV	%EBX,%EAX

(229) 0x433650 VMOVUPD	(%R11),%YMM6

(229) 0x433655 AND	$-0x4,%EAX

(229) 0x433658 ADD	%EAX,0x3c(%RSP)

(229) 0x43365c AND	$0x3,%EBX

(229) 0x43365f VMULPD	%YMM9,%YMM6,%YMM0

(229) 0x433664 VMULPD	(%R15,%R13,8),%YMM0,%YMM3

(229) 0x43366a VDIVPD	%YMM6,%YMM15,%YMM31

(229) 0x433670 VMOVUPD	%YMM3,(%R10,%RCX,8)

(229) 0x433676 VMOVUPD	(%R11),%YMM19

(229) 0x43367c VMOVQ	%XMM7,%RCX

(229) 0x433681 VMULPD	%YMM31,%YMM31,%YMM16

(229) 0x433687 VMULPD	%YMM9,%YMM19,%YMM18

(229) 0x43368d VMULPD	%YMM3,%YMM18,%YMM20

(229) 0x433693 VFMADD132PD	%YMM19,%YMM20,%YMM3

(229) 0x433699 VMULPD	%YMM3,%YMM16,%YMM17

(229) 0x43369f VSQRTPD	%YMM17,%YMM21

(229) 0x4336a5 VMOVUPD	%YMM21,(%RCX,%R12,8)

(229) 0x4336ac JE	433830

(229) 0x4336b2 VMOVQ	%XMM4,%RBX

(229) 0x4336b7 MOV	%RSI,%R11

(229) 0x4336ba MOV	%RDI,%R13

(229) 0x4336bd MOV	%R8,%R12

(229) 0x4336c0 SUB	%RBX,%R11

(229) 0x4336c3 SUB	%RBX,%R13

(229) 0x4336c6 SUB	%RBX,%R12

(229) 0x4336c9 VMOVQ	%XMM4,%RCX

(229) 0x4336ce MOV	%R9,%RBX

(229) 0x4336d1 MOV	%R11,0x20(%RSP)

(229) 0x4336d6 SUB	%RCX,%RBX

(229) 0x4336d9 MOVSXD	0x3c(%RSP),%RCX

(229) 0x4336de ADD	%RCX,%R11

(229) 0x4336e1 LEA	(%RCX,%R13,1),%RAX

(229) 0x4336e5 VMOVSD	(%R14,%R11,8),%XMM5

(229) 0x4336eb VMULSD	%XMM8,%XMM5,%XMM6

(229) 0x4336f0 VMULSD	(%R15,%RAX,8),%XMM6,%XMM0

(229) 0x4336f6 LEA	(%RCX,%R12,1),%RAX

(229) 0x4336fa VMOVSD	%XMM0,(%R10,%RAX,8)

(229) 0x433700 VMOVSD	(%R14,%R11,8),%XMM23

(229) 0x433707 VMULSD	%XMM8,%XMM23,%XMM25

(229) 0x43370d VMULSD	%XMM0,%XMM25,%XMM26

(229) 0x433713 VFMADD132SD	%XMM23,%XMM26,%XMM0

(229) 0x433719 ADD	%RBX,%RCX

(229) 0x43371c VMOVQ	%XMM7,%R11

(229) 0x433721 VDIVSD	%XMM5,%XMM10,%XMM22

(229) 0x433727 VMULSD	%XMM22,%XMM22,%XMM24

(229) 0x43372d VMULSD	%XMM24,%XMM0,%XMM3

(229) 0x433733 VSQRTSD	%XMM3,%XMM3,%XMM3

(229) 0x433737 VMOVSD	%XMM3,(%R11,%RCX,8)

(229) 0x43373d MOV	0x3c(%RSP),%ECX

(229) 0x433741 LEA	0x1(%RCX),%EAX

(229) 0x433744 CMP	%EAX,0x28(%RSP)

(229) 0x433748 JL	433830

(229) 0x43374e MOV	0x20(%RSP),%R11

(229) 0x433753 MOVSXD	%EAX,%RCX

(229) 0x433756 LEA	(%R11,%RCX,1),%RAX

(229) 0x43375a VMOVSD	(%R14,%RAX,8),%XMM27

(229) 0x433761 VMOVQ	%RAX,%XMM5

(229) 0x433766 LEA	(%R13,%RCX,1),%RAX

(229) 0x43376b VMULSD	%XMM8,%XMM27,%XMM29

(229) 0x433771 VMULSD	(%R15,%RAX,8),%XMM29,%XMM30

(229) 0x433778 LEA	(%R12,%RCX,1),%RAX

(229) 0x43377c ADD	%RBX,%RCX

(229) 0x43377f VDIVSD	%XMM27,%XMM10,%XMM28

(229) 0x433785 VMOVSD	%XMM30,(%R10,%RAX,8)

(229) 0x43378c VMOVQ	%XMM5,%RAX

(229) 0x433791 VMULSD	%XMM28,%XMM28,%XMM31

(229) 0x433797 VMOVSD	(%R14,%RAX,8),%XMM6

(229) 0x43379d VMULSD	%XMM8,%XMM6,%XMM19

(229) 0x4337a3 VMULSD	%XMM30,%XMM19,%XMM16

(229) 0x4337a9 VFMADD132SD	%XMM30,%XMM16,%XMM6

(229) 0x4337af VMOVQ	%XMM7,%RAX

(229) 0x4337b4 VMULSD	%XMM31,%XMM6,%XMM0

(229) 0x4337ba VSQRTSD	%XMM0,%XMM0,%XMM0

(229) 0x4337be VMOVSD	%XMM0,(%RAX,%RCX,8)

(229) 0x4337c3 MOV	0x3c(%RSP),%EAX

(229) 0x4337c7 ADD	$0x2,%EAX

(229) 0x4337ca CMP	%EAX,0x28(%RSP)

(229) 0x4337ce JL	433830

(229) 0x4337d0 CLTQ

(229) 0x4337d2 ADD	%RAX,%R11

(229) 0x4337d5 ADD	%RAX,%R13

(229) 0x4337d8 ADD	%RAX,%R12

(229) 0x4337db ADD	%RAX,%RBX

(229) 0x4337de VMOVSD	(%R14,%R11,8),%XMM3

(229) 0x4337e4 VMULSD	%XMM8,%XMM3,%XMM5

(229) 0x4337e9 VMULSD	(%R15,%R13,8),%XMM5,%XMM6

(229) 0x4337ef VMOVSD	%XMM6,(%R10,%R12,8)

(229) 0x4337f5 VMOVSD	(%R14,%R11,8),%XMM18

(229) 0x4337fc VMULSD	%XMM8,%XMM18,%XMM17

(229) 0x433802 VMULSD	%XMM6,%XMM17,%XMM22

(229) 0x433808 VFMADD132SD	%XMM18,%XMM22,%XMM6

(229) 0x43380e VMOVQ	%XMM7,%R13

(229) 0x433813 VDIVSD	%XMM3,%XMM10,%XMM20

(229) 0x433819 VMULSD	%XMM20,%XMM20,%XMM21

(229) 0x43381f VMULSD	%XMM21,%XMM6,%XMM0

(229) 0x433825 VSQRTSD	%XMM0,%XMM0,%XMM0

(229) 0x433829 VMOVSD	%XMM0,(%R13,%RBX,8)

(229) 0x433830 VMOVQ	%XMM12,%R12

(229) 0x433835 VMOVQ	%XMM13,%RBX

(229) 0x43383a INC	%EDX

(229) 0x43383c VMOVQ	%XMM11,%RCX

(229) 0x433841 VMOVQ	%XMM14,%R11

(229) 0x433846 ADD	%R12,%RSI

(229) 0x433849 ADD	%RBX,%RDI

(229) 0x43384c ADD	%RCX,%R8

(229) 0x43384f ADD	%R11,%R9

(229) 0x433852 CMP	%EDX,0x2c(%RSP)

(229) 0x433856 JG	433340

0x43385c MOV	0x10(%RSP),%EAX

0x433860 MOV	0x8(%RSP),%RBX

0x433865 VZEROUPPER

0x433868 MOV	%EAX,%R12D

0x43386b MOV	%R12D,0x80(%RBX)

0x433872 LEA	-0x28(%RBP),%RSP

0x433876 POP	%RBX

0x433877 POP	%R12

0x433879 POP	%R13

0x43387b POP	%R14

0x43387d POP	%R15

0x43387f POP	%RBP

0x433880 RET

0x433881 NOPW	%CS:(%RAX,%RAX,1)

0x43388c NOPL	(%RAX)

(229) 0x433890 MOV	0x1c(%RSP),%EBX

(229) 0x433894 XOR	%ECX,%ECX

(229) 0x433896 MOV	%EBX,0x3c(%RSP)

(229) 0x43389a JMP	433628

0x43389f INC	%EAX

0x4338a1 XOR	%EDX,%EDX

0x4338a3 JMP	433215

0x4338a8 XOR	%R10D,%R10D

0x4338ab NOPL	(%RAX,%RAX,1)

(228) 0x4338b0 INC	%EDX

(228) 0x4338b2 CMP	%EAX,%ECX

(228) 0x4338b4 JE	4338d0

(228) 0x4338b6 CMP	%EDX,0x2c(%RSP)

(228) 0x4338ba JG	4338b0

0x4338bc TEST	%R10B,%R10B

0x4338bf JNE	43386b

0x4338c1 LEA	-0x28(%RBP),%RSP

0x4338c5 POP	%RBX

0x4338c6 POP	%R12

0x4338c8 POP	%R13

0x4338ca POP	%R14

0x4338cc POP	%R15

0x4338ce POP	%RBP

0x4338cf RET

(228) 0x4338d0 CMP	%EDX,0x2c(%RSP)

(228) 0x4338d4 JLE	433868

(228) 0x4338d6 MOV	%ECX,%R12D

(228) 0x4338d9 MOV	$0x1,%R10D

(228) 0x4338df JMP	4338b0

0x4338e1 NOPW	%CS:(%RAX,%RAX,1)

0x4338ec NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►95.66+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.00+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	ideal_gas_kernel	ideal_gas_kernel.f90:61	exec
○	ideal_gas	ideal_gas.f90:58	exec
○	timestep	timestep.f90:60	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec
►1.94+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	ideal_gas_kernel	ideal_gas_kernel.f90:61	exec
○	ideal_gas	ideal_gas.f90:58	exec
○	pdv	PdV.f90:124	exec
○	hydro	hydro.f90:56	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.63 to 3.50 cycles (4.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.63 to 1.18 cycles (13.28x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:48
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	127
nb uops	125
loop length	472
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	2
used zmm registers	2
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.63 cycles
front end	15.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.33	8.33	8.33	8.33	8.33	8.33	9.00	9.00	9.00	9.00	0.00	2.00	2.00	0.00	3.50	3.50
cycles	8.33	8.33	8.33	8.33	8.33	8.33	9.00	9.00	9.00	9.00	0.00	2.00	2.00	0.00	3.50	3.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	15.63
Dispatch	9.00
DIV/SQRT	6.00
Overall L1	15.63

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	4%

Vector efficiency ratios

INT

all	10%
load	12%
store	7%
mul	10%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	7%
mul	10%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.63 cycles. At this rate:

4% of peak load performance is reached (11.01 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.07 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.63 to 9.00 cycles (1.74x speedup).

ASM code

In the binary file, the address of the function is: 4331d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 402380 <@plt_start@+0x360>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4022f0 <@plt_start@+0x2d0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 43389f <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x6cf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433872 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x6a2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x40(%RBX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x50(%RBX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x60(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x70(%RBX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %EDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ 0x28(%RBX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x38(%RBX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RSI),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
VMOVQ %XMM11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %R13,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVSXD %R10D,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%R14),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R10D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R14D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD 0x48(%RBX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD 0x58(%RBX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %R8,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD 0x68(%RBX),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM4,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD 0x78(%RBX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R11,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %RAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R11,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %R13,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R14D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R10D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%R13),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMOVLE %ECX,%R10D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R13D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11D,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
JG 4338a8 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x6d8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSD 0x6f62b(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6f7f3(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
AND $-0x8,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x3,%R12D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOV %R10D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R11D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RBX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM8,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
SAL $0x6,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVQ %XMM6,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM5,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R12D,0x80(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 433215 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x45>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
TEST %R10B,%R10B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 43386b <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x69b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.63 to 3.50 cycles (4.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:48
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	127
nb uops	125
loop length	472
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	2
used zmm registers	2
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.63 cycles
front end	15.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.33	8.33	8.33	8.33	8.33	8.33	9.00	9.00	9.00	9.00	0.00	2.00	2.00	0.00	3.50	3.50
cycles	8.33	8.33	8.33	8.33	8.33	8.33	9.00	9.00	9.00	9.00	0.00	2.00	2.00	0.00	3.50	3.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	15.63
Dispatch	9.00
DIV/SQRT	6.00
Overall L1	15.63

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	4%

Vector efficiency ratios

INT

all	10%
load	12%
store	7%
mul	10%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	7%
mul	10%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.63 cycles. At this rate:

4% of peak load performance is reached (11.01 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.07 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4331d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 402380 <@plt_start@+0x360>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4022f0 <@plt_start@+0x2d0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 43389f <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x6cf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433872 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x6a2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x40(%RBX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x50(%RBX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x60(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x70(%RBX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %EDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ 0x28(%RBX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x38(%RBX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RSI),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
VMOVQ %XMM11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %R13,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVSXD %R10D,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%R14),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R10D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R14D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD 0x48(%RBX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD 0x58(%RBX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %R8,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD 0x68(%RBX),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM4,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD 0x78(%RBX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R11,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %RAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R11,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %R13,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R14D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R10D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%R13),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMOVLE %ECX,%R10D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R13D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11D,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
JG 4338a8 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x6d8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSD 0x6f62b(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x6f7f3(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
AND $-0x8,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x3,%R12D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOV %R10D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R11D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RBX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM8,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
SAL $0x6,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
VMOVQ %XMM6,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM5,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R12D,0x80(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 433215 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x45>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
TEST %R10B,%R10B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 43386b <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x69b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0–	5.45	2.04
▼Loop 229 - ideal_gas_kernel.f90:48-55 - exec–	0.00	0.00
○Loop 230 - ideal_gas_kernel.f90:50-55 - exec	5.45	2.04
○Loop 228 - ideal_gas_kernel.f90:45-48 - exec	0.00	0.00

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