OV - exec - Function __field_summary_kernel_module_MOD_field_summary_kernel._omp

	Function: __field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0	Module: exec	Source: field_summary_kernel.f90:54-71	Coverage (incl. loops): 0.30% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 54 - 71

--------------------------------------------------------------------------------

54:     !$OMP PARALLEL

55:     !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke)

56:     DO k=y_min,y_max

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

0x42bdd0 PUSH	%RBP

0x42bdd1 MOV	%RSP,%RBP

0x42bdd4 PUSH	%R15

0x42bdd6 PUSH	%R14

0x42bdd8 PUSH	%R13

0x42bdda PUSH	%R12

0x42bddc PUSH	%RBX

0x42bddd MOV	%RDI,%RBX

0x42bde0 AND	$-0x40,%RSP

0x42bde4 SUB	$0x140,%RSP

0x42bdeb MOV	0x10(%RDI),%RAX

0x42bdef MOV	(%RAX),%R14D

0x42bdf2 CALL	402380 <@plt_start@+0x360>

0x42bdf7 MOV	%EAX,%R12D

0x42bdfa CALL	4022f0 <@plt_start@+0x2d0>

0x42bdff MOV	0x18(%RBX),%RDX

0x42be03 MOV	%EAX,%ECX

0x42be05 MOV	(%RDX),%EAX

0x42be07 INC	%EAX

0x42be09 SUB	%R14D,%EAX

0x42be0c CLTD

0x42be0d IDIV	%R12D

0x42be10 CMP	%EDX,%ECX

0x42be12 JL	42ccab

0x42be18 IMUL	%EAX,%ECX

0x42be1b ADD	%ECX,%EDX

0x42be1d ADD	%EDX,%EAX

0x42be1f CMP	%EAX,%EDX

0x42be21 JGE	42cbd0

0x42be27 VMOVQ	0xa8(%RBX),%XMM19

0x42be2e MOV	(%RBX),%RSI

0x42be31 MOV	0x8(%RBX),%RDI

0x42be35 LEA	(%R14,%RDX,1),%R8D

0x42be39 ADD	%R14D,%EAX

0x42be3c VMOVQ	0x78(%RBX),%XMM24

0x42be43 VMOVQ	0x20(%RBX),%XMM11

0x42be48 MOV	%R8D,0xf8(%RSP)

0x42be50 VMOVQ	0x88(%RBX),%XMM25

0x42be57 MOVSXD	%R8D,%R8

0x42be5a MOV	%EAX,0x80(%RSP)

0x42be61 VMOVQ	0x28(%RBX),%XMM8

0x42be66 VMOVQ	0x30(%RBX),%XMM4

0x42be6b VMOVQ	0x98(%RBX),%XMM10

0x42be73 MOV	%R8,0x138(%RSP)

0x42be7b VXORPD	%XMM2,%XMM2,%XMM2

0x42be7f VMOVQ	0x38(%RBX),%XMM13

0x42be84 VMOVQ	0x40(%RBX),%XMM1

0x42be89 VMOVAPD	%XMM2,%XMM3

0x42be8d VMOVAPD	%XMM2,%XMM5

0x42be91 MOV	(%RSI),%R9D

0x42be94 MOV	(%RDI),%R11D

0x42be97 MOV	0x48(%RBX),%RDI

0x42be9b VMOVAPD	%XMM2,%XMM6

0x42be9f VMOVQ	%XMM19,%R14

0x42bea5 VMOVQ	%XMM19,%R10

0x42beab VMOVAPD	%XMM2,%XMM7

0x42beaf VMOVAPD	%XMM2,%XMM21

0x42beb5 SAL	$0x3,%R14

0x42beb9 VXORPD	%XMM23,%XMM23,%XMM23

0x42bebf VMOVQ	%XMM24,%RAX

0x42bec5 VMOVQ	%XMM11,%RCX

0x42beca VMOVQ	%R14,%XMM29

0x42bed0 MOV	0xb0(%RBX),%R14

0x42bed7 IMUL	%R8,%R10

0x42bedb VMOVQ	%XMM24,%RDX

0x42bee1 LEA	0x1(%R11),%R15D

0x42bee5 MOV	%R11D,0xfc(%RSP)

0x42beed MOVSXD	%R9D,%R11

0x42bef0 MOV	%R9D,0x130(%RSP)

0x42bef8 SAL	$0x3,%RAX

0x42befc MOV	%R15D,0x84(%RSP)

0x42bf04 VMOVDQA64	%XMM13,%XMM31

0x42bf0a MOV	0x80(%RBX),%R15

0x42bf11 MOV	%RAX,0x70(%RSP)

0x42bf16 VMOVQ	%XMM25,%RAX

0x42bf1c LEA	(%R14,%R11,1),%R12

0x42bf20 ADD	%R10,%R12

0x42bf23 LEA	(%R14,%R10,1),%R10

0x42bf27 LEA	(%RCX,%R12,8),%RSI

0x42bf2b MOV	%R12,0x98(%RSP)

0x42bf33 MOV	%R8,%R12

0x42bf36 VMOVQ	%XMM8,%RCX

0x42bf3b IMUL	%RDX,%R12

0x42bf3f VMOVQ	%XMM25,%RDX

0x42bf45 SAL	$0x3,%RAX

0x42bf49 LEA	(%R15,%R11,1),%R9

0x42bf4d MOV	%RAX,0x78(%RSP)

0x42bf52 MOV	0x90(%RBX),%RAX

0x42bf59 LEA	(%R15,%R12,1),%R14

0x42bf5d ADD	%R12,%R9

0x42bf60 MOV	%R9,0xa8(%RSP)

0x42bf68 LEA	(%RCX,%R9,8),%RCX

0x42bf6c MOV	%R8,%R9

0x42bf6f IMUL	%RDX,%R9

0x42bf73 VMOVQ	%XMM4,%RDX

0x42bf78 ADD	%R11,%RAX

0x42bf7b ADD	%R9,%RAX

0x42bf7e MOV	%RAX,0xa0(%RSP)

0x42bf86 LEA	(%RDX,%RAX,8),%RAX

0x42bf8a VMOVQ	%XMM10,%RDX

0x42bf8f MOV	%RAX,0xd8(%RSP)

0x42bf97 VMOVQ	%XMM10,%RAX

0x42bf9c IMUL	%RAX,%R8

0x42bfa0 MOV	0xa0(%RBX),%RAX

0x42bfa7 SAL	$0x3,%RDX

0x42bfab MOV	%RDX,0x68(%RSP)

0x42bfb0 VMOVQ	%XMM13,%RDX

0x42bfb5 VMOVDQA64	%XMM29,%XMM13

0x42bfbb ADD	%R11,%RAX

0x42bfbe VMOVDQA64	%XMM25,%XMM29

0x42bfc4 VMOVDQA64	%XMM19,%XMM25

0x42bfca ADD	%R8,%RAX

0x42bfcd MOV	%RAX,0x90(%RSP)

0x42bfd5 MOV	%R10,0x88(%RSP)

0x42bfdd VMOVQ	0xb8(%RBX),%XMM27

0x42bfe4 MOV	0xa0(%RBX),%R12

0x42bfeb VMOVQ	0xc8(%RBX),%XMM28

0x42bff2 MOV	%R14,0x108(%RSP)

0x42bffa MOV	0xc0(%RBX),%R14

0x42c001 ADD	0x90(%RBX),%R9

0x42c008 LEA	(%RDX,%RAX,8),%RAX

0x42c00c VMOVSD	0x76902(%RIP),%XMM17

0x42c016 VMOVSD	0x76908(%RIP),%XMM20

0x42c020 MOVQ	$0,0x120(%RSP)

0x42c02c MOVQ	$0,0x118(%RSP)

0x42c038 VBROADCASTSD	%XMM17,%YMM18

0x42c03e VBROADCASTSD	%XMM20,%YMM22

0x42c044 ADD	%R8,%R12

0x42c047 VMOVQ	%XMM27,%R8

0x42c04d VMOVQ	%XMM27,%R15

0x42c053 MOV	%R12,0x100(%RSP)

0x42c05b LEA	(%R14,%R11,1),%R12

0x42c05f SAL	$0x3,%R8

0x42c063 MOV	%R9,0x110(%RSP)

0x42c06b VMOVDQA64	%XMM28,%XMM19

0x42c071 VMOVQ	%R8,%XMM9

0x42c076 MOV	0x138(%RSP),%R8

0x42c07e MOV	%R8,%R10

0x42c081 IMUL	%R15,%R10

0x42c085 VMOVQ	%XMM28,%R15

0x42c08b SAL	$0x3,%R15

0x42c08f LEA	(%R12,%R10,1),%R9

0x42c093 VMOVQ	%R15,%XMM26

0x42c099 MOV	0xd0(%RBX),%R15

0x42c0a0 LEA	(%R14,%R10,1),%R10

0x42c0a4 LEA	(,%R9,8),%RDX

0x42c0ac MOV	%R9,0x50(%RSP)

0x42c0b1 MOV	%R8,%R9

0x42c0b4 INC	%R8

0x42c0b7 MOV	%RDX,0xd0(%RSP)

0x42c0bf VMOVQ	%XMM28,%RDX

0x42c0c5 MOV	%R8,0x138(%RSP)

0x42c0cd MOV	%R10,0x30(%RSP)

0x42c0d2 IMUL	%RDX,%R9

0x42c0d6 MOV	%RDI,%R10

0x42c0d9 ADD	%R15,%R11

0x42c0dc LEA	(%R11,%R9,1),%RDX

0x42c0e0 LEA	(%R9,%R15,1),%R9

0x42c0e4 MOV	%RDX,0x48(%RSP)

0x42c0e9 SAL	$0x3,%RDX

0x42c0ed MOV	%R9,0x28(%RSP)

0x42c0f2 MOV	%RDX,0xc8(%RSP)

0x42c0fa VMOVQ	%XMM27,%RDX

0x42c100 MOV	0xfc(%RSP),%R9D

0x42c108 IMUL	%R8,%RDX

0x42c10c LEA	(%RDX,%R12,1),%R12

0x42c110 MOV	%RDX,%R8

0x42c113 VMOVQ	%XMM28,%RDX

0x42c119 VMOVDQA64	%XMM24,%XMM28

0x42c11f MOV	%R12,0x40(%RSP)

0x42c124 SAL	$0x3,%R12

0x42c128 VMOVDQA64	%XMM10,%XMM24

0x42c12e LEA	(%R14,%R8,1),%R14

0x42c132 MOV	%R12,0xc0(%RSP)

0x42c13a MOV	0x130(%RSP),%R8D

0x42c142 MOV	0x138(%RSP),%R12

0x42c14a MOV	%R14,0x20(%RSP)

0x42c14f IMUL	%RDX,%R12

0x42c153 SUB	%R8D,%R9D

0x42c156 XOR	%R8D,%R8D

0x42c159 MOV	%R9D,0xb0(%RSP)

0x42c161 INC	%R9D

0x42c164 MOV	%R9D,0x5c(%RSP)

0x42c169 SHR	$0x3,%R9D

0x42c16d LEA	(%R12,%R11,1),%R11

0x42c171 LEA	(%R15,%R12,1),%R15

0x42c175 VMOVQ	%XMM1,%R12

0x42c17a MOV	%R11,0x38(%RSP)

0x42c17f SAL	$0x3,%R11

0x42c183 MOV	%R15,0x18(%RSP)

0x42c188 SAL	$0x6,%R9

0x42c18c MOV	%R11,0xb8(%RSP)

0x42c194 MOV	%R9,0x138(%RSP)

0x42c19c VMOVQ	%XMM27,0x60(%RSP)

0x42c1a4 VMOVQ	%XMM11,0xf0(%RSP)

0x42c1ad MOV	%RAX,0x128(%RSP)

0x42c1b5 VMOVQ	%XMM8,0xe8(%RSP)

0x42c1be VMOVQ	%XMM4,0xe0(%RSP)

0x42c1c7 MOV	%RBX,0x10(%RSP)

0x42c1cc VMOVDQA64	%XMM9,%XMM27

0x42c1d2 NOPW	%CS:(%RAX,%RAX,1)

0x42c1dd NOPL	(%RAX)

(173) 0x42c1e0 MOV	0xfc(%RSP),%EBX

(173) 0x42c1e7 INCL	0xf8(%RSP)

(173) 0x42c1ee CMP	%EBX,0x130(%RSP)

(173) 0x42c1f5 JG	42cba1

(173) 0x42c1fb CMPL	$0x6,0xb0(%RSP)

(173) 0x42c203 JBE	42cc9c

(173) 0x42c209 MOV	0xd0(%RSP),%R13

(173) 0x42c211 MOV	0xc8(%RSP),%RDX

(173) 0x42c219 MOV	0xb8(%RSP),%R8

(173) 0x42c221 MOV	0xc0(%RSP),%RDI

(173) 0x42c229 VBROADCASTSD	0x766e5(%RIP),%ZMM12

(173) 0x42c233 VBROADCASTSD	0x766eb(%RIP),%ZMM16

(173) 0x42c23d VMOVQ	%R10,%XMM14

(173) 0x42c242 MOV	0xd8(%RSP),%RAX

(173) 0x42c24a VXORPD	%XMM15,%XMM15,%XMM15

(173) 0x42c24f LEA	(%RDX,%R10,1),%R15

(173) 0x42c253 LEA	(%R8,%R10,1),%R11

(173) 0x42c257 LEA	(%R13,%R12,1),%R9

(173) 0x42c25c LEA	0x8(%R12,%R13,1),%R14

(173) 0x42c261 LEA	0x8(%R10,%RDX,1),%R13

(173) 0x42c266 LEA	0x8(%R10,%R8,1),%RDX

(173) 0x42c26b MOV	%RSI,%R10

(173) 0x42c26e MOV	%RCX,%RSI

(173) 0x42c271 MOV	0x128(%RSP),%RCX

(173) 0x42c279 LEA	(%RDI,%R12,1),%RBX

(173) 0x42c27d XOR	%R8D,%R8D

(173) 0x42c280 LEA	0x8(%R12,%RDI,1),%RDI

(173) 0x42c285 NOPW	%CS:(%RAX,%RAX,1)

  (174) 0x42c290 VMOVUPD	(%R15,%R8,1),%ZMM1

  (174) 0x42c297 VMOVUPD	(%R9,%R8,1),%ZMM0

  (174) 0x42c29e VMOVUPD	(%R13,%R8,1),%ZMM4

  (174) 0x42c2a6 VMOVUPD	(%R14,%R8,1),%ZMM8

  (174) 0x42c2ad VMOVUPD	(%R11,%R8,1),%ZMM9

  (174) 0x42c2b4 VMULPD	%ZMM1,%ZMM1,%ZMM11

  (174) 0x42c2ba VMULPD	%ZMM4,%ZMM4,%ZMM10

  (174) 0x42c2c0 VMULPD	%ZMM9,%ZMM9,%ZMM1

  (174) 0x42c2c6 VMOVUPD	(%RDI,%R8,1),%ZMM9

  (174) 0x42c2cd VFMADD132PD	%ZMM0,%ZMM11,%ZMM0

  (174) 0x42c2d3 VFMADD132PD	%ZMM8,%ZMM10,%ZMM8

  (174) 0x42c2d9 VMOVUPD	(%RDX,%R8,1),%ZMM11

  (174) 0x42c2e0 VFMADD132PD	%ZMM12,%ZMM15,%ZMM0

  (174) 0x42c2e6 VFMADD132PD	%ZMM12,%ZMM0,%ZMM8

  (174) 0x42c2ec VMOVUPD	(%RBX,%R8,1),%ZMM0

  (174) 0x42c2f3 VFMADD132PD	%ZMM0,%ZMM1,%ZMM0

  (174) 0x42c2f9 VMOVUPD	(%R10,%R8,1),%ZMM1

  (174) 0x42c300 VFMADD132PD	%ZMM12,%ZMM8,%ZMM0

  (174) 0x42c306 VMULPD	%ZMM11,%ZMM11,%ZMM8

  (174) 0x42c30c VEXTRACTF64X2	$0x1,%YMM1,%XMM10

  (174) 0x42c313 VADDSD	%XMM7,%XMM1,%XMM7

  (174) 0x42c317 VFMADD132PD	%ZMM9,%ZMM8,%ZMM9

  (174) 0x42c31d VUNPCKHPD	%XMM1,%XMM1,%XMM8

  (174) 0x42c321 VADDSD	%XMM8,%XMM7,%XMM4

  (174) 0x42c326 VEXTRACTF64X4	$0x1,%ZMM1,%YMM8

  (174) 0x42c32d VALIGNQ	$0x3,%YMM1,%YMM1,%YMM11

  (174) 0x42c334 VADDSD	%XMM10,%XMM4,%XMM7

  (174) 0x42c339 VFMADD132PD	%ZMM12,%ZMM0,%ZMM9

  (174) 0x42c33f VMULPD	(%RSI,%R8,1),%ZMM1,%ZMM0

  (174) 0x42c346 VADDSD	%XMM11,%XMM7,%XMM7

  (174) 0x42c34b VADDSD	%XMM8,%XMM7,%XMM11

  (174) 0x42c350 VUNPCKHPD	%XMM8,%XMM8,%XMM7

  (174) 0x42c355 VEXTRACTF64X2	$0x1,%YMM8,%XMM10

  (174) 0x42c35c VADDSD	%XMM7,%XMM11,%XMM4

  (174) 0x42c360 VALIGNQ	$0x3,%YMM8,%YMM8,%YMM8

  (174) 0x42c367 VADDSD	%XMM10,%XMM4,%XMM11

  (174) 0x42c36c VADDSD	%XMM0,%XMM6,%XMM6

  (174) 0x42c370 VEXTRACTF64X2	$0x1,%YMM0,%XMM10

  (174) 0x42c377 VADDSD	%XMM8,%XMM11,%XMM7

  (174) 0x42c37c VUNPCKHPD	%XMM0,%XMM0,%XMM8

  (174) 0x42c380 VADDSD	%XMM8,%XMM6,%XMM4

  (174) 0x42c385 VEXTRACTF64X4	$0x1,%ZMM0,%YMM8

  (174) 0x42c38c VALIGNQ	$0x3,%YMM0,%YMM0,%YMM11

  (174) 0x42c393 VADDSD	%XMM10,%XMM4,%XMM6

  (174) 0x42c398 VEXTRACTF64X2	$0x1,%YMM8,%XMM10

  (174) 0x42c39f VADDSD	%XMM11,%XMM6,%XMM6

  (174) 0x42c3a4 VADDSD	%XMM8,%XMM6,%XMM11

  (174) 0x42c3a9 VUNPCKHPD	%XMM8,%XMM8,%XMM6

  (174) 0x42c3ae VADDSD	%XMM6,%XMM11,%XMM4

  (174) 0x42c3b2 VALIGNQ	$0x3,%YMM8,%YMM8,%YMM8

  (174) 0x42c3b9 VADDSD	%XMM10,%XMM4,%XMM11

  (174) 0x42c3be VADDSD	%XMM8,%XMM11,%XMM6

  (174) 0x42c3c3 VMULPD	(%RAX,%R8,1),%ZMM0,%ZMM8

  (174) 0x42c3ca VMULPD	%ZMM16,%ZMM0,%ZMM0

  (174) 0x42c3d0 VMULPD	(%RCX,%R8,1),%ZMM1,%ZMM1

  (174) 0x42c3d7 ADD	$0x40,%R8

  (174) 0x42c3db VEXTRACTF64X2	$0x1,%YMM8,%XMM4

  (174) 0x42c3e2 VUNPCKHPD	%XMM8,%XMM8,%XMM10

  (174) 0x42c3e7 VADDSD	%XMM8,%XMM3,%XMM3

  (174) 0x42c3ec VADDSD	%XMM10,%XMM3,%XMM3

  (174) 0x42c3f1 VADDSD	%XMM1,%XMM5,%XMM5

  (174) 0x42c3f5 VALIGNQ	$0x3,%YMM8,%YMM8,%YMM11

  (174) 0x42c3fc VADDSD	%XMM4,%XMM3,%XMM10

  (174) 0x42c400 VEXTRACTF64X4	$0x1,%ZMM8,%YMM8

  (174) 0x42c407 VADDSD	%XMM11,%XMM10,%XMM4

  (174) 0x42c40c VEXTRACTF64X2	$0x1,%YMM8,%XMM10

  (174) 0x42c413 VADDSD	%XMM8,%XMM4,%XMM11

  (174) 0x42c418 VUNPCKHPD	%XMM8,%XMM8,%XMM4

  (174) 0x42c41d VADDSD	%XMM4,%XMM11,%XMM3

  (174) 0x42c421 VALIGNQ	$0x3,%YMM8,%YMM8,%YMM8

  (174) 0x42c428 VADDSD	%XMM10,%XMM3,%XMM11

  (174) 0x42c42d VMULPD	%ZMM9,%ZMM0,%ZMM10

  (174) 0x42c433 VADDSD	%XMM10,%XMM2,%XMM2

  (174) 0x42c438 VEXTRACTF64X2	$0x1,%YMM10,%XMM4

  (174) 0x42c43f VADDSD	%XMM8,%XMM11,%XMM3

  (174) 0x42c444 VUNPCKHPD	%XMM10,%XMM10,%XMM8

  (174) 0x42c449 VADDSD	%XMM8,%XMM2,%XMM0

  (174) 0x42c44e VALIGNQ	$0x3,%YMM10,%YMM10,%YMM11

  (174) 0x42c455 VADDSD	%XMM4,%XMM0,%XMM9

  (174) 0x42c459 VEXTRACTF64X4	$0x1,%ZMM10,%YMM10

  (174) 0x42c460 VADDSD	%XMM11,%XMM9,%XMM4

  (174) 0x42c465 VUNPCKHPD	%XMM10,%XMM10,%XMM9

  (174) 0x42c46a VADDSD	%XMM10,%XMM4,%XMM0

  (174) 0x42c46f VEXTRACTF64X2	$0x1,%YMM10,%XMM4

  (174) 0x42c476 VADDSD	%XMM9,%XMM0,%XMM11

  (174) 0x42c47b VALIGNQ	$0x3,%YMM10,%YMM10,%YMM10

  (174) 0x42c482 VADDSD	%XMM4,%XMM11,%XMM2

  (174) 0x42c486 VUNPCKHPD	%XMM1,%XMM1,%XMM11

  (174) 0x42c48a VADDSD	%XMM11,%XMM5,%XMM4

  (174) 0x42c48f VALIGNQ	$0x3,%YMM1,%YMM1,%YMM9

  (174) 0x42c496 VADDSD	%XMM10,%XMM2,%XMM2

  (174) 0x42c49b VEXTRACTF64X2	$0x1,%YMM1,%XMM10

  (174) 0x42c4a2 VEXTRACTF64X4	$0x1,%ZMM1,%YMM1

  (174) 0x42c4a9 VADDSD	%XMM10,%XMM4,%XMM0

  (174) 0x42c4ae VUNPCKHPD	%XMM1,%XMM1,%XMM10

  (174) 0x42c4b2 VADDSD	%XMM9,%XMM0,%XMM8

  (174) 0x42c4b7 VEXTRACTF64X2	$0x1,%YMM1,%XMM9

  (174) 0x42c4be VADDSD	%XMM1,%XMM8,%XMM4

  (174) 0x42c4c2 VADDSD	%XMM10,%XMM4,%XMM0

  (174) 0x42c4c7 VALIGNQ	$0x3,%YMM1,%YMM1,%YMM1

  (174) 0x42c4ce VADDSD	%XMM9,%XMM0,%XMM8

  (174) 0x42c4d3 VADDSD	%XMM1,%XMM8,%XMM5

  (174) 0x42c4d7 CMP	%R8,0x138(%RSP)

  (174) 0x42c4df JNE	42c290

(173) 0x42c4e5 MOV	0x5c(%RSP),%R9D

(173) 0x42c4ea MOV	0x130(%RSP),%R15D

(173) 0x42c4f2 MOV	%RCX,0x128(%RSP)

(173) 0x42c4fa MOV	%RSI,%RCX

(173) 0x42c4fd MOV	%R10,%RSI

(173) 0x42c500 VMOVQ	%XMM14,%R10

(173) 0x42c505 MOV	%R9D,%EAX

(173) 0x42c508 AND	$-0x8,%EAX

(173) 0x42c50b AND	$0x7,%R9D

(173) 0x42c50f LEA	(%RAX,%R15,1),%R11D

(173) 0x42c513 JE	42ca9a

(173) 0x42c519 MOV	0xb0(%RSP),%R14D

(173) 0x42c521 SUB	%EAX,%R14D

(173) 0x42c524 LEA	0x1(%R14),%EDX

(173) 0x42c528 CMP	$0x2,%R14D

(173) 0x42c52c JBE	42c74c

(173) 0x42c532 MOV	0x120(%RSP),%R15

(173) 0x42c53a MOV	0x48(%RSP),%RDI

(173) 0x42c53f MOV	0x118(%RSP),%R13

(173) 0x42c547 MOV	0x50(%RSP),%RBX

(173) 0x42c54c MOV	0x40(%RSP),%R9

(173) 0x42c551 LEA	(%R15,%RDI,1),%R14

(173) 0x42c555 LEA	(%R13,%RBX,1),%R8

(173) 0x42c55a MOV	0x38(%RSP),%RBX

(173) 0x42c55f MOV	0x98(%RSP),%RDI

(173) 0x42c567 ADD	%RAX,%R14

(173) 0x42c56a ADD	%RAX,%R8

(173) 0x42c56d LEA	(%R13,%R9,1),%R13

(173) 0x42c572 MOV	0xa8(%RSP),%R9

(173) 0x42c57a ADD	%RAX,%R13

(173) 0x42c57d SAL	$0x3,%R14

(173) 0x42c581 VMOVUPD	(%R10,%R14,1),%YMM12

(173) 0x42c587 VMOVUPD	0x8(%R10,%R14,1),%YMM0

(173) 0x42c58e ADD	%RBX,%R15

(173) 0x42c591 ADD	%RAX,%RDI

(173) 0x42c594 SAL	$0x3,%R8

(173) 0x42c598 VMOVQ	%RDI,%XMM14

(173) 0x42c59d VMOVUPD	(%R12,%R8,1),%YMM4

(173) 0x42c5a3 VMOVUPD	0x8(%R12,%R8,1),%YMM10

(173) 0x42c5aa ADD	%RAX,%R15

(173) 0x42c5ad MOV	0xf0(%RSP),%R8

(173) 0x42c5b5 ADD	%RAX,%R9

(173) 0x42c5b8 MOV	0xa0(%RSP),%RDI

(173) 0x42c5c0 MOV	0x90(%RSP),%RBX

(173) 0x42c5c8 VMULPD	%YMM12,%YMM12,%YMM15

(173) 0x42c5cd VMULPD	%YMM0,%YMM0,%YMM9

(173) 0x42c5d1 SAL	$0x3,%R15

(173) 0x42c5d5 VFMADD132PD	%YMM4,%YMM15,%YMM4

(173) 0x42c5da VMOVUPD	(%R10,%R15,1),%YMM1

(173) 0x42c5e0 VFMADD132PD	%YMM10,%YMM9,%YMM10

(173) 0x42c5e5 VMOVUPD	0x8(%R10,%R15,1),%YMM12

(173) 0x42c5ec SAL	$0x3,%R13

(173) 0x42c5f0 VMOVQ	%XMM14,%R15

(173) 0x42c5f5 VMOVUPD	(%R12,%R13,1),%YMM8

(173) 0x42c5fb VMOVUPD	0x8(%R12,%R13,1),%YMM15

(173) 0x42c602 MOV	0xe8(%RSP),%R13

(173) 0x42c60a VMOVUPD	(%R8,%R15,8),%YMM14

(173) 0x42c610 ADD	%RAX,%RDI

(173) 0x42c613 ADD	%RBX,%RAX

(173) 0x42c616 VFMADD132PD	%YMM18,%YMM23,%YMM4

(173) 0x42c61c VMULPD	(%R13,%R9,8),%YMM14,%YMM11

(173) 0x42c623 MOV	0xe0(%RSP),%R9

(173) 0x42c62b VFMADD132PD	%YMM18,%YMM4,%YMM10

(173) 0x42c631 VADDSD	%XMM14,%XMM7,%XMM7

(173) 0x42c636 VUNPCKHPD	%XMM14,%XMM14,%XMM16

(173) 0x42c63c VADDSD	%XMM16,%XMM7,%XMM30

(173) 0x42c642 VMULPD	%YMM1,%YMM1,%YMM4

(173) 0x42c646 VEXTRACTF64X2	$0x1,%YMM14,%XMM9

(173) 0x42c64d VFMADD132PD	%YMM8,%YMM4,%YMM8

(173) 0x42c652 VALIGNQ	$0x3,%YMM14,%YMM14,%YMM16

(173) 0x42c659 VADDSD	%XMM11,%XMM6,%XMM6

(173) 0x42c65e VFMADD132PD	%YMM18,%YMM10,%YMM8

(173) 0x42c664 VMULPD	%YMM12,%YMM12,%YMM10

(173) 0x42c669 VFMADD132PD	%YMM15,%YMM10,%YMM15

(173) 0x42c66e VEXTRACTF64X2	$0x1,%YMM11,%XMM4

(173) 0x42c675 VFMADD132PD	%YMM18,%YMM8,%YMM15

(173) 0x42c67b VADDSD	%XMM9,%XMM30,%XMM8

(173) 0x42c681 VADDSD	%XMM16,%XMM8,%XMM7

(173) 0x42c687 VUNPCKHPD	%XMM11,%XMM11,%XMM16

(173) 0x42c68d VADDSD	%XMM16,%XMM6,%XMM30

(173) 0x42c693 VADDSD	%XMM4,%XMM30,%XMM12

(173) 0x42c699 VMULPD	(%R9,%RDI,8),%YMM11,%YMM30

(173) 0x42c6a0 VMOVQ	%XMM31,%RDI

(173) 0x42c6a6 VALIGNQ	$0x3,%YMM11,%YMM11,%YMM16

(173) 0x42c6ad VMULPD	%YMM22,%YMM11,%YMM11

(173) 0x42c6b3 VMULPD	%YMM15,%YMM11,%YMM8

(173) 0x42c6b8 VMULPD	(%RDI,%RAX,8),%YMM14,%YMM14

(173) 0x42c6bd VADDSD	%XMM16,%XMM12,%XMM6

(173) 0x42c6c3 MOV	%EDX,%EAX

(173) 0x42c6c5 AND	$-0x4,%EAX

(173) 0x42c6c8 VEXTRACTF64X2	$0x1,%YMM30,%XMM0

(173) 0x42c6cf VADDSD	%XMM30,%XMM3,%XMM3

(173) 0x42c6d5 VUNPCKHPD	%XMM30,%XMM30,%XMM16

(173) 0x42c6db VADDSD	%XMM8,%XMM2,%XMM2

(173) 0x42c6e0 VADDSD	%XMM16,%XMM3,%XMM16

(173) 0x42c6e6 VUNPCKHPD	%XMM8,%XMM8,%XMM4

(173) 0x42c6eb VADDSD	%XMM4,%XMM2,%XMM12

(173) 0x42c6ef VEXTRACTF64X2	$0x1,%YMM8,%XMM10

(173) 0x42c6f6 VADDSD	%XMM0,%XMM16,%XMM9

(173) 0x42c6fc VADDSD	%XMM14,%XMM5,%XMM5

(173) 0x42c701 VUNPCKHPD	%XMM14,%XMM14,%XMM15

(173) 0x42c706 VADDSD	%XMM15,%XMM5,%XMM1

(173) 0x42c70b VALIGNQ	$0x3,%YMM30,%YMM30,%YMM30

(173) 0x42c712 VADDSD	%XMM10,%XMM12,%XMM0

(173) 0x42c717 VEXTRACTF64X2	$0x1,%YMM14,%XMM4

(173) 0x42c71e VADDSD	%XMM30,%XMM9,%XMM3

(173) 0x42c724 VALIGNQ	$0x3,%YMM14,%YMM14,%YMM12

(173) 0x42c72b VADDSD	%XMM4,%XMM1,%XMM10

(173) 0x42c72f VALIGNQ	$0x3,%YMM8,%YMM8,%YMM9

(173) 0x42c736 VADDSD	%XMM12,%XMM10,%XMM5

(173) 0x42c73b ADD	%EAX,%R11D

(173) 0x42c73e AND	$0x3,%EDX

(173) 0x42c741 VADDSD	%XMM9,%XMM0,%XMM2

(173) 0x42c746 JE	42ca9a

(173) 0x42c74c MOV	0x118(%RSP),%RBX

(173) 0x42c754 MOV	0x120(%RSP),%R8

(173) 0x42c75c MOV	0x20(%RSP),%R13

(173) 0x42c761 MOV	0x18(%RSP),%R9

(173) 0x42c766 MOV	0x28(%RSP),%R15

(173) 0x42c76b MOV	0x30(%RSP),%RDX

(173) 0x42c770 LEA	(%RBX,%R13,1),%R14

(173) 0x42c774 LEA	(%R8,%R9,1),%R13

(173) 0x42c778 ADD	%R8,%R15

(173) 0x42c77b MOVSXD	%R11D,%R8

(173) 0x42c77e ADD	%RBX,%RDX

(173) 0x42c781 LEA	(%R8,%R13,1),%RDI

(173) 0x42c785 LEA	(%R8,%R15,1),%RBX

(173) 0x42c789 LEA	(%R8,%RDX,1),%R9

(173) 0x42c78d LEA	(%R8,%R14,1),%RAX

(173) 0x42c791 VMOVSD	(%R10,%RDI,8),%XMM16

(173) 0x42c798 LEA	0x1(%R11),%EDI

(173) 0x42c79c VMOVSD	(%R10,%RBX,8),%XMM9

(173) 0x42c7a2 VMOVSD	(%R12,%R9,8),%XMM14

(173) 0x42c7a8 MOVSXD	%EDI,%RBX

(173) 0x42c7ab VMOVSD	(%R12,%RAX,8),%XMM0

(173) 0x42c7b1 VMULSD	%XMM16,%XMM16,%XMM16

(173) 0x42c7b7 VMULSD	%XMM9,%XMM9,%XMM11

(173) 0x42c7bc LEA	(%R15,%RBX,1),%R9

(173) 0x42c7c0 VFMADD132SD	%XMM0,%XMM16,%XMM0

(173) 0x42c7c6 VFMADD132SD	%XMM14,%XMM11,%XMM14

(173) 0x42c7cb MOV	%EDI,0xb4(%RSP)

(173) 0x42c7d2 VMOVSD	(%R10,%R9,8),%XMM30

(173) 0x42c7d9 MOV	0x88(%RSP),%R9

(173) 0x42c7e1 LEA	(%R14,%RBX,1),%RDI

(173) 0x42c7e5 LEA	(%RDX,%RBX,1),%RAX

(173) 0x42c7e9 VMOVSD	(%R12,%RDI,8),%XMM15

(173) 0x42c7ef VMOVSD	(%R12,%RAX,8),%XMM8

(173) 0x42c7f5 VMULSD	%XMM30,%XMM30,%XMM30

(173) 0x42c7fb VFMADD132SD	%XMM8,%XMM30,%XMM8

(173) 0x42c801 LEA	(%R13,%RBX,1),%RAX

(173) 0x42c806 VMOVAPD	%XMM0,%XMM4

(173) 0x42c80a VFMADD132SD	%XMM17,%XMM21,%XMM14

(173) 0x42c810 LEA	(%R9,%R8,1),%RDI

(173) 0x42c814 VMULSD	%XMM17,%XMM8,%XMM1

(173) 0x42c81a VMOVQ	%RDI,%XMM0

(173) 0x42c81f MOV	0xf0(%RSP),%RDI

(173) 0x42c827 VADDSD	%XMM14,%XMM1,%XMM30

(173) 0x42c82d VFMADD132SD	%XMM17,%XMM30,%XMM4

(173) 0x42c833 VMOVSD	(%R10,%RAX,8),%XMM30

(173) 0x42c83a VMOVQ	%XMM0,%RAX

(173) 0x42c83f VMULSD	%XMM30,%XMM30,%XMM16

(173) 0x42c845 VFMADD132SD	%XMM15,%XMM16,%XMM15

(173) 0x42c84b VMOVSD	(%RDI,%RAX,8),%XMM30

(173) 0x42c852 MOV	0x108(%RSP),%RDI

(173) 0x42c85a VADDSD	%XMM30,%XMM7,%XMM7

(173) 0x42c860 VMULSD	%XMM17,%XMM15,%XMM10

(173) 0x42c866 VADDSD	%XMM4,%XMM10,%XMM12

(173) 0x42c86a LEA	(%RDI,%R8,1),%RAX

(173) 0x42c86e MOV	0xe8(%RSP),%RDI

(173) 0x42c876 VMULSD	(%RDI,%RAX,8),%XMM30,%XMM16

(173) 0x42c87d MOV	0x110(%RSP),%RAX

(173) 0x42c885 MOV	0xe0(%RSP),%RDI

(173) 0x42c88d VADDSD	%XMM16,%XMM6,%XMM6

(173) 0x42c893 LEA	(%RAX,%R8,1),%RAX

(173) 0x42c897 VFMADD231SD	(%RDI,%RAX,8),%XMM16,%XMM3

(173) 0x42c89e MOV	0x100(%RSP),%RAX

(173) 0x42c8a6 VMOVQ	%XMM31,%RDI

(173) 0x42c8ac VMULSD	%XMM20,%XMM16,%XMM16

(173) 0x42c8b2 VFMADD231SD	%XMM12,%XMM16,%XMM2

(173) 0x42c8b8 ADD	%RAX,%R8

(173) 0x42c8bb VFMADD231SD	(%RDI,%R8,8),%XMM30,%XMM5

(173) 0x42c8c2 MOV	0xb4(%RSP),%R8D

(173) 0x42c8ca CMP	%R8D,0xfc(%RSP)

(173) 0x42c8d2 JL	42ca9a

(173) 0x42c8d8 LEA	0x2(%R11),%EAX

(173) 0x42c8dc VADDSD	%XMM21,%XMM1,%XMM9

(173) 0x42c8e2 MOVSXD	%EAX,%R8

(173) 0x42c8e5 MOV	%EAX,0xb4(%RSP)

(173) 0x42c8ec LEA	(%RDX,%R8,1),%RDI

(173) 0x42c8f0 LEA	(%R15,%R8,1),%RAX

(173) 0x42c8f4 VMOVSD	(%R12,%RDI,8),%XMM14

(173) 0x42c8fa LEA	(%R14,%R8,1),%RDI

(173) 0x42c8fe VMOVSD	(%R10,%RAX,8),%XMM30

(173) 0x42c905 LEA	(%R13,%R8,1),%RAX

(173) 0x42c90a VMOVSD	(%R12,%RDI,8),%XMM4

(173) 0x42c910 MOV	0xf0(%RSP),%RDI

(173) 0x42c918 VMULSD	%XMM30,%XMM30,%XMM16

(173) 0x42c91e VMOVSD	(%R10,%RAX,8),%XMM30

(173) 0x42c925 LEA	(%R9,%RBX,1),%RAX

(173) 0x42c929 VFMADD132SD	%XMM14,%XMM16,%XMM14

(173) 0x42c92f VMULSD	%XMM30,%XMM30,%XMM16

(173) 0x42c935 VFMADD132SD	%XMM4,%XMM16,%XMM4

(173) 0x42c93b VMOVSD	(%RDI,%RAX,8),%XMM30

(173) 0x42c942 MOV	0x108(%RSP),%RAX

(173) 0x42c94a MOV	0xe8(%RSP),%RDI

(173) 0x42c952 VMULSD	%XMM17,%XMM14,%XMM11

(173) 0x42c958 VMULSD	%XMM17,%XMM4,%XMM15

(173) 0x42c95e VADDSD	%XMM11,%XMM9,%XMM8

(173) 0x42c963 VADDSD	%XMM30,%XMM7,%XMM7

(173) 0x42c969 VADDSD	%XMM8,%XMM10,%XMM1

(173) 0x42c96e VADDSD	%XMM1,%XMM15,%XMM10

(173) 0x42c972 LEA	(%RAX,%RBX,1),%RAX

(173) 0x42c976 VMULSD	(%RDI,%RAX,8),%XMM30,%XMM16

(173) 0x42c97d MOV	0x110(%RSP),%RAX

(173) 0x42c985 MOV	0xe0(%RSP),%RDI

(173) 0x42c98d VADDSD	%XMM16,%XMM6,%XMM6

(173) 0x42c993 LEA	(%RAX,%RBX,1),%RAX

(173) 0x42c997 VFMADD231SD	(%RDI,%RAX,8),%XMM16,%XMM3

(173) 0x42c99e MOV	0x100(%RSP),%RAX

(173) 0x42c9a6 VMULSD	%XMM20,%XMM16,%XMM16

(173) 0x42c9ac VFMADD231SD	%XMM10,%XMM16,%XMM2

(173) 0x42c9b2 ADD	%RAX,%RBX

(173) 0x42c9b5 VMOVQ	%XMM31,%RAX

(173) 0x42c9bb VFMADD231SD	(%RAX,%RBX,8),%XMM30,%XMM5

(173) 0x42c9c2 MOV	0xb4(%RSP),%EBX

(173) 0x42c9c9 CMP	%EBX,0xfc(%RSP)

(173) 0x42c9d0 JL	42ca9a

(173) 0x42c9d6 ADD	$0x3,%R11D

(173) 0x42c9da VADDSD	%XMM21,%XMM11,%XMM12

(173) 0x42c9e0 MOV	0xe8(%RSP),%RDI

(173) 0x42c9e8 MOV	0x110(%RSP),%RBX

(173) 0x42c9f0 MOVSXD	%R11D,%R11

(173) 0x42c9f3 LEA	(%RDX,%R11,1),%RDX

(173) 0x42c9f7 ADD	%R11,%R15

(173) 0x42c9fa ADD	%R11,%R14

(173) 0x42c9fd ADD	%R11,%R13

(173) 0x42ca00 VMOVSD	(%R12,%RDX,8),%XMM0

(173) 0x42ca06 VMOVSD	(%R10,%R15,8),%XMM30

(173) 0x42ca0d VMULSD	%XMM30,%XMM30,%XMM16

(173) 0x42ca13 VFMADD132SD	%XMM0,%XMM16,%XMM0

(173) 0x42ca19 VMOVSD	(%R12,%R14,8),%XMM14

(173) 0x42ca1f VMOVSD	(%R10,%R13,8),%XMM11

(173) 0x42ca25 VMULSD	%XMM11,%XMM11,%XMM8

(173) 0x42ca2a VFMADD132SD	%XMM14,%XMM8,%XMM14

(173) 0x42ca2f MOV	0xf0(%RSP),%R14

(173) 0x42ca37 MOV	0x108(%RSP),%R13

(173) 0x42ca3f LEA	(%R9,%R8,1),%R15

(173) 0x42ca43 MOV	0xe0(%RSP),%RDX

(173) 0x42ca4b LEA	(%RBX,%R8,1),%R11

(173) 0x42ca4f VFMADD132SD	%XMM17,%XMM12,%XMM0

(173) 0x42ca55 VMOVSD	(%R14,%R15,8),%XMM1

(173) 0x42ca5b MOV	0x100(%RSP),%R15

(173) 0x42ca63 LEA	(%R13,%R8,1),%R9

(173) 0x42ca68 VADDSD	%XMM1,%XMM7,%XMM7

(173) 0x42ca6c VADDSD	%XMM0,%XMM15,%XMM9

(173) 0x42ca70 VFMADD132SD	%XMM17,%XMM9,%XMM14

(173) 0x42ca76 VMULSD	(%RDI,%R9,8),%XMM1,%XMM4

(173) 0x42ca7c VMULSD	%XMM20,%XMM4,%XMM15

(173) 0x42ca82 VADDSD	%XMM4,%XMM6,%XMM6

(173) 0x42ca86 VFMADD231SD	(%RDX,%R11,8),%XMM4,%XMM3

(173) 0x42ca8c VFMADD231SD	%XMM15,%XMM14,%XMM2

(173) 0x42ca91 ADD	%R15,%R8

(173) 0x42ca94 VFMADD231SD	(%RAX,%R8,8),%XMM1,%XMM5

(173) 0x42ca9a MOV	0x84(%RSP),%R13D

(173) 0x42caa2 MOV	$0x1,%R8D

(173) 0x42caa8 MOV	0x70(%RSP),%R14

(173) 0x42caad MOV	0x68(%RSP),%RDI

(173) 0x42cab2 MOV	0x78(%RSP),%R9

(173) 0x42cab7 VMOVQ	%XMM25,%RBX

(173) 0x42cabd ADD	%RDI,0x128(%RSP)

(173) 0x42cac5 MOV	0x60(%RSP),%RDI

(173) 0x42caca VMOVQ	%XMM28,%R11

(173) 0x42cad0 VMOVQ	%XMM29,%RDX

(173) 0x42cad6 VMOVQ	%XMM24,%R15

(173) 0x42cadc ADD	%RBX,0x88(%RSP)

(173) 0x42cae4 ADD	%R11,0x108(%RSP)

(173) 0x42caec ADD	%RDX,0x110(%RSP)

(173) 0x42caf4 ADD	%RBX,0x98(%RSP)

(173) 0x42cafc ADD	%R11,0xa8(%RSP)

(173) 0x42cb04 ADD	%RDX,0xa0(%RSP)

(173) 0x42cb0c VMOVQ	%XMM27,%R11

(173) 0x42cb12 VMOVQ	%XMM26,%RDX

(173) 0x42cb18 VMOVQ	%XMM13,%RAX

(173) 0x42cb1d ADD	%R9,0xd8(%RSP)

(173) 0x42cb25 ADD	%R15,0x100(%RSP)

(173) 0x42cb2d ADD	%R14,%RCX

(173) 0x42cb30 VMOVQ	%XMM19,%RBX

(173) 0x42cb36 ADD	%R15,0x90(%RSP)

(173) 0x42cb3e ADD	%RDI,0x118(%RSP)

(173) 0x42cb46 ADD	%RBX,0x120(%RSP)

(173) 0x42cb4e ADD	%R11,0xd0(%RSP)

(173) 0x42cb56 ADD	%RDX,0xc8(%RSP)

(173) 0x42cb5e ADD	%R11,0xc0(%RSP)

(173) 0x42cb66 MOV	0xf8(%RSP),%R14D

(173) 0x42cb6e ADD	%RAX,%RSI

(173) 0x42cb71 ADD	%RDX,0xb8(%RSP)

(173) 0x42cb79 CMP	%R14D,0x80(%RSP)

(173) 0x42cb81 JG	42c1e0

0x42cb87 MOV	0x10(%RSP),%RBX

0x42cb8c TEST	%R8B,%R8B

0x42cb8f JE	42ccb4

0x42cb95 MOV	%R13D,0xd8(%RBX)

0x42cb9c VZEROUPPER

0x42cb9f JMP	42cbe4

(173) 0x42cba1 MOV	0x84(%RSP),%EDI

(173) 0x42cba8 CMP	%EDI,0x130(%RSP)

(173) 0x42cbaf JNE	42caa8

(173) 0x42cbb5 MOV	0x130(%RSP),%R13D

(173) 0x42cbbd MOV	$0x1,%R8D

(173) 0x42cbc3 JMP	42caa8

0x42cbc8 NOPL	(%RAX,%RAX,1)

0x42cbd0 VXORPD	%XMM2,%XMM2,%XMM2

0x42cbd4 VMOVAPD	%XMM2,%XMM3

0x42cbd8 VMOVAPD	%XMM2,%XMM5

0x42cbdc VMOVAPD	%XMM2,%XMM6

0x42cbe0 VMOVAPD	%XMM2,%XMM7

0x42cbe4 VMOVSD	%XMM2,0x118(%RSP)

0x42cbed VMOVSD	%XMM3,0x120(%RSP)

0x42cbf6 VMOVSD	%XMM5,0x128(%RSP)

0x42cbff VMOVSD	%XMM6,0x130(%RSP)

0x42cc08 VMOVSD	%XMM7,0x138(%RSP)

0x42cc11 CALL	402120 <@plt_start@+0x100>

0x42cc16 MOV	0x60(%RBX),%R13

0x42cc1a MOV	0x68(%RBX),%R12

0x42cc1e MOV	0x50(%RBX),%RCX

0x42cc22 MOV	0x58(%RBX),%RSI

0x42cc26 MOV	0x70(%RBX),%R10

0x42cc2a VMOVSD	0x138(%RSP),%XMM7

0x42cc33 VMOVSD	0x130(%RSP),%XMM3

0x42cc3c VMOVSD	0x128(%RSP),%XMM5

0x42cc45 VMOVSD	0x120(%RSP),%XMM12

0x42cc4e VMOVSD	0x118(%RSP),%XMM9

0x42cc57 VADDSD	(%RCX),%XMM7,%XMM6

0x42cc5b VMOVSD	%XMM6,(%RCX)

0x42cc5f VADDSD	(%RSI),%XMM3,%XMM2

0x42cc63 VMOVSD	%XMM2,(%RSI)

0x42cc67 VADDSD	(%R10),%XMM5,%XMM10

0x42cc6c VMOVSD	%XMM10,(%R10)

0x42cc71 VADDSD	(%R13),%XMM12,%XMM0

0x42cc77 VMOVSD	%XMM0,(%R13)

0x42cc7d VADDSD	(%R12),%XMM9,%XMM14

0x42cc83 VMOVSD	%XMM14,(%R12)

0x42cc89 LEA	-0x28(%RBP),%RSP

0x42cc8d POP	%RBX

0x42cc8e POP	%R12

0x42cc90 POP	%R13

0x42cc92 POP	%R14

0x42cc94 POP	%R15

0x42cc96 POP	%RBP

0x42cc97 JMP	402160

(173) 0x42cc9c MOV	0x130(%RSP),%R11D

(173) 0x42cca4 XOR	%EAX,%EAX

(173) 0x42cca6 JMP	42c519

0x42ccab INC	%EAX

0x42ccad XOR	%EDX,%EDX

0x42ccaf JMP	42be18

0x42ccb4 VZEROUPPER

0x42ccb7 JMP	42cbe4

0x42ccbc NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►95.70+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.39+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	field_summary_kernel	field_summary_kernel.f90:54	exec
○	field_summary	field_summary.f90:69	exec
○	hydro	hydro.f90:74	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-71.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.63 to 16.50 cycles (1.92x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 376 bytes (47 double precision FP elements). The binary function is storing 392 bytes (49 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	254
nb uops	253
loop length	1299
used x86 registers	16
used mmx registers	0
used xmm registers	27
used ymm registers	2
used zmm registers	0
nb stack references	41

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.63 cycles
front end	31.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	13.50	13.50	13.50	13.50	13.50	13.50	26.50	26.50	26.50	26.50	0.00	1.00	3.00	3.00	16.50	16.50
cycles	13.50	13.50	13.50	13.50	13.50	13.50	26.50	26.50	26.50	26.50	0.00	1.00	3.00	3.00	16.50	16.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	31.63
Dispatch	26.50
DIV/SQRT	6.00
Overall L1	31.63

Vectorization ratios

INT

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	33%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	17%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	44%

Vector efficiency ratios

INT

all	12%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

INT+FP

all	13%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.63 cycles. At this rate:

4% of peak load performance is reached (11.89 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 31.63 to 26.50 cycles (1.19x speedup).

ASM code

In the binary file, the address of the function is: 42bdd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x140,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 402380 <@plt_start@+0x360>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4022f0 <@plt_start@+0x2d0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD																				scal (6.3%)
IDIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 42ccab <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0xedb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42cbd0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0xe00>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ 0xa8(%RBX),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R14,%RDX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x78(%RBX),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x20(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R8D,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ 0x88(%RBX),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD %R8D,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ 0x28(%RBX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x98(%RBX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R8,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ 0x38(%RBX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x40(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV (%RSI),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD %XMM2,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %XMM19,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM19,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SAL $0x3,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %XMM24,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %R14,%XMM29	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV 0xb0(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVQ %XMM24,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x1(%R11),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11D,0xfc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVSXD %R9D,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9D,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R15D,0x84(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVDQA64 %XMM13,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x80(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM25,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%R14,%R11,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R10,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R14,%R10,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%R12,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %RDX,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVQ %XMM25,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R15,%R11,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x90(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R15,%R12,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R12,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%R9,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RDX,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %R11,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R9,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDX,%RAX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %RAX,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0xa0(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVDQA64 %XMM29,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %R11,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQA64 %XMM25,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA64 %XMM19,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %R8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ 0xb8(%RBX),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0xc8(%RBX),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R14,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xc0(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD 0x90(%RBX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDX,%RAX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD 0x76902(%RIP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x76908(%RIP),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVQ $0,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBROADCASTSD %XMM17,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM20,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
ADD %R8,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM27,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM27,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R14,%R11,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R9,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA64 %XMM28,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %R8,%XMM9	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV 0x138(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R15,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVQ %XMM28,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x3,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R12,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %R15,%XMM26	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV 0xd0(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R14,%R10,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (,%R9,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM28,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R8,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL %RDX,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R15,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R9,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R9,%R15,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R9,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM27,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xfc(%RSP),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDX,%R12,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM28,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVDQA64 %XMM24,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R12,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x3,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVDQA64 %XMM10,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%R14,%R8,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x130(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x138(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R14,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL %RDX,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
SUB %R8D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R9D,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9D,0x5c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SHR $0x3,%R9D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R12,%R11,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R15,%R12,1),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM1,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R11,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x3,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R15,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x6,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R11,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM27,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM11,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM8,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM4,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA64 %XMM9,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x10(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %R8B,%R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 42ccb4 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0xee4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13D,0xd8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 42cbe4 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0xe14>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD %XMM2,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM3,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM5,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM6,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM7,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 402120 <@plt_start@+0x100>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x68(%RBX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x138(%RSP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x130(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x128(%RSP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x120(%RSP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x118(%RSP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RCX),%XMM7,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM6,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD (%RSI),%XMM3,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM2,(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD (%R10),%XMM5,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM10,(%R10)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD (%R13),%XMM12,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD (%R12),%XMM9,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM14,(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 402160 <@plt_start@+0x140>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42be18 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x48>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 42cbe4 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0xe14>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 376 bytes (47 double precision FP elements). The binary function is storing 392 bytes (49 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	254
nb uops	253
loop length	1299
used x86 registers	16
used mmx registers	0
used xmm registers	27
used ymm registers	2
used zmm registers	0
nb stack references	41

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.63 cycles
front end	31.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	13.50	13.50	13.50	13.50	13.50	13.50	26.50	26.50	26.50	26.50	0.00	1.00	3.00	3.00	16.50	16.50
cycles	13.50	13.50	13.50	13.50	13.50	13.50	26.50	26.50	26.50	26.50	0.00	1.00	3.00	3.00	16.50	16.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	31.63
Dispatch	26.50
DIV/SQRT	6.00
Overall L1	31.63

Vectorization ratios

INT

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	33%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	17%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	44%

Vector efficiency ratios

INT

all	12%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

INT+FP

all	13%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.63 cycles. At this rate:

4% of peak load performance is reached (11.89 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42bdd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x140,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 402380 <@plt_start@+0x360>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4022f0 <@plt_start@+0x2d0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD																				scal (6.3%)
IDIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 42ccab <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0xedb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42cbd0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0xe00>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ 0xa8(%RBX),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R14,%RDX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x78(%RBX),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x20(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R8D,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ 0x88(%RBX),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD %R8D,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ 0x28(%RBX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x98(%RBX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R8,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ 0x38(%RBX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x40(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV (%RSI),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD %XMM2,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %XMM19,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM19,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SAL $0x3,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %XMM24,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %R14,%XMM29	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV 0xb0(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVQ %XMM24,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x1(%R11),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11D,0xfc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVSXD %R9D,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9D,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R15D,0x84(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVDQA64 %XMM13,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x80(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM25,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%R14,%R11,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R10,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R14,%R10,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%R12,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %RDX,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVQ %XMM25,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R15,%R11,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x90(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R15,%R12,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R12,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%R9,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RDX,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %R11,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R9,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDX,%RAX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %RAX,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0xa0(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVDQA64 %XMM29,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %R11,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQA64 %XMM25,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA64 %XMM19,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %R8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ 0xb8(%RBX),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0xc8(%RBX),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R14,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xc0(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD 0x90(%RBX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDX,%RAX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD 0x76902(%RIP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x76908(%RIP),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVQ $0,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBROADCASTSD %XMM17,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM20,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
ADD %R8,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM27,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM27,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R14,%R11,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R9,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA64 %XMM28,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %R8,%XMM9	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV 0x138(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R15,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVQ %XMM28,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x3,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R12,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %R15,%XMM26	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV 0xd0(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R14,%R10,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (,%R9,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM28,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R8,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL %RDX,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R15,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R9,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R9,%R15,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R9,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM27,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xfc(%RSP),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDX,%R12,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM28,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVDQA64 %XMM24,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R12,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x3,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVDQA64 %XMM10,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%R14,%R8,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x130(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x138(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R14,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL %RDX,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
SUB %R8D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R9D,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9D,0x5c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SHR $0x3,%R9D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R12,%R11,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R15,%R12,1),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM1,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R11,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x3,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R15,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SAL $0x6,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R11,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM27,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM11,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM8,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM4,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA64 %XMM9,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x10(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %R8B,%R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 42ccb4 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0xee4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13D,0xd8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 42cbe4 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0xe14>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD %XMM2,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM3,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM5,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM6,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM7,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 402120 <@plt_start@+0x100>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x68(%RBX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x138(%RSP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x130(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x128(%RSP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x120(%RSP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x118(%RSP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RCX),%XMM7,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM6,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD (%RSI),%XMM3,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM2,(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD (%R10),%XMM5,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM10,(%R10)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD (%R13),%XMM12,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD (%R12),%XMM9,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM14,(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 402160 <@plt_start@+0x140>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42be18 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x48>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 42cbe4 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0xe14>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0–	0.30	0.11
▼Loop 173 - field_summary_kernel.f90:57-71 - exec–	0.00	0.00
○Loop 174 - field_summary_kernel.f90:62-71 - exec	0.30	0.11

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512-bits vectorization

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Code clean check

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Vectorization

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code