OV - exec - Function __revert_kernel_module_MOD_revert_kernel._omp

	Function: __revert_kernel_module_MOD_revert_kernel._omp_fn.0	Module: exec	Source: revert_kernel.f90:41-48	Coverage (incl. loops): 2.55% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90: 41 - 48

--------------------------------------------------------------------------------

41:     !$OMP PARALLEL

42:

43:     !$OMP DO

44:     DO k=y_min,y_max

45:     !$OMP SIMD

46:       DO j=x_min,x_max

47:         density1(j,k)=density0(j,k)

48:         energy1(j,k)=energy0(j,k)

0x443f70 PUSH	%RBP

0x443f71 MOV	%RSP,%RBP

0x443f74 PUSH	%R15

0x443f76 PUSH	%R14

0x443f78 PUSH	%R13

0x443f7a PUSH	%R12

0x443f7c PUSH	%RBX

0x443f7d MOV	%RDI,%RBX

0x443f80 AND	$-0x40,%RSP

0x443f84 SUB	$0x40,%RSP

0x443f88 MOV	0x10(%RDI),%RAX

0x443f8c MOV	(%RAX),%R14D

0x443f8f CALL	402380 <@plt_start@+0x360>

0x443f94 MOV	%EAX,%R13D

0x443f97 CALL	4022f0 <@plt_start@+0x2d0>

0x443f9c MOV	0x18(%RBX),%RDX

0x443fa0 MOV	%EAX,%ECX

0x443fa2 MOV	(%RDX),%EAX

0x443fa4 INC	%EAX

0x443fa6 SUB	%R14D,%EAX

0x443fa9 CLTD

0x443faa IDIV	%R13D

0x443fad CMP	%EDX,%ECX

0x443faf JL	4444cf

0x443fb5 IMUL	%EAX,%ECX

0x443fb8 ADD	%ECX,%EDX

0x443fba ADD	%EDX,%EAX

0x443fbc CMP	%EAX,%EDX

0x443fbe JGE	4444ae

0x443fc4 MOV	(%RBX),%RSI

0x443fc7 MOV	0x8(%RBX),%RDI

0x443fcb VMOVQ	0x50(%RBX),%XMM9

0x443fd0 VMOVQ	0x40(%RBX),%XMM8

0x443fd5 ADD	%R14D,%EDX

0x443fd8 VMOVQ	0x60(%RBX),%XMM7

0x443fdd VMOVQ	0x70(%RBX),%XMM6

0x443fe2 ADD	%R14D,%EAX

0x443fe5 MOVSXD	%EDX,%R13

0x443fe8 MOV	%EAX,0x2c(%RSP)

0x443fec VMOVQ	0x20(%RBX),%XMM0

0x443ff1 VMOVQ	0x28(%RBX),%XMM2

0x443ff6 VMOVQ	0x30(%RBX),%XMM3

0x443ffb VMOVQ	0x38(%RBX),%XMM4

0x444000 MOVSXD	(%RSI),%R15

0x444003 MOV	(%RDI),%R11D

0x444006 MOV	0x58(%RBX),%RDI

0x44400a MOV	0x48(%RBX),%RSI

0x44400e VMOVQ	%XMM9,%R9

0x444013 VMOVQ	%XMM8,%R8

0x444018 IMUL	%R13,%R9

0x44401c VMOVQ	%XMM6,%RAX

0x444021 VMOVQ	%XMM7,%RCX

0x444026 IMUL	%R13,%R8

0x44402a IMUL	%R13,%RCX

0x44402e ADD	%R15,%RDI

0x444031 ADD	%R15,%RSI

0x444034 MOV	%R15,%R14

0x444037 LEA	0x1(%R11),%R10D

0x44403b ADD	%R9,%RDI

0x44403e MOV	0x78(%RBX),%R9

0x444042 IMUL	%RAX,%R13

0x444046 ADD	%R8,%RSI

0x444049 MOV	0x68(%RBX),%R8

0x44404d MOV	%R15D,0x24(%RSP)

0x444052 MOV	%R11D,0x28(%RSP)

0x444057 ADD	%R15,%R9

0x44405a ADD	%R13,%R9

0x44405d MOV	%R11D,%R13D

0x444060 ADD	%R15,%R8

0x444063 SUB	%R15D,%R13D

0x444066 ADD	%RCX,%R8

0x444069 MOV	%R13D,0x38(%RSP)

0x44406e INC	%R13D

0x444071 CMP	%R11D,%R15D

0x444074 CMOVLE	%R10D,%R14D

0x444078 MOV	%R14D,%EAX

0x44407b JG	4444d8

0x444081 MOV	%R13D,%R12D

0x444084 MOV	%R13D,%R14D

0x444087 VMOVQ	%R15,%XMM1

0x44408c AND	$0x7,%R13D

0x444090 SHR	$0x3,%R12D

0x444094 MOV	%R13D,0x1c(%RSP)

0x444099 MOV	%EAX,0x18(%RSP)

0x44409d MOV	%RBX,0x10(%RSP)

0x4440a2 VMOVQ	%XMM2,%R15

0x4440a7 VMOVQ	%XMM3,%R10

0x4440ac AND	$-0x8,%R14D

0x4440b0 SAL	$0x6,%R12

0x4440b4 MOV	%R14D,0x20(%RSP)

0x4440b9 VMOVQ	%XMM0,%R14

0x4440be MOV	%R12,0x30(%RSP)

0x4440c3 NOPW	%CS:(%RAX,%RAX,1)

0x4440ce XCHG	%AX,%AX

(364) 0x4440d0 CMPL	$0x6,0x38(%RSP)

(364) 0x4440d5 JBE	4444c0

(364) 0x4440db MOV	0x30(%RSP),%RCX

(364) 0x4440e0 VMOVQ	%XMM4,%R11

(364) 0x4440e5 XOR	%EAX,%EAX

(364) 0x4440e7 LEA	(%R14,%RSI,8),%R13

(364) 0x4440eb LEA	(%R15,%RDI,8),%R12

(364) 0x4440ef LEA	(%R10,%R8,8),%RBX

(364) 0x4440f3 LEA	(%R11,%R9,8),%R11

(364) 0x4440f7 SUB	$0x40,%RCX

(364) 0x4440fb SHR	$0x6,%RCX

(364) 0x4440ff INC	%RCX

(364) 0x444102 AND	$0x7,%ECX

(364) 0x444105 JE	44422b

(364) 0x44410b CMP	$0x1,%RCX

(364) 0x44410f JE	4441ff

(364) 0x444115 CMP	$0x2,%RCX

(364) 0x444119 JE	4441de

(364) 0x44411f CMP	$0x3,%RCX

(364) 0x444123 JE	4441bd

(364) 0x444129 CMP	$0x4,%RCX

(364) 0x44412d JE	44419c

(364) 0x44412f CMP	$0x5,%RCX

(364) 0x444133 JE	44417b

(364) 0x444135 CMP	$0x6,%RCX

(364) 0x444139 JE	44415a

(364) 0x44413b VMOVUPD	(%R13),%ZMM5

(364) 0x444142 MOV	$0x40,%EAX

(364) 0x444147 VMOVUPD	%ZMM5,(%R12)

(364) 0x44414e VMOVUPD	(%RBX),%ZMM10

(364) 0x444154 VMOVUPD	%ZMM10,(%R11)

(364) 0x44415a VMOVUPD	(%R13,%RAX,1),%ZMM11

(364) 0x444162 VMOVUPD	%ZMM11,(%R12,%RAX,1)

(364) 0x444169 VMOVUPD	(%RBX,%RAX,1),%ZMM12

(364) 0x444170 VMOVUPD	%ZMM12,(%R11,%RAX,1)

(364) 0x444177 ADD	$0x40,%RAX

(364) 0x44417b VMOVUPD	(%R13,%RAX,1),%ZMM13

(364) 0x444183 VMOVUPD	%ZMM13,(%R12,%RAX,1)

(364) 0x44418a VMOVUPD	(%RBX,%RAX,1),%ZMM14

(364) 0x444191 VMOVUPD	%ZMM14,(%R11,%RAX,1)

(364) 0x444198 ADD	$0x40,%RAX

(364) 0x44419c VMOVUPD	(%R13,%RAX,1),%ZMM15

(364) 0x4441a4 VMOVUPD	%ZMM15,(%R12,%RAX,1)

(364) 0x4441ab VMOVUPD	(%RBX,%RAX,1),%ZMM0

(364) 0x4441b2 VMOVUPD	%ZMM0,(%R11,%RAX,1)

(364) 0x4441b9 ADD	$0x40,%RAX

(364) 0x4441bd VMOVUPD	(%R13,%RAX,1),%ZMM2

(364) 0x4441c5 VMOVUPD	%ZMM2,(%R12,%RAX,1)

(364) 0x4441cc VMOVUPD	(%RBX,%RAX,1),%ZMM3

(364) 0x4441d3 VMOVUPD	%ZMM3,(%R11,%RAX,1)

(364) 0x4441da ADD	$0x40,%RAX

(364) 0x4441de VMOVUPD	(%R13,%RAX,1),%ZMM5

(364) 0x4441e6 VMOVUPD	%ZMM5,(%R12,%RAX,1)

(364) 0x4441ed VMOVUPD	(%RBX,%RAX,1),%ZMM10

(364) 0x4441f4 VMOVUPD	%ZMM10,(%R11,%RAX,1)

(364) 0x4441fb ADD	$0x40,%RAX

(364) 0x4441ff VMOVUPD	(%R13,%RAX,1),%ZMM11

(364) 0x444207 VMOVUPD	%ZMM11,(%R12,%RAX,1)

(364) 0x44420e VMOVUPD	(%RBX,%RAX,1),%ZMM12

(364) 0x444215 VMOVUPD	%ZMM12,(%R11,%RAX,1)

(364) 0x44421c ADD	$0x40,%RAX

(364) 0x444220 CMP	%RAX,0x30(%RSP)

(364) 0x444225 JE	444339

  (365) 0x44422b VMOVUPD	(%R13,%RAX,1),%ZMM13

  (365) 0x444233 VMOVUPD	%ZMM13,(%R12,%RAX,1)

  (365) 0x44423a VMOVUPD	(%RBX,%RAX,1),%ZMM14

  (365) 0x444241 VMOVUPD	%ZMM14,(%R11,%RAX,1)

  (365) 0x444248 VMOVUPD	0x40(%R13,%RAX,1),%ZMM15

  (365) 0x444250 VMOVUPD	%ZMM15,0x40(%R12,%RAX,1)

  (365) 0x444258 VMOVUPD	0x40(%RBX,%RAX,1),%ZMM0

  (365) 0x444260 VMOVUPD	%ZMM0,0x40(%R11,%RAX,1)

  (365) 0x444268 VMOVUPD	0x80(%R13,%RAX,1),%ZMM2

  (365) 0x444270 VMOVUPD	%ZMM2,0x80(%R12,%RAX,1)

  (365) 0x444278 VMOVUPD	0x80(%RBX,%RAX,1),%ZMM3

  (365) 0x444280 VMOVUPD	%ZMM3,0x80(%R11,%RAX,1)

  (365) 0x444288 VMOVUPD	0xc0(%R13,%RAX,1),%ZMM5

  (365) 0x444290 VMOVUPD	%ZMM5,0xc0(%R12,%RAX,1)

  (365) 0x444298 VMOVUPD	0xc0(%RBX,%RAX,1),%ZMM10

  (365) 0x4442a0 VMOVUPD	%ZMM10,0xc0(%R11,%RAX,1)

  (365) 0x4442a8 VMOVUPD	0x100(%R13,%RAX,1),%ZMM11

  (365) 0x4442b0 VMOVUPD	%ZMM11,0x100(%R12,%RAX,1)

  (365) 0x4442b8 VMOVUPD	0x100(%RBX,%RAX,1),%ZMM12

  (365) 0x4442c0 VMOVUPD	%ZMM12,0x100(%R11,%RAX,1)

  (365) 0x4442c8 VMOVUPD	0x140(%R13,%RAX,1),%ZMM13

  (365) 0x4442d0 VMOVUPD	%ZMM13,0x140(%R12,%RAX,1)

  (365) 0x4442d8 VMOVUPD	0x140(%RBX,%RAX,1),%ZMM14

  (365) 0x4442e0 VMOVUPD	%ZMM14,0x140(%R11,%RAX,1)

  (365) 0x4442e8 VMOVUPD	0x180(%R13,%RAX,1),%ZMM15

  (365) 0x4442f0 VMOVUPD	%ZMM15,0x180(%R12,%RAX,1)

  (365) 0x4442f8 VMOVUPD	0x180(%RBX,%RAX,1),%ZMM0

  (365) 0x444300 VMOVUPD	%ZMM0,0x180(%R11,%RAX,1)

  (365) 0x444308 VMOVUPD	0x1c0(%R13,%RAX,1),%ZMM2

  (365) 0x444310 VMOVUPD	%ZMM2,0x1c0(%R12,%RAX,1)

  (365) 0x444318 VMOVUPD	0x1c0(%RBX,%RAX,1),%ZMM3

  (365) 0x444320 VMOVUPD	%ZMM3,0x1c0(%R11,%RAX,1)

  (365) 0x444328 ADD	$0x200,%RAX

  (365) 0x44432e CMP	%RAX,0x30(%RSP)

  (365) 0x444333 JNE	44422b

(364) 0x444339 MOV	0x20(%RSP),%R13D

(364) 0x44433e MOV	0x24(%RSP),%R12D

(364) 0x444343 MOV	0x1c(%RSP),%EBX

(364) 0x444347 MOV	%R13D,%ECX

(364) 0x44434a ADD	%R12D,%R13D

(364) 0x44434d MOV	%R13D,0x3c(%RSP)

(364) 0x444352 TEST	%EBX,%EBX

(364) 0x444354 JE	44446c

(364) 0x44435a MOV	0x38(%RSP),%R11D

(364) 0x44435f SUB	%ECX,%R11D

(364) 0x444362 LEA	0x1(%R11),%EAX

(364) 0x444366 CMP	$0x2,%R11D

(364) 0x44436a JBE	4443aa

(364) 0x44436c LEA	(%RCX,%RSI,1),%R13

(364) 0x444370 LEA	(%RCX,%RDI,1),%R12

(364) 0x444374 LEA	(%RCX,%R8,1),%RBX

(364) 0x444378 VMOVQ	%XMM4,%R11

(364) 0x44437d VMOVUPD	(%R14,%R13,8),%YMM5

(364) 0x444383 ADD	%R9,%RCX

(364) 0x444386 VMOVUPD	%YMM5,(%R15,%R12,8)

(364) 0x44438c VMOVUPD	(%R10,%RBX,8),%YMM10

(364) 0x444392 VMOVUPD	%YMM10,(%R11,%RCX,8)

(364) 0x444398 MOV	%EAX,%ECX

(364) 0x44439a AND	$-0x4,%ECX

(364) 0x44439d ADD	%ECX,0x3c(%RSP)

(364) 0x4443a1 AND	$0x3,%EAX

(364) 0x4443a4 JE	44446c

(364) 0x4443aa MOVSXD	0x3c(%RSP),%RCX

(364) 0x4443af VMOVQ	%XMM1,%RAX

(364) 0x4443b4 MOV	%RSI,%R13

(364) 0x4443b7 MOV	%RDI,%R12

(364) 0x4443ba SUB	%RAX,%R13

(364) 0x4443bd MOV	%R8,%RBX

(364) 0x4443c0 MOV	%R9,%R11

(364) 0x4443c3 SUB	%RAX,%R12

(364) 0x4443c6 SUB	%RAX,%RBX

(364) 0x4443c9 SUB	%RAX,%R11

(364) 0x4443cc LEA	(%R13,%RCX,1),%RAX

(364) 0x4443d1 VMOVSD	(%R14,%RAX,8),%XMM11

(364) 0x4443d7 LEA	(%RCX,%R12,1),%RAX

(364) 0x4443db VMOVSD	%XMM11,(%R15,%RAX,8)

(364) 0x4443e1 LEA	(%RCX,%RBX,1),%RAX

(364) 0x4443e5 ADD	%R11,%RCX

(364) 0x4443e8 VMOVSD	(%R10,%RAX,8),%XMM12

(364) 0x4443ee VMOVQ	%XMM4,%RAX

(364) 0x4443f3 VMOVSD	%XMM12,(%RAX,%RCX,8)

(364) 0x4443f8 MOV	0x3c(%RSP),%ECX

(364) 0x4443fc LEA	0x1(%RCX),%EAX

(364) 0x4443ff CMP	%EAX,0x28(%RSP)

(364) 0x444403 JL	44446c

(364) 0x444405 MOVSXD	%EAX,%RCX

(364) 0x444408 LEA	(%RCX,%R13,1),%RAX

(364) 0x44440c VMOVSD	(%R14,%RAX,8),%XMM13

(364) 0x444412 LEA	(%RCX,%R12,1),%RAX

(364) 0x444416 VMOVSD	%XMM13,(%R15,%RAX,8)

(364) 0x44441c LEA	(%RCX,%RBX,1),%RAX

(364) 0x444420 ADD	%R11,%RCX

(364) 0x444423 VMOVSD	(%R10,%RAX,8),%XMM14

(364) 0x444429 VMOVQ	%XMM4,%RAX

(364) 0x44442e VMOVSD	%XMM14,(%RAX,%RCX,8)

(364) 0x444433 MOV	0x3c(%RSP),%EAX

(364) 0x444437 ADD	$0x2,%EAX

(364) 0x44443a CMP	%EAX,0x28(%RSP)

(364) 0x44443e JL	44446c

(364) 0x444440 CLTQ

(364) 0x444442 ADD	%RAX,%R13

(364) 0x444445 ADD	%RAX,%R12

(364) 0x444448 ADD	%RAX,%RBX

(364) 0x44444b ADD	%RAX,%R11

(364) 0x44444e VMOVSD	(%R14,%R13,8),%XMM15

(364) 0x444454 VMOVQ	%XMM4,%R13

(364) 0x444459 VMOVSD	%XMM15,(%R15,%R12,8)

(364) 0x44445f VMOVSD	(%R10,%RBX,8),%XMM0

(364) 0x444465 VMOVSD	%XMM0,(%R13,%R11,8)

(364) 0x44446c VMOVQ	%XMM8,%R12

(364) 0x444471 VMOVQ	%XMM9,%RBX

(364) 0x444476 INC	%EDX

(364) 0x444478 VMOVQ	%XMM7,%R11

(364) 0x44447d VMOVQ	%XMM6,%RCX

(364) 0x444482 ADD	%R12,%RSI

(364) 0x444485 ADD	%RBX,%RDI

(364) 0x444488 ADD	%R11,%R8

(364) 0x44448b ADD	%RCX,%R9

(364) 0x44448e CMP	%EDX,0x2c(%RSP)

(364) 0x444492 JG	4440d0

0x444498 MOV	0x18(%RSP),%EAX

0x44449c MOV	0x10(%RSP),%RBX

0x4444a1 VZEROUPPER

0x4444a4 MOV	%EAX,%R12D

0x4444a7 MOV	%R12D,0x80(%RBX)

0x4444ae LEA	-0x28(%RBP),%RSP

0x4444b2 POP	%RBX

0x4444b3 POP	%R12

0x4444b5 POP	%R13

0x4444b7 POP	%R14

0x4444b9 POP	%R15

0x4444bb POP	%RBP

0x4444bc RET

0x4444bd NOPL	(%RAX)

(364) 0x4444c0 MOV	0x24(%RSP),%EBX

(364) 0x4444c4 XOR	%ECX,%ECX

(364) 0x4444c6 MOV	%EBX,0x3c(%RSP)

(364) 0x4444ca JMP	44435a

0x4444cf INC	%EAX

0x4444d1 XOR	%EDX,%EDX

0x4444d3 JMP	443fb5

0x4444d8 XOR	%R15D,%R15D

0x4444db NOPL	(%RAX,%RAX,1)

(363) 0x4444e0 INC	%EDX

(363) 0x4444e2 CMP	%EAX,%R10D

(363) 0x4444e5 JE	444501

(363) 0x4444e7 CMP	%EDX,0x2c(%RSP)

(363) 0x4444eb JG	4444e0

0x4444ed TEST	%R15B,%R15B

0x4444f0 JNE	4444a7

0x4444f2 LEA	-0x28(%RBP),%RSP

0x4444f6 POP	%RBX

0x4444f7 POP	%R12

0x4444f9 POP	%R13

0x4444fb POP	%R14

0x4444fd POP	%R15

0x4444ff POP	%RBP

0x444500 RET

(363) 0x444501 CMP	%EDX,0x2c(%RSP)

(363) 0x444505 JLE	4444a4

(363) 0x444507 MOV	%R10D,%R12D

(363) 0x44450a MOV	$0x1,%R15D

(363) 0x444510 JMP	4444e0

0x444512 NOPW	%CS:(%RAX,%RAX,1)

0x44451d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►95.78+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►4.13+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	revert_kernel	revert_kernel.f90:55	exec
○	revert	revert.f90:37	exec
○	pdv	PdV.f90:137	exec
○	hydro	hydro.f90:56	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	revert_kernel.f90:41-48
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:41-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.25 to 3.50 cycles (4.36x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.25 to 1.14 cycles (13.42x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:45
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 156 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	125
nb uops	122
loop length	443
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.25 cycles
front end	15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	3.50	3.50
cycles	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	3.50	3.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	15.25
Dispatch	8.50
DIV/SQRT	6.00
Overall L1	15.25

Vectorization ratios

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	3%

Vector efficiency ratios

all	9%
load	11%
store	7%
mul	11%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.25 cycles. At this rate:

3% of peak load performance is reached (10.23 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.15 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.25 to 8.50 cycles (1.79x speedup).

ASM code

In the binary file, the address of the function is: 443f70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
CALL 402380 <@plt_start@+0x360>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4022f0 <@plt_start@+0x2d0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 4444cf <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x55f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 4444ae <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x53e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x50(%RBX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x40(%RBX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x60(%RBX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x70(%RBX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %EDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ 0x20(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x28(%RBX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x38(%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD (%RSI),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
VMOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %R13,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA 0x1(%R11),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
IMUL %RAX,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R15D,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R11D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD %R15,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R13,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R11D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %R15,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R15D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R13D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R11D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMOVLE %R10D,%R14D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JG 4444d8 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x568>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R13D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ %R15,%XMM1	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
AND $0x7,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x3,%R12D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOV %R13D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RBX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM2,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM3,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
AND $-0x8,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R14D,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ %XMM0,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x18(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R12D,0x80(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 443fb5 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x45>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
TEST %R15B,%R15B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4444a7 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x537>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	revert_kernel.f90:41-48
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.25 to 3.50 cycles (4.36x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:45
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 156 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	125
nb uops	122
loop length	443
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.25 cycles
front end	15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	3.50	3.50
cycles	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	3.50	3.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	15.25
Dispatch	8.50
DIV/SQRT	6.00
Overall L1	15.25

Vectorization ratios

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	3%

Vector efficiency ratios

all	9%
load	11%
store	7%
mul	11%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.25 cycles. At this rate:

3% of peak load performance is reached (10.23 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.15 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 443f70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
CALL 402380 <@plt_start@+0x360>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4022f0 <@plt_start@+0x2d0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 4444cf <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x55f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 4444ae <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x53e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x50(%RBX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x40(%RBX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ 0x60(%RBX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x70(%RBX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %EDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ 0x20(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x28(%RBX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x38(%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD (%RSI),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
VMOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IMUL %R13,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %R13,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA 0x1(%R11),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
IMUL %RAX,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R15D,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R11D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADD %R15,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R13,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R11D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %R15,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R15D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R13D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R11D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMOVLE %R10D,%R14D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JG 4444d8 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x568>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R13D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ %R15,%XMM1	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
AND $0x7,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x3,%R12D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOV %R13D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RBX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM2,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM3,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
AND $-0x8,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R14D,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVQ %XMM0,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x18(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R12D,0x80(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 443fb5 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x45>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
TEST %R15B,%R15B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4444a7 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x537>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼__revert_kernel_module_MOD_revert_kernel._omp_fn.0–	2.55	0.96
▼Loop 364 - revert_kernel.f90:45-48 - exec–	0.00	0.00
○Loop 365 - revert_kernel.f90:47-48 - exec	2.55	0.96
○Loop 363 - revert_kernel.f90:41-45 - exec	0.00	0.00

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