OV - exec - Loop 879

	Loop Id: 879	Module: exec	Source: viscosity_kernel.f90:53-89	Coverage: 6.50%

0x45d550 VCMPPD	$0x1,%YMM13,%YMM22,%K3

0x45d557 VBROADCASTSD	0xb6220(%RIP),%YMM8    [10]

0x45d560 VBLENDMPD	%YMM8,%YMM18,%YMM31{%K3}

0x45d566 VBROADCASTSD	0x98bb0(%RIP),%YMM29    [10]

0x45d570 VANDPD	%YMM29,%YMM22,%YMM1

0x45d576 VMAXPD	%YMM1,%YMM14,%YMM1

0x45d57a VMULPD	%YMM31,%YMM1,%YMM1

0x45d580 VCMPPD	$0x1,%YMM13,%YMM1,%K3

0x45d587 VBLENDMPD	%YMM8,%YMM18,%YMM25{%K3}

0x45d58d VANDPD	%YMM29,%YMM21,%YMM13

0x45d593 VMAXPD	%YMM13,%YMM14,%YMM13

0x45d598 VMULPD	%YMM25,%YMM13,%YMM13

0x45d59e VMULPD	%YMM1,%YMM1,%YMM20

0x45d5a4 VFMADD231PD	%YMM13,%YMM13,%YMM20

0x45d5aa VXORPD	%XMM28,%XMM28,%XMM28

0x45d5b0 VSQRTPD	%YMM20,%YMM23

0x45d5b6 VMULPD	%YMM2,%YMM23,%YMM2

0x45d5bc VDIVPD	%YMM1,%YMM2,%YMM1

0x45d5c0 VANDPD	%YMM29,%YMM1,%YMM22

0x45d5c6 VMULPD	%YMM24,%YMM23,%YMM1

0x45d5cc VDIVPD	%YMM13,%YMM1,%YMM1

0x45d5d1 VANDPD	%YMM29,%YMM1,%YMM21

0x45d5d7 VCMPPD	$0x2,%YMM21,%YMM22,%K3

0x45d5de VBLENDMPD	%YMM22,%YMM21,%YMM30{%K3}

0x45d5e4 VMULPD	%YMM30,%YMM30,%YMM29

0x45d5ea VMULPD	%YMM10,%YMM10,%YMM1

0x45d5ef IMUL	%R8,%RCX

0x45d5f3 ADD	%R9,%RCX

0x45d5f6 VMOVUPD	(%RCX,%R13,8),%YMM2{%K2}{z}    [3]

0x45d5fd VADDPD	%YMM29,%YMM29,%YMM10

0x45d603 VMULPD	%YMM2,%YMM1,%YMM1

0x45d607 VMULPD	%YMM1,%YMM10,%YMM1

0x45d60b VPBROADCASTQ	%R13,%YMM2

0x45d611 VPADDQ	0x99967(%RIP),%YMM2,%YMM2    [10]

0x45d619 VPBLENDMQ	%YMM5,%YMM2,%YMM5{%K1}

0x45d61f VMOVAPD	%YMM4,%YMM31{%K1}

0x45d625 VPBLENDMQ	%YMM9,%YMM2,%YMM9{%K1}

0x45d62b VMOVAPD	%YMM17,%YMM25{%K1}

0x45d631 VPBLENDMQ	%YMM6,%YMM2,%YMM6{%K1}

0x45d637 VMOVAPD	%YMM16,%YMM23{%K1}

0x45d63d VPBLENDMQ	%YMM3,%YMM2,%YMM3{%K1}

0x45d643 VMOVAPD	%YMM15,%YMM22{%K1}

0x45d649 VPBLENDMQ	%YMM11,%YMM2,%YMM11{%K1}

0x45d64f VMOVAPD	%YMM19,%YMM21{%K1}

0x45d655 VPBLENDMQ	%YMM12,%YMM2,%YMM12{%K1}

0x45d65b VMOVAPD	%YMM0,%YMM30{%K1}

0x45d661 VMOVDQA64	%YMM7,%YMM2{%K1}

0x45d667 VMOVAPD	%YMM27,%YMM29{%K1}

0x45d66d VMOVAPD	%YMM28,%YMM1{%K1}

0x45d673 VMOVUPD	%YMM1,(%R12,%R13,8)    [7]

0x45d679 ADD	$0x4,%R13

0x45d67d VMOVDQA	%YMM2,%YMM7

0x45d681 VMOVAPD	%YMM29,%YMM27

0x45d687 VMOVAPD	%YMM30,%YMM0

0x45d68d VMOVAPD	%YMM21,%YMM19

0x45d693 VMOVAPD	%YMM22,%YMM15

0x45d699 VMOVAPD	%YMM23,%YMM16

0x45d69f VMOVAPD	%YMM25,%YMM17

0x45d6a5 VMOVAPD	%YMM31,%YMM4

0x45d6ab CMP	%RDI,%R13

0x45d6ae VMOVAPD	%YMM14,%YMM8

0x45d6b3 JAE	45d850

0x45d6b9 VMOVUPD	-0x8(%R10,%R13,8),%YMM10    [1]

0x45d6c0 VMOVUPD	(%R10,%R13,8),%YMM21    [1]

0x45d6c7 VMOVUPD	-0x8(%R14,%R13,8),%YMM22    [8]

0x45d6d2 VMOVUPD	(%R14,%R13,8),%YMM23    [8]

0x45d6d9 VADDPD	%YMM21,%YMM23,%YMM2

0x45d6df VADDPD	%YMM22,%YMM10,%YMM25

0x45d6e5 VMOVUPD	-0x8(%RDX,%R13,8),%YMM29    [9]

0x45d6f0 VMOVUPD	(%RDX,%R13,8),%YMM30    [9]

0x45d6f7 VSUBPD	%YMM25,%YMM2,%YMM25

0x45d6fd VMOVUPD	-0x8(%RSI,%R13,8),%YMM31    [14]

0x45d708 VMOVUPD	(%RSI,%R13,8),%YMM20    [14]

0x45d70f VADDPD	%YMM29,%YMM30,%YMM2

0x45d715 VADDPD	%YMM20,%YMM31,%YMM1

0x45d71b VSUBPD	%YMM1,%YMM2,%YMM1

0x45d71f MOV	0x158(%RSP),%RCX    [13]

0x45d727 VMOVUPD	-0x8(%RCX,%R13,8),%YMM2    [5]

0x45d72e VMULPD	%YMM25,%YMM2,%YMM13

0x45d734 VFMADD231PD	%YMM1,%YMM24,%YMM13

0x45d73a VADDPD	%YMM10,%YMM21,%YMM10

0x45d740 VSUBPD	%YMM10,%YMM23,%YMM10

0x45d746 VADDPD	%YMM22,%YMM10,%YMM10

0x45d74c VBROADCASTSD	0x9980b(%RIP),%YMM14    [10]

0x45d755 VMULPD	%YMM14,%YMM10,%YMM10

0x45d75a VADDPD	%YMM31,%YMM29,%YMM21

0x45d760 VSUBPD	%YMM21,%YMM30,%YMM21

0x45d766 VADDPD	%YMM20,%YMM21,%YMM20

0x45d76c VMULPD	%YMM14,%YMM20,%YMM20

0x45d772 VDIVPD	%YMM2,%YMM18,%YMM23

0x45d778 VMULPD	%YMM23,%YMM20,%YMM20

0x45d77e VMOVUPD	(%RAX,%R13,8),%YMM21    [12]

0x45d785 VFMADD231PD	%YMM10,%YMM26,%YMM20

0x45d78b VSUBPD	-0x10(%RAX,%R13,8),%YMM21,%YMM10    [12]

0x45d796 VADDPD	(%RCX,%R13,8),%YMM2,%YMM21    [5]

0x45d79d VDIVPD	%YMM21,%YMM10,%YMM22

0x45d7a3 VMOVUPD	(%R15,%R13,8),%YMM10    [11]

0x45d7a9 VSUBPD	(%R11,%R13,8),%YMM10,%YMM10    [2]

0x45d7af VMULPD	0x180(%RSP),%YMM10,%YMM21    [13]

0x45d7b7 VMULPD	%YMM22,%YMM22,%YMM10

0x45d7bd VMULPD	%YMM21,%YMM21,%YMM29

0x45d7c3 VMULPD	%YMM14,%YMM25,%YMM25

0x45d7c9 VMULPD	%YMM23,%YMM25,%YMM23

0x45d7cf VMULPD	%YMM10,%YMM23,%YMM23

0x45d7d5 VMULPD	%YMM1,%YMM14,%YMM1

0x45d7d9 VMULPD	%YMM29,%YMM1,%YMM1

0x45d7df VMULPD	%YMM20,%YMM22,%YMM20

0x45d7e5 VFMADD213PD	%YMM23,%YMM21,%YMM20

0x45d7eb VFMADD231PD	%YMM1,%YMM26,%YMM20

0x45d7f1 VADDPD	%YMM10,%YMM29,%YMM1

0x45d7f7 VMAXPD	%YMM8,%YMM1,%YMM1

0x45d7fc VDIVPD	%YMM1,%YMM20,%YMM10

0x45d802 VCMPPD	$0x1,%YMM10,%YMM28,%K1

0x45d809 VCMPPD	$0x2,%YMM13,%YMM28,%K0

0x45d810 VCMPPD	$0x6,%YMM13,%YMM28,%K1{%K1}

0x45d817 KORW	%K1,%K0,%K1

0x45d81b KNOTW	%K1,%K2

0x45d81f KMOVD	%K2,%EBX

0x45d823 TEST	$0xf,%BL

0x45d826 VMOVAPD	%YMM8,%YMM14

0x45d82b VXORPD	%XMM13,%XMM13,%XMM13

0x45d830 JE	45d550

0x45d836 MOV	0x78(%RBP),%RCX    [6]

0x45d83a MOV	(%RCX),%RCX    [4]

0x45d83d JMP	45d550

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 53 - 89

--------------------------------------------------------------------------------

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Coverage (%)	Name	Source Location	Module
►48.52+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►38.59+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►5.83+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
►4.30+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	viscosity_kernel	viscosity_kernel.f90:98	exec
○	viscosity	viscosity.f90:40	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.47+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks
Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source	viscosity_kernel.f90:53-89
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	28.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	14.25
CQA cycles if fully vectorized	14.25
Front-end cycles	15.56
P0 cycles	1.25
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	5.75
P7 cycles	5.75
P8 cycles	5.75
P9 cycles	5.75
P10 cycles	19.00
P11 cycles	19.00
P12 cycles	19.00
P13 cycles	19.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	28.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	123.50
Nb uops	124.50
Nb loads	22.00
Nb stores	1.00
Nb stack references	2.50
FLOP/cycle	7.72
Nb FLOP add-sub	68.00
Nb FLOP mul	88.00
Nb FLOP fma	20.00
Nb FLOP div	20.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.61
Bytes prefetched	0.00
Bytes loaded	584.00
Bytes stored	32.00
Stride 0	2.50
Stride 1	4.00
Stride n	0.00
Stride unknown	0.50
Stride indirect	0.00
Vectorization ratio all	95.54
Vectorization ratio load	85.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	89.58
Vector-efficiency ratio all	47.88
Vector-efficiency ratio load	44.38
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	45.05

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11,
Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source	viscosity_kernel.f90:53-89
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	28.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	14.25
CQA cycles if fully vectorized	14.25
Front-end cycles	15.75
P0 cycles	1.33
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	19.00
P11 cycles	19.00
P12 cycles	19.00
P13 cycles	19.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	28.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	125.00
Nb uops	126.00
Nb loads	23.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	7.72
Nb FLOP add-sub	68.00
Nb FLOP mul	88.00
Nb FLOP fma	20.00
Nb FLOP div	20.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.89
Bytes prefetched	0.00
Bytes loaded	592.00
Bytes stored	32.00
Stride 0	3.00
Stride 1	4.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	95.54
Vectorization ratio load	85.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	89.58
Vector-efficiency ratio all	47.88
Vector-efficiency ratio load	44.38
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	45.05

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11,
Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source	viscosity_kernel.f90:53-89
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	28.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	14.25
CQA cycles if fully vectorized	14.25
Front-end cycles	15.38
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	5.50
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	19.00
P11 cycles	19.00
P12 cycles	19.00
P13 cycles	19.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	28.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	123.00
Nb loads	21.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	7.72
Nb FLOP add-sub	68.00
Nb FLOP mul	88.00
Nb FLOP fma	20.00
Nb FLOP div	20.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	95.54
Vectorization ratio load	85.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	89.58
Vector-efficiency ratio all	47.88
Vector-efficiency ratio load	44.38
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	45.05

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	viscosity_kernel.f90:53-89
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:53-89.

It is main loop of related source loop which is unrolled by 4 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
89% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.50 to 19.00 cycles (1.50x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTQ: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 0 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

59 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 220 FP arithmetical operations:

88: addition or subtraction (20 inside FMA instructions)
108: multiply (20 inside FMA instructions)
20: divide
4: square root

The binary loop is loading 584 bytes (73 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.36 FP operations per loaded or stored byte.

General properties

nb instructions	123.50
nb uops	124.50
loop length	748
used x86 registers	15.50
used mmx registers	0
used xmm registers	2
used ymm registers	32
used zmm registers	0
nb stack references	2.50
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	15.56 cycles
front end	15.56 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.25	1.25	1.25	1.25	1.25	1.25	5.75	5.75	5.75	5.75	19.00	19.00	19.00	19.00	1.00	1.00
cycles	1.25	1.25	1.25	1.25	1.25	1.25	5.75	5.75	5.75	5.75	19.00	19.00	19.00	19.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	28.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	15.56
Dispatch	19.00
DIV/SQRT	28.50
Data deps.	1.00
Overall L1	28.50

Vectorization ratios

INT

all	81%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	97%
load	84%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	92%

INT+FP

all	95%
load	85%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

Vector efficiency ratios

INT

all	43%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	48%
load	44%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	45%

INT+FP

all	47%
load	44%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	45%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

8% of peak load performance is reached (20.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	viscosity_kernel.f90:53-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
89% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 28.50 to 19.00 cycles (1.50x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.50 to 19.00 cycles (1.50x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:55

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

59 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 220 FP arithmetical operations:

88: addition or subtraction (20 inside FMA instructions)
108: multiply (20 inside FMA instructions)
20: divide
4: square root

The binary loop is loading 592 bytes (74 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.35 FP operations per loaded or stored byte.

General properties

nb instructions	125
nb uops	126
loop length	754
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	32
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.75 cycles
front end	15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.33	1.33	1.33	6.00	6.00	6.00	6.00	19.00	19.00	19.00	19.00	1.00	1.00
cycles	1.33	1.33	1.33	1.33	1.33	1.33	6.00	6.00	6.00	6.00	19.00	19.00	19.00	19.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	28.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	15.75
Dispatch	19.00
DIV/SQRT	28.50
Data deps.	1.00
Overall L1	28.50

Vectorization ratios

INT

all	81%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	97%
load	84%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	92%

INT+FP

all	95%
load	85%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

Vector efficiency ratios

INT

all	43%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	48%
load	44%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	45%

INT+FP

all	47%
load	44%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	45%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

8% of peak load performance is reached (20.77 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45d6b9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VCMPPD $0x1,%YMM13,%YMM22,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0xb6220(%RIP),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBLENDMPD %YMM8,%YMM18,%YMM31{%K3}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VBROADCASTSD 0x98bb0(%RIP),%YMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %YMM29,%YMM22,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMAXPD %YMM1,%YMM14,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM31,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM13,%YMM1,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM8,%YMM18,%YMM25{%K3}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM29,%YMM21,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMAXPD %YMM13,%YMM14,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM25,%YMM13,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM1,%YMM1,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM13,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VSQRTPD %YMM20,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (50.0%)
VMULPD %YMM2,%YMM23,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VANDPD %YMM29,%YMM1,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM24,%YMM23,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM13,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VANDPD %YMM29,%YMM1,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM21,%YMM22,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM22,%YMM21,%YMM30{%K3}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM30,%YMM30,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM10,%YMM10,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%RCX,%R13,8),%YMM2{%K2}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM29,%YMM29,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM2,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM1,%YMM10,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPBROADCASTQ %R13,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ 0x99967(%RIP),%YMM2,%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VPBLENDMQ %YMM5,%YMM2,%YMM5{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM4,%YMM31{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM9,%YMM2,%YMM9{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM17,%YMM25{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM6,%YMM2,%YMM6{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM16,%YMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM3,%YMM2,%YMM3{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM15,%YMM22{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM11,%YMM2,%YMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM19,%YMM21{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM12,%YMM2,%YMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM0,%YMM30{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA64 %YMM7,%YMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM27,%YMM29{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM28,%YMM1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVUPD %YMM1,(%R12,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x4,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQA %YMM2,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM29,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM30,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM21,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM22,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM23,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM25,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM31,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
CMP %RDI,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVAPD %YMM14,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
JAE 45d850 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x840>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD -0x8(%R10,%R13,8),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R10,%R13,8),%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x8(%R14,%R13,8),%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R14,%R13,8),%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM21,%YMM23,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM22,%YMM10,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD -0x8(%RDX,%R13,8),%YMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RDX,%R13,8),%YMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM25,%YMM2,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD -0x8(%RSI,%R13,8),%YMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%R13,8),%YMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM29,%YMM30,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM20,%YMM31,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV 0x158(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD -0x8(%RCX,%R13,8),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM25,%YMM2,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM1,%YMM24,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM10,%YMM21,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM10,%YMM23,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM22,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VBROADCASTSD 0x9980b(%RIP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %YMM14,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM31,%YMM29,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM21,%YMM30,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM20,%YMM21,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM14,%YMM20,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM2,%YMM18,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM23,%YMM20,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RAX,%R13,8),%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM10,%YMM26,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSUBPD -0x10(%RAX,%R13,8),%YMM21,%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD (%RCX,%R13,8),%YMM2,%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD %YMM21,%YMM10,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMOVUPD (%R15,%R13,8),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD (%R11,%R13,8),%YMM10,%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD 0x180(%RSP),%YMM10,%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM22,%YMM22,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM21,%YMM21,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM14,%YMM25,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM23,%YMM25,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM10,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM1,%YMM14,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM29,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM20,%YMM22,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM23,%YMM21,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM1,%YMM26,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM10,%YMM29,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMAXPD %YMM8,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD %YMM1,%YMM20,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VCMPPD $0x1,%YMM10,%YMM28,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x2,%YMM13,%YMM28,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM13,%YMM28,%K1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KORW %K1,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KNOTW %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVD %K2,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1	N/A
TEST $0xf,%BL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %YMM8,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JE 45d550 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x540>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 45d550 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x540>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	viscosity_kernel.f90:53-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
89% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.50 to 19.00 cycles (1.50x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:55

Type of elements and instruction set

59 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 220 FP arithmetical operations:

88: addition or subtraction (20 inside FMA instructions)
108: multiply (20 inside FMA instructions)
20: divide
4: square root

The binary loop is loading 576 bytes (72 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.36 FP operations per loaded or stored byte.

General properties

nb instructions	122
nb uops	123
loop length	742
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	32
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.38 cycles
front end	15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	5.50	5.50	5.50	5.50	19.00	19.00	19.00	19.00	1.00	1.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	5.50	5.50	5.50	5.50	19.00	19.00	19.00	19.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	28.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	15.38
Dispatch	19.00
DIV/SQRT	28.50
Data deps.	1.00
Overall L1	28.50

Vectorization ratios

INT

all	81%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	97%
load	84%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	92%

INT+FP

all	95%
load	85%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

Vector efficiency ratios

INT

all	43%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	48%
load	44%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	45%

INT+FP

all	47%
load	44%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	45%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

7% of peak load performance is reached (20.21 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45d6b9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VCMPPD $0x1,%YMM13,%YMM22,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD 0xb6220(%RIP),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBLENDMPD %YMM8,%YMM18,%YMM31{%K3}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VBROADCASTSD 0x98bb0(%RIP),%YMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VANDPD %YMM29,%YMM22,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMAXPD %YMM1,%YMM14,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM31,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM13,%YMM1,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM8,%YMM18,%YMM25{%K3}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM29,%YMM21,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMAXPD %YMM13,%YMM14,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM25,%YMM13,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM1,%YMM1,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM13,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VSQRTPD %YMM20,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (50.0%)
VMULPD %YMM2,%YMM23,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VANDPD %YMM29,%YMM1,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM24,%YMM23,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM13,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VANDPD %YMM29,%YMM1,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM21,%YMM22,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM22,%YMM21,%YMM30{%K3}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM30,%YMM30,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM10,%YMM10,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%RCX,%R13,8),%YMM2{%K2}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM29,%YMM29,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM2,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM1,%YMM10,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPBROADCASTQ %R13,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ 0x99967(%RIP),%YMM2,%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VPBLENDMQ %YMM5,%YMM2,%YMM5{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM4,%YMM31{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM9,%YMM2,%YMM9{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM17,%YMM25{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM6,%YMM2,%YMM6{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM16,%YMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM3,%YMM2,%YMM3{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM15,%YMM22{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM11,%YMM2,%YMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM19,%YMM21{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM12,%YMM2,%YMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM0,%YMM30{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA64 %YMM7,%YMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM27,%YMM29{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM28,%YMM1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVUPD %YMM1,(%R12,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x4,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQA %YMM2,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM29,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM30,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM21,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM22,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM23,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM25,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM31,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
CMP %RDI,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVAPD %YMM14,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
JAE 45d850 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x840>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD -0x8(%R10,%R13,8),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R10,%R13,8),%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x8(%R14,%R13,8),%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R14,%R13,8),%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM21,%YMM23,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM22,%YMM10,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD -0x8(%RDX,%R13,8),%YMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RDX,%R13,8),%YMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM25,%YMM2,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD -0x8(%RSI,%R13,8),%YMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%R13,8),%YMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM29,%YMM30,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM20,%YMM31,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV 0x158(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD -0x8(%RCX,%R13,8),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM25,%YMM2,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM1,%YMM24,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM10,%YMM21,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM10,%YMM23,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM22,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VBROADCASTSD 0x9980b(%RIP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %YMM14,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM31,%YMM29,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM21,%YMM30,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM20,%YMM21,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM14,%YMM20,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM2,%YMM18,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM23,%YMM20,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RAX,%R13,8),%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM10,%YMM26,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSUBPD -0x10(%RAX,%R13,8),%YMM21,%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD (%RCX,%R13,8),%YMM2,%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD %YMM21,%YMM10,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMOVUPD (%R15,%R13,8),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD (%R11,%R13,8),%YMM10,%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD 0x180(%RSP),%YMM10,%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM22,%YMM22,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM21,%YMM21,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM14,%YMM25,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM23,%YMM25,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM10,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM1,%YMM14,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM29,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM20,%YMM22,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM23,%YMM21,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM1,%YMM26,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM10,%YMM29,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMAXPD %YMM8,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD %YMM1,%YMM20,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VCMPPD $0x1,%YMM10,%YMM28,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x2,%YMM13,%YMM28,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM13,%YMM28,%K1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KORW %K1,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KNOTW %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVD %K2,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1	N/A
TEST $0xf,%BL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %YMM8,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JE 45d550 <viscosity_kernel_module_mp_viscosity_kernel_.DIR.OMP.PARALLEL.2+0x540>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios