OV - exec - Loop 79

	Loop Id: 79	Module: exec	Source: advec_cell_kernel.f90:204-248 [...]	Coverage: 3.33%

0x419810 VMOVUPD	(%R9,%R10,8),%YMM5    [11]

0x419816 VCMPPD	$0x1,%YMM5,%YMM12,%K1

0x41981d VPBLENDMD	%XMM30,%XMM31,%XMM10{%K1}

0x419823 VPMOVSXDQ	%XMM10,%YMM10

0x419828 VPSUBQ	%YMM1,%YMM10,%YMM10

0x41982c VPMULLQ	%YMM10,%YMM2,%YMM11

0x419832 VPBROADCASTQ	%R10,%YMM18

0x419838 VPADDQ	%YMM18,%YMM15,%YMM18

0x41983e VPSUBQ	%YMM4,%YMM18,%YMM18

0x419844 VPSLLQ	$0x3,%YMM18,%YMM18

0x41984b VPADDQ	%YMM18,%YMM0,%YMM19

0x419851 VPADDQ	%YMM11,%YMM19,%YMM19

0x419857 VPXOR	%XMM11,%XMM11,%XMM11

0x41985c KXNORW	%K0,%K0,%K2

0x419860 VGATHERQPD	(,%YMM19,1),%YMM11{%K2}    [6]

0x41986b VPBLENDMD	%XMM30,%XMM27,%XMM19{%K1}

0x419871 VPMOVSXDQ	%XMM19,%YMM19

0x419877 VPSUBQ	%YMM1,%YMM19,%YMM19

0x41987d VXORPD	%XMM21,%XMM21,%XMM21

0x419883 KXNORW	%K0,%K0,%K2

0x419887 VGATHERQPD	(%R15,%YMM19,8),%YMM21{%K2}    [9]

0x41988e VPBLENDMD	%XMM9,%XMM27,%XMM19{%K1}

0x419894 VPBLENDMD	%XMM31,%XMM30,%XMM22{%K1}

0x41989a VPMULLQ	%YMM10,%YMM8,%YMM24

0x4198a0 VMOVDQA64	%YMM25,%YMM14

0x4198a6 VANDPD	%YMM13,%YMM5,%YMM25

0x4198ac VDIVPD	%YMM11,%YMM25,%YMM25

0x4198b2 VXORPD	%XMM3,%XMM3,%XMM3

0x4198b6 VMOVAPD	%YMM28,%YMM12

0x4198bc VMOVAPD	%YMM16,%YMM29

0x4198c2 VMOVAPD	%YMM26,%YMM16

0x4198c8 VPADDQ	%YMM18,%YMM6,%YMM26

0x4198ce VPADDQ	%YMM24,%YMM26,%YMM24

0x4198d4 VXORPD	%XMM23,%XMM23,%XMM23

0x4198da KXNORW	%K0,%K0,%K1

0x4198de VGATHERQPD	(,%YMM24,1),%YMM23{%K1}    [3]

0x4198e9 VPMOVSXDQ	%XMM19,%YMM19

0x4198ef VPSUBQ	%YMM1,%YMM19,%YMM19

0x4198f5 VPMULLQ	%YMM19,%YMM8,%YMM24

0x4198fb VPADDQ	%YMM24,%YMM26,%YMM24

0x419901 VMOVDQA	%XMM9,%XMM7

0x419905 VMOVDQA	%YMM6,%YMM9

0x419909 VMOVDQA	%YMM4,%YMM6

0x41990d VMOVDQA	%YMM15,%YMM4

0x419911 VPXOR	%XMM15,%XMM15,%XMM15

0x419916 KXNORW	%K0,%K0,%K1

0x41991a VGATHERQPD	(,%YMM24,1),%YMM15{%K1}    [2]

0x419925 VFMADD213PD	%YMM28,%YMM25,%YMM28

0x41992b VDIVPD	%YMM21,%YMM28,%YMM21

0x419931 VBROADCASTSD	0xddac5(%RIP),%YMM24    [8]

0x41993b VSUBPD	%YMM25,%YMM24,%YMM24

0x419941 VSUBPD	%YMM15,%YMM23,%YMM15

0x419947 VPMOVSXDQ	%XMM22,%YMM22

0x41994d VPSUBQ	%YMM1,%YMM22,%YMM22

0x419953 VPMULLQ	%YMM22,%YMM8,%YMM28

0x419959 VPADDQ	%YMM28,%YMM26,%YMM26

0x41995f VPXORD	%XMM28,%XMM28,%XMM28

0x419965 KXNORW	%K0,%K0,%K1

0x419969 VGATHERQPD	(,%YMM26,1),%YMM28{%K1}    [5]

0x419974 VSUBPD	%YMM23,%YMM28,%YMM26

0x41997a VMULPD	%YMM15,%YMM26,%YMM28

0x419980 VCMPPD	$0x1,%YMM28,%YMM3,%K1

0x419987 VANDPD	%YMM13,%YMM15,%YMM15

0x41998c VANDPD	%YMM13,%YMM26,%YMM28

0x419992 VMOVDQA	%YMM2,%YMM3

0x419996 VMOVDQA	%YMM0,%YMM2

0x41999a VMULPD	%YMM21,%YMM15,%YMM0

0x4199a0 VFMADD231PD	%YMM24,%YMM28,%YMM0

0x4199a6 VMULPD	%YMM20,%YMM0,%YMM0

0x4199ac VCMPPD	$0x2,%YMM0,%YMM28,%K2

0x4199b3 VMOVAPD	%YMM28,%YMM0{%K2}

0x4199b9 VMOVAPD	%YMM12,%YMM28

0x4199bf VXORPD	%XMM12,%XMM12,%XMM12

0x4199c4 VCMPPD	$0x2,%YMM12,%YMM26,%K2

0x4199cb VMOVAPD	%YMM16,%YMM26

0x4199d1 VMOVAPD	%YMM29,%YMM16

0x4199d7 VSUBPD	%YMM25,%YMM26,%YMM25

0x4199dd VXORPD	%YMM29,%YMM25,%YMM25{%K2}

0x4199e3 VCMPPD	$0x2,%YMM0,%YMM15,%K2

0x4199ea VMOVAPD	%YMM15,%YMM0{%K2}

0x4199f0 VMOVAPD	%YMM23,%YMM15

0x4199f6 VFMADD231PD	%YMM25,%YMM0,%YMM15{%K1}

0x4199fc VMOVDQA64	%YMM14,%YMM25

0x419a02 VMULPD	%YMM5,%YMM15,%YMM0

0x419a06 VMOVUPD	%YMM0,(%RDI,%R10,8)    [7]

0x419a0c VPMULLQ	%YMM10,%YMM17,%YMM5

0x419a12 VPADDQ	%YMM18,%YMM14,%YMM10

0x419a18 VPADDQ	%YMM5,%YMM10,%YMM5

0x419a1c VXORPD	%XMM15,%XMM15,%XMM15

0x419a21 KXNORW	%K0,%K0,%K1

0x419a25 VGATHERQPD	(,%YMM5,1),%YMM15{%K1}    [12]

0x419a30 VPMULLQ	%YMM19,%YMM17,%YMM5

0x419a36 VPADDQ	%YMM5,%YMM10,%YMM5

0x419a3a VPXORD	%XMM18,%XMM18,%XMM18

0x419a40 KXNORW	%K0,%K0,%K1

0x419a44 VGATHERQPD	(,%YMM5,1),%YMM18{%K1}    [4]

0x419a4f VMULPD	%YMM11,%YMM23,%YMM5

0x419a55 VPMULLQ	%YMM22,%YMM17,%YMM11

0x419a5b VPADDQ	%YMM11,%YMM10,%YMM10

0x419a60 VPXOR	%XMM11,%XMM11,%XMM11

0x419a65 KXNORW	%K0,%K0,%K1

0x419a69 VGATHERQPD	(,%YMM10,1),%YMM11{%K1}    [1]

0x419a74 VSUBPD	%YMM18,%YMM15,%YMM10

0x419a7a VSUBPD	%YMM15,%YMM11,%YMM11

0x419a7f VMULPD	%YMM10,%YMM11,%YMM18

0x419a85 VCMPPD	$0x1,%YMM18,%YMM12,%K1

0x419a8c VANDPD	%YMM13,%YMM0,%YMM18

0x419a92 VDIVPD	%YMM5,%YMM18,%YMM5

0x419a98 VANDPD	%YMM13,%YMM10,%YMM10

0x419a9d VANDPD	%YMM13,%YMM11,%YMM18

0x419aa3 VMULPD	%YMM21,%YMM10,%YMM19

0x419aa9 VFMADD231PD	%YMM24,%YMM18,%YMM19

0x419aaf VMULPD	%YMM20,%YMM19,%YMM19

0x419ab5 VCMPPD	$0x2,%YMM19,%YMM18,%K2

0x419abc VMOVAPD	%YMM18,%YMM19{%K2}

0x419ac2 VCMPPD	$0x2,%YMM19,%YMM10,%K2

0x419ac9 VMOVAPD	%YMM10,%YMM19{%K2}

0x419acf VCMPPD	$0x2,%YMM12,%YMM11,%K2

0x419ad6 VSUBPD	%YMM5,%YMM26,%YMM5

0x419adc VXORPD	%YMM29,%YMM5,%YMM5{%K2}

0x419ae2 VFMADD231PD	%YMM5,%YMM19,%YMM15{%K1}

0x419ae8 VMULPD	%YMM0,%YMM15,%YMM0

0x419aec VMOVDQA	%YMM4,%YMM15

0x419af0 VMOVDQA	%YMM6,%YMM4

0x419af4 VMOVDQA	%YMM9,%YMM6

0x419af8 VMOVDQA	%XMM7,%XMM9

0x419afc VMOVUPD	%YMM0,(%RCX,%R10,8)    [10]

0x419b02 VMOVDQA	%YMM2,%YMM0

0x419b06 VMOVDQA	%YMM3,%YMM2

0x419b0a ADD	$0x4,%R10

0x419b0e CMP	%RDX,%R10

0x419b11 JBE	419810

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 204 - 248

--------------------------------------------------------------------------------

204:           IF(vol_flux_y(j,k).GT.0.0)THEN

[...]

216:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

217:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

218:           sigma4=2.0_8-sigmat

219:

220:           sigma=sigmat

221:           sigmav=sigmat

222:

223:           diffuw=density1(j,donor)-density1(j,upwind)

224:           diffdw=density1(j,downwind)-density1(j,donor)

225:           wind=1.0_8

226:           IF(diffdw.LE.0.0) wind=-1.0_8

227:           IF(diffuw*diffdw.GT.0.0)THEN

228:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

229:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

230:           ELSE

231:             limiter=0.0

232:           ENDIF

233:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

234:

235:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

236:           diffuw=energy1(j,donor)-energy1(j,upwind)

237:           diffdw=energy1(j,downwind)-energy1(j,donor)

238:           wind=1.0_8

239:           IF(diffdw.LE.0.0) wind=-1.0_8

240:           IF(diffuw*diffdw.GT.0.0)THEN

241:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

242:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

243:           ELSE

244:             limiter=0.0

245:           ENDIF

246:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

247:

248:         ENDDO

Coverage (%)	Name	Source Location	Module
►50.60+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►36.85+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►5.69+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
►2.40+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
►2.08+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	advec_cell_kernel	advec_cell_kernel.f90:270	exec
○	advec_cell_driver	advec_cell_driver.f90:36	exec
○	advection	advection.f90:90	exec
○	hydro	hydro.f90:64	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	advec_cell_kernel	advec_cell_kernel.f90:270	exec
○	advec_cell_driver	advec_cell_driver.f90:36	exec
○	advection	advection.f90:59	exec
○	hydro	hydro.f90:64	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.45
CQA speedup if fully vectorized	3.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	micro-operation queue,
Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source	advec_cell_kernel.f90:204-204,advec_cell_kernel.f90:216-248
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	39.50
CQA cycles if no scalar integer	38.50
CQA cycles if FP arith vectorized	27.23
CQA cycles if fully vectorized	13.09
Front-end cycles	39.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	31.00
P11 cycles	31.00
P12 cycles	31.00
P13 cycles	31.00
P14 cycles	25.00
P15 cycles	25.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	132.00
Nb uops	316.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.94
Nb FLOP add-sub	28.00
Nb FLOP mul	36.00
Nb FLOP fma	20.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.11
Bytes prefetched	0.00
Bytes loaded	296.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	8.00
Vectorization ratio all	98.35
Vectorization ratio load	90.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	97.18
Vector-efficiency ratio all	45.25
Vector-efficiency ratio load	46.25
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	41.90

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.45
CQA speedup if fully vectorized	3.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	micro-operation queue,
Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source	advec_cell_kernel.f90:204-204,advec_cell_kernel.f90:216-248
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	39.50
CQA cycles if no scalar integer	38.50
CQA cycles if FP arith vectorized	27.23
CQA cycles if fully vectorized	13.09
Front-end cycles	39.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	31.00
P11 cycles	31.00
P12 cycles	31.00
P13 cycles	31.00
P14 cycles	25.00
P15 cycles	25.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	132.00
Nb uops	316.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.94
Nb FLOP add-sub	28.00
Nb FLOP mul	36.00
Nb FLOP fma	20.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.11
Bytes prefetched	0.00
Bytes loaded	296.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	8.00
Vectorization ratio all	98.35
Vectorization ratio load	90.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	97.18
Vector-efficiency ratio all	45.25
Vector-efficiency ratio load	46.25
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	41.90

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	advec_cell_kernel.f90:204-248
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:204,216-248.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 45% of vector register length is used (average across all SSE/AVX instructions).

Details

98% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

90% of SSE/AVX loads are used in vector version.
97% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:216
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:217
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:223
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:223
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:224
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:236
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:236
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:237
VPBROADCASTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:204

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:216
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:217
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:223
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:223
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:224
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:236
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:236
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:237

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

33 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

48: addition or subtraction (20 inside FMA instructions)
56: multiply (20 inside FMA instructions)
12: divide

The binary loop is loading 296 bytes (37 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	132
nb uops	316
loop length	775
used x86 registers	6
used mmx registers	0
used xmm registers	16
used ymm registers	28
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.78

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	39.50 cycles
front end	39.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	31.00	31.00	31.00	31.00	25.00	25.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	31.00	31.00	31.00	31.00	25.00	25.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	12.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	39.50
Dispatch	31.00
DIV/SQRT	12.00
Data deps.	1.00
Overall L1	39.50

Vectorization ratios

INT

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	96%

all	98%
load	90%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	97%

INT+FP

all	98%
load	90%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	97%

Vector efficiency ratios

INT

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	47%
load	46%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	46%

INT+FP

all	45%
load	46%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	41%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 39.50 cycles. At this rate:

2% of peak load performance is reached (7.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 39.50 to 31.00 cycles (1.27x speedup).

ASM code

In the binary file, the address of the loop is: 419810

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R9,%R10,8),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM5,%YMM12,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPBLENDMD %XMM30,%XMM31,%XMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBQ %YMM1,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMULLQ %YMM10,%YMM2,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPBROADCASTQ %R10,%YMM18	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ %YMM18,%YMM15,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSUBQ %YMM4,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSLLQ $0x3,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (50.0%)
VPADDQ %YMM18,%YMM0,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM11,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPXOR %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KXNORW %K0,%K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM19,1),%YMM11{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VPBLENDMD %XMM30,%XMM27,%XMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBQ %YMM1,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM19,8),%YMM21{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VPBLENDMD %XMM9,%XMM27,%XMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPBLENDMD %XMM31,%XMM30,%XMM22{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMULLQ %YMM10,%YMM8,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM25,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VANDPD %YMM13,%YMM5,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VDIVPD %YMM11,%YMM25,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %YMM28,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM16,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM26,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPADDQ %YMM18,%YMM6,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM24,%YMM26,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM24,1),%YMM23{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VPMOVSXDQ %XMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBQ %YMM1,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMULLQ %YMM19,%YMM8,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM24,%YMM26,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQA %XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA %YMM6,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM4,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM15,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPXOR %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM24,1),%YMM15{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD213PD %YMM28,%YMM25,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM21,%YMM28,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VBROADCASTSD 0xddac5(%RIP),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBPD %YMM25,%YMM24,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM15,%YMM23,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VPMOVSXDQ %XMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBQ %YMM1,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMULLQ %YMM22,%YMM8,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM28,%YMM26,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPXORD %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM26,1),%YMM28{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VSUBPD %YMM23,%YMM28,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM15,%YMM26,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM28,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM13,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM13,%YMM26,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQA %YMM2,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM0,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMULPD %YMM21,%YMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM28,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM20,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x2,%YMM0,%YMM28,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM28,%YMM0{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM12,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VXORPD %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPPD $0x2,%YMM12,%YMM26,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM16,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM29,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VSUBPD %YMM25,%YMM26,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VXORPD %YMM29,%YMM25,%YMM25{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM0,%YMM15,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM15,%YMM0{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM23,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD231PD %YMM25,%YMM0,%YMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA64 %YMM14,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMULPD %YMM5,%YMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM0,(%RDI,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPMULLQ %YMM10,%YMM17,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM18,%YMM14,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM5,%YMM10,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM5,1),%YMM15{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VPMULLQ %YMM19,%YMM17,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM5,%YMM10,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPXORD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM5,1),%YMM18{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VMULPD %YMM11,%YMM23,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM22,%YMM17,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM11,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPXOR %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM10,1),%YMM11{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VSUBPD %YMM18,%YMM15,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM15,%YMM11,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM10,%YMM11,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM18,%YMM12,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM13,%YMM0,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VDIVPD %YMM5,%YMM18,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VANDPD %YMM13,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM13,%YMM11,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM21,%YMM10,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM18,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM20,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x2,%YMM19,%YMM18,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM18,%YMM19{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM19,%YMM10,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM10,%YMM19{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM12,%YMM11,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM26,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VXORPD %YMM29,%YMM5,%YMM5{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VFMADD231PD %YMM5,%YMM19,%YMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM0,%YMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA %YMM4,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM9,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %XMM7,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVUPD %YMM0,(%RCX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQA %YMM2,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
ADD $0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JBE 419810 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0x22d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	advec_cell_kernel.f90:204-248
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 45% of vector register length is used (average across all SSE/AVX instructions).

Details

98% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

90% of SSE/AVX loads are used in vector version.
97% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:216
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:217
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:223
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:223
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:224
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:236
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:236
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:237
VPBROADCASTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:204

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:216
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:217
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:223
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:223
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:224
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:236
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:236
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:237

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

33 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

48: addition or subtraction (20 inside FMA instructions)
56: multiply (20 inside FMA instructions)
12: divide

The binary loop is loading 296 bytes (37 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	132
nb uops	316
loop length	775
used x86 registers	6
used mmx registers	0
used xmm registers	16
used ymm registers	28
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.78

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	39.50 cycles
front end	39.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	31.00	31.00	31.00	31.00	25.00	25.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	31.00	31.00	31.00	31.00	25.00	25.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	12.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	39.50
Dispatch	31.00
DIV/SQRT	12.00
Data deps.	1.00
Overall L1	39.50

Vectorization ratios

INT

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	96%

all	98%
load	90%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	97%

INT+FP

all	98%
load	90%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	97%

Vector efficiency ratios

INT

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	47%
load	46%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	46%

INT+FP

all	45%
load	46%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	41%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 39.50 cycles. At this rate:

2% of peak load performance is reached (7.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 419810

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R9,%R10,8),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM5,%YMM12,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPBLENDMD %XMM30,%XMM31,%XMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBQ %YMM1,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMULLQ %YMM10,%YMM2,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPBROADCASTQ %R10,%YMM18	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ %YMM18,%YMM15,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSUBQ %YMM4,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSLLQ $0x3,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (50.0%)
VPADDQ %YMM18,%YMM0,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM11,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPXOR %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KXNORW %K0,%K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM19,1),%YMM11{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VPBLENDMD %XMM30,%XMM27,%XMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBQ %YMM1,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%R15,%YMM19,8),%YMM21{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VPBLENDMD %XMM9,%XMM27,%XMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPBLENDMD %XMM31,%XMM30,%XMM22{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMULLQ %YMM10,%YMM8,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 %YMM25,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VANDPD %YMM13,%YMM5,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VDIVPD %YMM11,%YMM25,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %YMM28,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM16,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM26,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPADDQ %YMM18,%YMM6,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM24,%YMM26,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM24,1),%YMM23{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VPMOVSXDQ %XMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBQ %YMM1,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMULLQ %YMM19,%YMM8,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM24,%YMM26,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQA %XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA %YMM6,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM4,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM15,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPXOR %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM24,1),%YMM15{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VFMADD213PD %YMM28,%YMM25,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM21,%YMM28,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VBROADCASTSD 0xddac5(%RIP),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBPD %YMM25,%YMM24,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM15,%YMM23,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VPMOVSXDQ %XMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBQ %YMM1,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMULLQ %YMM22,%YMM8,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM28,%YMM26,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPXORD %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM26,1),%YMM28{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VSUBPD %YMM23,%YMM28,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM15,%YMM26,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM28,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM13,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM13,%YMM26,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQA %YMM2,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM0,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMULPD %YMM21,%YMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM28,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM20,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x2,%YMM0,%YMM28,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM28,%YMM0{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM12,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VXORPD %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPPD $0x2,%YMM12,%YMM26,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM16,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM29,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VSUBPD %YMM25,%YMM26,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VXORPD %YMM29,%YMM25,%YMM25{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM0,%YMM15,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM15,%YMM0{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM23,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD231PD %YMM25,%YMM0,%YMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVDQA64 %YMM14,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMULPD %YMM5,%YMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM0,(%RDI,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPMULLQ %YMM10,%YMM17,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM18,%YMM14,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM5,%YMM10,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM5,1),%YMM15{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VPMULLQ %YMM19,%YMM17,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM5,%YMM10,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPXORD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM5,1),%YMM18{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VMULPD %YMM11,%YMM23,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM22,%YMM17,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM11,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPXOR %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (,%YMM10,1),%YMM11{%K1}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VSUBPD %YMM18,%YMM15,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM15,%YMM11,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM10,%YMM11,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM18,%YMM12,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VANDPD %YMM13,%YMM0,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VDIVPD %YMM5,%YMM18,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VANDPD %YMM13,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM13,%YMM11,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM21,%YMM10,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM24,%YMM18,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM20,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x2,%YMM19,%YMM18,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM18,%YMM19{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM19,%YMM10,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM10,%YMM19{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM12,%YMM11,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM26,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VXORPD %YMM29,%YMM5,%YMM5{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VFMADD231PD %YMM5,%YMM19,%YMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM0,%YMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA %YMM4,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM9,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %XMM7,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVUPD %YMM0,(%RCX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQA %YMM2,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA %YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
ADD $0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JBE 419810 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0x22d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code