OV - exec - Loop 57

	Loop Id: 57	Module: exec	Source: PdV_kernel.f90:111-135 [...]	Coverage: 6.32%

0x413cf0 VMOVUPD	-0x8(%R9,%RBX,8),%YMM3    [9]

0x413cf7 VMOVUPD	(%R9,%RBX,8),%YMM4    [9]

0x413cfd VADDPD	-0x8(%R11,%RBX,8),%YMM3,%YMM3    [3]

0x413d04 VADDPD	-0x8(%RCX,%RBX,8),%YMM3,%YMM3    [1]

0x413d0a VADDPD	-0x8(%R15,%RBX,8),%YMM3,%YMM3    [6]

0x413d11 VMULPD	-0x8(%R12,%RBX,8),%YMM2,%YMM5    [4]

0x413d18 VADDPD	(%R11,%RBX,8),%YMM4,%YMM4    [3]

0x413d1e VADDPD	(%RCX,%RBX,8),%YMM4,%YMM4    [1]

0x413d23 VADDPD	(%R15,%RBX,8),%YMM4,%YMM4    [6]

0x413d29 VMULPD	(%R12,%RBX,8),%YMM2,%YMM6    [4]

0x413d2f VMOVUPD	(%RSI,%RBX,8),%YMM7    [19]

0x413d34 VADDPD	-0x8(%RSI,%RBX,8),%YMM7,%YMM7    [19]

0x413d3a VADDPD	-0x8(%RAX,%RBX,8),%YMM7,%YMM7    [12]

0x413d40 VADDPD	(%RAX,%RBX,8),%YMM7,%YMM7    [12]

0x413d45 VMULPD	(%R8,%RBX,8),%YMM2,%YMM8    [8]

0x413d4b VMULPD	%YMM7,%YMM8,%YMM7

0x413d4f VFMADD231PD	%YMM5,%YMM3,%YMM7

0x413d54 VFNMADD231PD	%YMM6,%YMM4,%YMM7

0x413d59 VMOVUPD	(%R10,%RBX,8),%YMM3    [2]

0x413d5f VADDPD	-0x8(%R10,%RBX,8),%YMM3,%YMM3    [2]

0x413d66 VADDPD	-0x8(%RDI,%RBX,8),%YMM3,%YMM3    [7]

0x413d6c VADDPD	(%RDI,%RBX,8),%YMM3,%YMM3    [7]

0x413d71 VMULPD	(%RDX,%RBX,8),%YMM2,%YMM4    [11]

0x413d76 VMOVUPD	(%R13,%RBX,8),%YMM5    [5]

0x413d7d MOV	-0x58(%RBP),%R14    [10]

0x413d81 VMOVUPD	(%R14,%RBX,8),%YMM6    [18]

0x413d87 VFMSUB213PD	%YMM7,%YMM3,%YMM4

0x413d8c MOV	-0x60(%RBP),%R14    [10]

0x413d90 VADDPD	(%R14,%RBX,8),%YMM6,%YMM3    [17]

0x413d96 VMULPD	%YMM3,%YMM4,%YMM3

0x413d9a MOV	-0x48(%RBP),%R14    [10]

0x413d9e VMULPD	(%R14,%RBX,8),%YMM5,%YMM6    [16]

0x413da4 VDIVPD	%YMM6,%YMM3,%YMM3

0x413da8 MOV	-0x30(%RBP),%R14    [10]

0x413dac VMOVUPD	(%R14,%RBX,8),%YMM7    [15]

0x413db2 VSUBPD	%YMM3,%YMM7,%YMM3

0x413db6 MOV	-0x38(%RBP),%R14    [10]

0x413dba VMOVUPD	%YMM3,(%R14,%RBX,8)    [14]

0x413dc0 VADDPD	%YMM5,%YMM4,%YMM3

0x413dc4 VDIVPD	%YMM3,%YMM6,%YMM3

0x413dc8 MOV	-0x68(%RBP),%R14    [10]

0x413dcc VMOVUPD	%YMM3,(%R14,%RBX,8)    [13]

0x413dd2 ADD	$0x4,%RBX

0x413dd6 CMP	-0xb0(%RBP),%RBX    [10]

0x413ddd JB	413cf0

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 111 - 135

--------------------------------------------------------------------------------

111:         DO j=x_min,x_max

112:

113:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

Coverage (%)	Name	Source Location	Module
►50.88+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►36.66+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►5.67+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
►4.14+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	pdv_kernel	PdV_kernel.f90:145	exec
○	pdv	PdV.f90:61	exec
○	hydro	hydro.f90:60	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.35+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.11
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7, P8, P9,
Function	pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2
Source	PdV_kernel.f90:111-123,PdV_kernel.f90:131-135
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	8.50
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	7.63
CQA cycles if fully vectorized	4.25
Front-end cycles	5.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	8.50
P7 cycles	8.50
P8 cycles	8.50
P9 cycles	8.50
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	8.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	44.00
Nb loads	32.00
Nb stores	2.00
Nb stack references	7.00
FLOP/cycle	14.12
Nb FLOP add-sub	60.00
Nb FLOP mul	28.00
Nb FLOP fma	12.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	108.24
Bytes prefetched	0.00
Bytes loaded	856.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.11
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7, P8, P9,
Function	pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2
Source	PdV_kernel.f90:111-123,PdV_kernel.f90:131-135
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	8.50
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	7.63
CQA cycles if fully vectorized	4.25
Front-end cycles	5.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	8.50
P7 cycles	8.50
P8 cycles	8.50
P9 cycles	8.50
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	8.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	44.00
Nb loads	32.00
Nb stores	2.00
Nb stack references	7.00
FLOP/cycle	14.12
Nb FLOP add-sub	60.00
Nb FLOP mul	28.00
Nb FLOP fma	12.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	108.24
Bytes prefetched	0.00
Bytes loaded	856.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	PdV_kernel.f90:111-135
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:111-123,131-135.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 8.00 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

27 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
40: multiply (12 inside FMA instructions)
8: divide

The binary loop is loading 856 bytes (107 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	45
nb uops	44
loop length	243
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	7
used zmm registers	0
nb stack references	7
ADD-SUB / MUL ratio	2.14

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	8.50	8.50	8.50	8.50	6.00	6.00	7.50	7.50	1.00	1.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	8.50	8.50	8.50	8.50	6.00	6.00	7.50	7.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.50
Dispatch	8.50
DIV/SQRT	8.00
Data deps.	1.00
Overall L1	8.50

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

39% of peak load performance is reached (100.71 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 413cf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD -0x8(%R9,%RBX,8),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R9,%RBX,8),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%R11,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD -0x8(%RCX,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD -0x8(%R15,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD -0x8(%R12,%RBX,8),%YMM2,%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD (%R11,%RBX,8),%YMM4,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD (%RCX,%RBX,8),%YMM4,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD (%R15,%RBX,8),%YMM4,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R12,%RBX,8),%YMM2,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%RBX,8),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%RSI,%RBX,8),%YMM7,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD -0x8(%RAX,%RBX,8),%YMM7,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD (%RAX,%RBX,8),%YMM7,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R8,%RBX,8),%YMM2,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM7,%YMM8,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM5,%YMM3,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFNMADD231PD %YMM6,%YMM4,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD (%R10,%RBX,8),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%R10,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD -0x8(%RDI,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD (%RDI,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%RDX,%RBX,8),%YMM2,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R13,%RBX,8),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
MOV -0x58(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD (%R14,%RBX,8),%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMSUB213PD %YMM7,%YMM3,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
MOV -0x60(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD (%R14,%RBX,8),%YMM6,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM3,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
MOV -0x48(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULPD (%R14,%RBX,8),%YMM5,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM6,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
MOV -0x30(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD (%R14,%RBX,8),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM7,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV -0x38(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD %YMM3,(%R14,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VADDPD %YMM5,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD %YMM3,%YMM6,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
MOV -0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD %YMM3,(%R14,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0xb0(%RBP),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JB 413cf0 <pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2+0x860>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	PdV_kernel.f90:111-135
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 8.00 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Type of elements and instruction set

27 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
40: multiply (12 inside FMA instructions)
8: divide

The binary loop is loading 856 bytes (107 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	45
nb uops	44
loop length	243
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	7
used zmm registers	0
nb stack references	7
ADD-SUB / MUL ratio	2.14

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	8.50	8.50	8.50	8.50	6.00	6.00	7.50	7.50	1.00	1.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	8.50	8.50	8.50	8.50	6.00	6.00	7.50	7.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.50
Dispatch	8.50
DIV/SQRT	8.00
Data deps.	1.00
Overall L1	8.50

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

39% of peak load performance is reached (100.71 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 413cf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD -0x8(%R9,%RBX,8),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R9,%RBX,8),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%R11,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD -0x8(%RCX,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD -0x8(%R15,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD -0x8(%R12,%RBX,8),%YMM2,%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD (%R11,%RBX,8),%YMM4,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD (%RCX,%RBX,8),%YMM4,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD (%R15,%RBX,8),%YMM4,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R12,%RBX,8),%YMM2,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%RBX,8),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%RSI,%RBX,8),%YMM7,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD -0x8(%RAX,%RBX,8),%YMM7,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD (%RAX,%RBX,8),%YMM7,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R8,%RBX,8),%YMM2,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM7,%YMM8,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM5,%YMM3,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFNMADD231PD %YMM6,%YMM4,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD (%R10,%RBX,8),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%R10,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD -0x8(%RDI,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD (%RDI,%RBX,8),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%RDX,%RBX,8),%YMM2,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R13,%RBX,8),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
MOV -0x58(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD (%R14,%RBX,8),%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMSUB213PD %YMM7,%YMM3,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
MOV -0x60(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD (%R14,%RBX,8),%YMM6,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM3,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
MOV -0x48(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULPD (%R14,%RBX,8),%YMM5,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM6,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
MOV -0x30(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD (%R14,%RBX,8),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM7,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV -0x38(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD %YMM3,(%R14,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VADDPD %YMM5,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD %YMM3,%YMM6,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
MOV -0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD %YMM3,(%R14,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0xb0(%RBP),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JB 413cf0 <pdv_kernel_module_mp_pdv_kernel_.DIR.OMP.PARALLEL.2+0x860>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code