OV - exec - Loop 193

	Loop Id: 193	Module: exec	Source: generate_chunk_kernel.f90:87-163 [...]	Coverage: 0.01%

0x428750 MOV	-0x58(%RBP),%R8D

0x428754 INC	%R8D

0x428757 MOV	-0xd8(%RBP),%R10

0x42875e INC	%R10

0x428761 MOV	-0x60(%RBP),%RCX

0x428765 INC	%RCX

0x428768 CMP	-0x188(%RBP),%R10

0x42876f MOV	-0xf4(%RBP),%EDX

0x428775 JE	4286a0

0x42877b MOVSXD	%R8D,%RDI

0x42877e LEA	(,%RDI,8),%R9

0x428786 CMP	%RDI,%RCX

0x428789 MOV	%RDI,%RSI

0x42878c CMOVG	%RCX,%RSI

0x428790 SUB	%RDI,%RSI

0x428793 INC	%RSI

0x428796 SHR	$0x3,%RSI

0x42879a NEG	%RSI

0x42879d MOV	-0x180(%RBP),%RAX

0x4287a4 LEA	(%R10,%RAX,1),%R11

0x4287a8 CMP	-0xf0(%RBP),%EDX

0x4287ae MOV	%RCX,-0x60(%RBP)

0x4287b2 MOV	%R8D,-0x58(%RBP)

0x4287b6 MOV	%R10,-0xd8(%RBP)

0x4287bd JNE	428960

0x4287c3 LEA	0x1(%R11),%RAX

0x4287c7 MOV	%RAX,%R12

0x4287ca SUB	-0x50(%RBP),%RAX

0x4287ce MOV	0xb8(%RBP),%RCX

0x4287d5 VMOVSD	(%RCX,%RAX,8),%XMM0

0x4287da MOV	0x50(%RBP),%RAX

0x4287de MOV	-0x40(%RBP),%RCX

0x4287e2 VUCOMISD	-0x8(%RAX,%RCX,8),%XMM0

0x4287e8 JB	428750

0x4287ee MOV	%R11,%RDX

0x4287f1 SUB	-0x50(%RBP),%RDX

0x4287f5 MOV	0x48(%RBP),%RAX

0x4287f9 MOV	-0x40(%RBP),%RCX

0x4287fd VMOVSD	-0x8(%RAX,%RCX,8),%XMM0

0x428803 MOV	0xb8(%RBP),%RAX

0x42880a VUCOMISD	(%RAX,%RDX,8),%XMM0

0x42880f JBE	428750

0x428815 MOV	0xb0(%RBP),%RAX

0x42881c MOV	-0x178(%RBP),%RCX

0x428823 VMOVSD	(%RAX,%RCX,8),%XMM0

0x428828 MOV	0x40(%RBP),%RAX

0x42882c MOV	-0x40(%RBP),%RCX

0x428830 VUCOMISD	-0x8(%RAX,%RCX,8),%XMM0

0x428836 JB	428750

0x42883c MOV	0x38(%RBP),%RAX

0x428840 MOV	-0x40(%RBP),%RCX

0x428844 VMOVSD	-0x8(%RAX,%RCX,8),%XMM0

0x42884a MOV	0xb0(%RBP),%RAX

0x428851 MOV	-0x70(%RBP),%RCX

0x428855 VUCOMISD	(%RAX,%RCX,8),%XMM0

0x42885a JBE	428750

0x428860 MOV	%RDX,%R10

0x428863 MOV	0xe0(%RBP),%RAX

0x42886a MOV	(%RAX),%RAX

0x42886d MOV	-0x70(%RBP),%R8

0x428871 IMUL	%R8,%RAX

0x428875 ADD	0x90(%RBP),%RAX

0x42887c MOV	0x68(%RBP),%RCX

0x428880 MOV	-0x40(%RBP),%RDX

0x428884 VMOVSD	-0x8(%RCX,%RDX,8),%XMM0

0x42888a VMOVSD	%XMM0,(%RAX,%R10,8)

0x428890 MOV	0xf0(%RBP),%RAX

0x428897 MOV	(%RAX),%RAX

0x42889a IMUL	%R8,%RAX

0x42889e ADD	0x98(%RBP),%RAX

0x4288a5 MOV	0x70(%RBP),%RCX

0x4288a9 VMOVSD	-0x8(%RCX,%RDX,8),%XMM0

0x4288af VMOVSD	%XMM0,(%RAX,%R10,8)

0x4288b5 MOV	0x60(%RBP),%RAX

0x4288b9 VMOVSD	-0x8(%RAX,%RDX,8),%XMM0

0x4288bf MOV	0x100(%RBP),%RAX

0x4288c6 MOV	(%RAX),%RCX

0x4288c9 MOV	0x58(%RBP),%RAX

0x4288cd VMOVSD	-0x8(%RAX,%RDX,8),%XMM1

0x4288d3 MOV	0x110(%RBP),%RAX

0x4288da MOV	(%RAX),%R10

0x4288dd CMP	%RDI,%R12

0x4288e0 CMOVLE	%RDI,%R12

0x4288e4 SUB	%RDI,%R12

0x4288e7 LEA	0x1(%R12),%R13

0x4288ec MOV	%R13,%RAX

0x4288ef AND	$-0x8,%RAX

0x4288f3 MOV	%R12,-0x90(%RBP)

0x4288fa SUB	%RAX,%R12

0x4288fd MOV	%RAX,-0x88(%RBP)

0x428904 ADD	%RAX,%RDI

0x428907 SUB	-0x50(%RBP),%RDI

0x42890b LEA	(%R14,%RDI,8),%RAX

0x42890f ADD	$0x30,%RAX

0x428913 MOV	%RAX,-0x80(%RBP)

0x428917 LEA	0x30(%R15,%RDI,8),%RAX

0x42891c MOV	%RAX,-0x78(%RBP)

0x428920 MOV	-0xd0(%RBP),%R8

0x428927 MOV	%R8,%RAX

0x42892a IMUL	%R10,%RAX

0x42892e MOV	-0xc8(%RBP),%RDX

0x428935 ADD	%R9,%RDX

0x428938 ADD	%RDX,%RAX

0x42893b MOV	%R8,%RDX

0x42893e IMUL	%RCX,%RDX

0x428942 ADD	-0xc0(%RBP),%R9

0x428949 ADD	%RDX,%R9

0x42894c XOR	%EBX,%EBX

0x42894e JMP	428b5f

0x428960 MOV	0x18(%RBP),%RAX

0x428964 CMP	(%RAX),%EDX

0x428966 JNE	428ed0

0x42896c MOV	%R11,%RAX

0x42896f SUB	-0x50(%RBP),%RAX

0x428973 MOV	0xa8(%RBP),%RCX

0x42897a VMOVSD	(%RCX,%RAX,8),%XMM0

0x42897f VSUBSD	%XMM2,%XMM0,%XMM0

0x428983 VMULSD	%XMM0,%XMM0,%XMM0

0x428987 MOV	0xa0(%RBP),%RCX

0x42898e MOV	-0x70(%RBP),%RDX

0x428992 VMOVSD	(%RCX,%RDX,8),%XMM1

0x428997 VSUBSD	%XMM3,%XMM1,%XMM1

0x42899b VFMADD213SD	%XMM0,%XMM1,%XMM1

0x4289a0 VSQRTSD	%XMM1,%XMM1,%XMM0

0x4289a4 MOV	0x30(%RBP),%RCX

0x4289a8 MOV	-0x40(%RBP),%RDX

0x4289ac VMOVSD	-0x8(%RCX,%RDX,8),%XMM1

0x4289b2 VUCOMISD	%XMM0,%XMM1

0x4289b6 JB	428750

0x4289bc MOV	%R11,%RBX

0x4289bf MOV	0xe0(%RBP),%RCX

0x4289c6 MOV	(%RCX),%RDX

0x4289c9 MOV	-0x70(%RBP),%R8

0x4289cd IMUL	%R8,%RDX

0x4289d1 ADD	0x90(%RBP),%RDX

0x4289d8 MOV	0x68(%RBP),%RCX

0x4289dc MOV	-0x40(%RBP),%R10

0x4289e0 VMOVSD	-0x8(%RCX,%R10,8),%XMM0

0x4289e7 VMOVSD	%XMM0,(%RDX,%RAX,8)

0x4289ec MOV	0xf0(%RBP),%RCX

0x4289f3 MOV	(%RCX),%RDX

0x4289f6 IMUL	%R8,%RDX

0x4289fa ADD	0x98(%RBP),%RDX

0x428a01 MOV	0x70(%RBP),%RCX

0x428a05 VMOVSD	-0x8(%RCX,%R10,8),%XMM0

0x428a0c VMOVSD	%XMM0,(%RDX,%RAX,8)

0x428a11 MOV	0x60(%RBP),%RAX

0x428a15 VMOVSD	-0x8(%RAX,%R10,8),%XMM0

0x428a1c MOV	0x100(%RBP),%RAX

0x428a23 MOV	(%RAX),%R8

0x428a26 MOV	0x58(%RBP),%RAX

0x428a2a VMOVSD	-0x8(%RAX,%R10,8),%XMM1

0x428a31 MOV	0x110(%RBP),%RAX

0x428a38 MOV	(%RAX),%R10

0x428a3b INC	%RBX

0x428a3e CMP	%RDI,%RBX

0x428a41 CMOVLE	%RDI,%RBX

0x428a45 SUB	%RDI,%RBX

0x428a48 LEA	0x1(%RBX),%R13

0x428a4c MOV	%R13,%RAX

0x428a4f AND	$-0x8,%RAX

0x428a53 MOV	%RBX,-0x90(%RBP)

0x428a5a SUB	%RAX,%RBX

0x428a5d MOV	%RAX,-0x88(%RBP)

0x428a64 ADD	%RAX,%RDI

0x428a67 SUB	-0x50(%RBP),%RDI

0x428a6b LEA	(%R14,%RDI,8),%RAX

0x428a6f ADD	$0x30,%RAX

0x428a73 MOV	%RAX,-0x80(%RBP)

0x428a77 LEA	0x30(%R15,%RDI,8),%RAX

0x428a7c MOV	%RAX,-0x78(%RBP)

0x428a80 MOV	-0xd0(%RBP),%R11

0x428a87 MOV	%R11,%RAX

0x428a8a IMUL	%R10,%RAX

0x428a8e MOV	-0xc8(%RBP),%RCX

0x428a95 ADD	%RCX,%RAX

0x428a98 ADD	%R9,%RAX

0x428a9b MOV	%R11,%RDX

0x428a9e IMUL	%R8,%RDX

0x428aa2 ADD	-0xc0(%RBP),%R9

0x428aa9 ADD	%RDX,%R9

0x428aac XOR	%EDX,%EDX

0x428aae JMP	428d62

  (198) 0x428ab3 MOV	-0x38(%RBP),%RDX

  (198) 0x428ab7 ADD	%RBX,%RDX

  (198) 0x428aba SUB	-0x30(%RBP),%RDX

  (198) 0x428abe MOV	%RCX,%R11

  (198) 0x428ac1 IMUL	%RDX,%R11

  (198) 0x428ac5 IMUL	%R10,%RDX

  (198) 0x428ac9 LEA	(%R14,%R11,1),%R8

  (198) 0x428acd VMOVSD	%XMM0,0x28(%R8,%RDI,8)

  (198) 0x428ad4 LEA	(%R15,%RDX,1),%R8

  (198) 0x428ad8 VMOVSD	%XMM1,0x28(%R8,%RDI,8)

  (198) 0x428adf LEA	(%R14,%R11,1),%R8

  (198) 0x428ae3 VMOVSD	%XMM0,0x20(%R8,%RDI,8)

  (198) 0x428aea LEA	(%R15,%RDX,1),%R8

  (198) 0x428aee VMOVSD	%XMM1,0x20(%R8,%RDI,8)

  (198) 0x428af5 LEA	(%R14,%R11,1),%R8

  (198) 0x428af9 VMOVSD	%XMM0,0x18(%R8,%RDI,8)

  (198) 0x428b00 LEA	(%R15,%RDX,1),%R8

  (198) 0x428b04 VMOVSD	%XMM1,0x18(%R8,%RDI,8)

  (198) 0x428b0b LEA	(%R14,%R11,1),%R8

  (198) 0x428b0f VMOVSD	%XMM0,0x10(%R8,%RDI,8)

  (198) 0x428b16 LEA	(%R15,%RDX,1),%R8

  (198) 0x428b1a VMOVSD	%XMM1,0x10(%R8,%RDI,8)

  (198) 0x428b21 LEA	(%R14,%R11,1),%R8

  (198) 0x428b25 VMOVSD	%XMM0,0x8(%R8,%RDI,8)

  (198) 0x428b2c LEA	(%R15,%RDX,1),%R8

  (198) 0x428b30 VMOVSD	%XMM1,0x8(%R8,%RDI,8)

  (198) 0x428b37 ADD	%R14,%R11

  (198) 0x428b3a VMOVSD	%XMM0,(%R11,%RDI,8)

  (198) 0x428b40 ADD	%R15,%RDX

  (198) 0x428b43 VMOVSD	%XMM1,(%RDX,%RDI,8)

  (198) 0x428b48 LEA	0x1(%RBX),%RDX

  (198) 0x428b4c ADD	%R10,%RAX

  (198) 0x428b4f ADD	%RCX,%R9

  (198) 0x428b52 CMP	$0x1,%RBX

  (198) 0x428b56 MOV	%RDX,%RBX

  (198) 0x428b59 JE	428750

  (198) 0x428b5f CMP	$0x8,%R13

  (198) 0x428b63 JB	428bdf

  (198) 0x428b65 MOV	$0x38,%EDX

  (198) 0x428b6a MOV	%RSI,%R8

  (198) 0x428b6d NOPL	(%RAX)

    (199) 0x428b70 VMOVSD	%XMM0,-0x38(%R9,%RDX,1)

    (199) 0x428b77 VMOVSD	%XMM1,-0x38(%RAX,%RDX,1)

    (199) 0x428b7d VMOVSD	%XMM0,-0x30(%R9,%RDX,1)

    (199) 0x428b84 VMOVSD	%XMM1,-0x30(%RAX,%RDX,1)

    (199) 0x428b8a VMOVSD	%XMM0,-0x28(%R9,%RDX,1)

    (199) 0x428b91 VMOVSD	%XMM1,-0x28(%RAX,%RDX,1)

    (199) 0x428b97 VMOVSD	%XMM0,-0x20(%R9,%RDX,1)

    (199) 0x428b9e VMOVSD	%XMM1,-0x20(%RAX,%RDX,1)

    (199) 0x428ba4 VMOVSD	%XMM0,-0x18(%R9,%RDX,1)

    (199) 0x428bab VMOVSD	%XMM1,-0x18(%RAX,%RDX,1)

    (199) 0x428bb1 VMOVSD	%XMM0,-0x10(%R9,%RDX,1)

    (199) 0x428bb8 VMOVSD	%XMM1,-0x10(%RAX,%RDX,1)

    (199) 0x428bbe VMOVSD	%XMM0,-0x8(%R9,%RDX,1)

    (199) 0x428bc5 VMOVSD	%XMM1,-0x8(%RAX,%RDX,1)

    (199) 0x428bcb VMOVSD	%XMM0,(%R9,%RDX,1)

    (199) 0x428bd1 VMOVSD	%XMM1,(%RAX,%RDX,1)

    (199) 0x428bd6 ADD	$0x40,%RDX

    (199) 0x428bda INC	%R8

    (199) 0x428bdd JNE	428b70

  (198) 0x428bdf CMP	$0x3,%R12

  (198) 0x428be3 JGE	428c20

  (198) 0x428be5 TEST	%R12,%R12

  (198) 0x428be8 JLE	428c8f

  (198) 0x428bee MOV	-0x38(%RBP),%RDX

  (198) 0x428bf2 ADD	%RBX,%RDX

  (198) 0x428bf5 SUB	-0x30(%RBP),%RDX

  (198) 0x428bf9 MOV	%RCX,%R11

  (198) 0x428bfc IMUL	%RDX,%R11

  (198) 0x428c00 IMUL	%R10,%RDX

  (198) 0x428c04 CMP	$0x1,%R12

  (198) 0x428c08 JNE	428b0b

  (198) 0x428c0e JMP	428b21

  (198) 0x428c20 CMP	$0x5,%R12

  (198) 0x428c24 JGE	428c50

  (198) 0x428c26 MOV	-0x38(%RBP),%RDX

  (198) 0x428c2a ADD	%RBX,%RDX

  (198) 0x428c2d SUB	-0x30(%RBP),%RDX

  (198) 0x428c31 MOV	%RCX,%R11

  (198) 0x428c34 IMUL	%RDX,%R11

  (198) 0x428c38 IMUL	%R10,%RDX

  (198) 0x428c3c CMP	$0x4,%R12

  (198) 0x428c40 JE	428adf

  (198) 0x428c46 JMP	428af5

  (198) 0x428c50 JE	428ab3

  (198) 0x428c56 CMP	$0x6,%R12

  (198) 0x428c5a JNE	428b48

  (198) 0x428c60 MOV	-0x38(%RBP),%RDX

  (198) 0x428c64 ADD	%RBX,%RDX

  (198) 0x428c67 SUB	-0x30(%RBP),%RDX

  (198) 0x428c6b MOV	%RCX,%R11

  (198) 0x428c6e IMUL	%RDX,%R11

  (198) 0x428c72 MOV	-0x80(%RBP),%R8

  (198) 0x428c76 VMOVSD	%XMM0,(%R8,%R11,1)

  (198) 0x428c7c IMUL	%R10,%RDX

  (198) 0x428c80 MOV	-0x78(%RBP),%R8

  (198) 0x428c84 VMOVSD	%XMM1,(%R8,%RDX,1)

  (198) 0x428c8a JMP	428ac9

  (198) 0x428c8f MOV	-0x88(%RBP),%RDX

  (198) 0x428c96 CMP	%RDX,-0x90(%RBP)

  (198) 0x428c9d JNE	428b48

  (198) 0x428ca3 MOV	-0x38(%RBP),%RDX

  (198) 0x428ca7 ADD	%RBX,%RDX

  (198) 0x428caa SUB	-0x30(%RBP),%RDX

  (198) 0x428cae MOV	%RCX,%R11

  (198) 0x428cb1 IMUL	%RDX,%R11

  (198) 0x428cb5 IMUL	%R10,%RDX

  (198) 0x428cb9 JMP	428b37

  (196) 0x428cbe MOV	-0x38(%RBP),%RCX

  (196) 0x428cc2 LEA	(%RDX,%RCX,1),%R11

  (196) 0x428cc6 SUB	-0x30(%RBP),%R11

  (196) 0x428cca MOV	%R8,%R12

  (196) 0x428ccd IMUL	%R11,%R12

  (196) 0x428cd1 IMUL	%R10,%R11

  (196) 0x428cd5 LEA	(%R14,%R12,1),%RCX

  (196) 0x428cd9 VMOVSD	%XMM0,0x28(%RCX,%RDI,8)

  (196) 0x428cdf LEA	(%R15,%R11,1),%RCX

  (196) 0x428ce3 VMOVSD	%XMM1,0x28(%RCX,%RDI,8)

  (196) 0x428ce9 LEA	(%R14,%R12,1),%RCX

  (196) 0x428ced VMOVSD	%XMM0,0x20(%RCX,%RDI,8)

  (196) 0x428cf3 LEA	(%R15,%R11,1),%RCX

  (196) 0x428cf7 VMOVSD	%XMM1,0x20(%RCX,%RDI,8)

  (196) 0x428cfd LEA	(%R14,%R12,1),%RCX

  (196) 0x428d01 VMOVSD	%XMM0,0x18(%RCX,%RDI,8)

  (196) 0x428d07 LEA	(%R15,%R11,1),%RCX

  (196) 0x428d0b VMOVSD	%XMM1,0x18(%RCX,%RDI,8)

  (196) 0x428d11 LEA	(%R14,%R12,1),%RCX

  (196) 0x428d15 VMOVSD	%XMM0,0x10(%RCX,%RDI,8)

  (196) 0x428d1b LEA	(%R15,%R11,1),%RCX

  (196) 0x428d1f VMOVSD	%XMM1,0x10(%RCX,%RDI,8)

  (196) 0x428d25 LEA	(%R14,%R12,1),%RCX

  (196) 0x428d29 VMOVSD	%XMM0,0x8(%RCX,%RDI,8)

  (196) 0x428d2f LEA	(%R15,%R11,1),%RCX

  (196) 0x428d33 VMOVSD	%XMM1,0x8(%RCX,%RDI,8)

  (196) 0x428d39 ADD	%R14,%R12

  (196) 0x428d3c VMOVSD	%XMM0,(%R12,%RDI,8)

  (196) 0x428d42 ADD	%R15,%R11

  (196) 0x428d45 VMOVSD	%XMM1,(%R11,%RDI,8)

  (196) 0x428d4b LEA	0x1(%RDX),%RCX

  (196) 0x428d4f ADD	%R10,%RAX

  (196) 0x428d52 ADD	%R8,%R9

  (196) 0x428d55 CMP	$0x1,%RDX

  (196) 0x428d59 MOV	%RCX,%RDX

  (196) 0x428d5c JE	428750

  (196) 0x428d62 CMP	$0x8,%R13

  (196) 0x428d66 JB	428df7

  (196) 0x428d6c MOV	$0x38,%R11D

  (196) 0x428d72 MOV	%RSI,%R12

  (196) 0x428d75 NOPW	%CS:(%RAX,%RAX,1)

    (197) 0x428d80 VMOVSD	%XMM0,-0x38(%R9,%R11,1)

    (197) 0x428d87 VMOVSD	%XMM1,-0x38(%RAX,%R11,1)

    (197) 0x428d8e VMOVSD	%XMM0,-0x30(%R9,%R11,1)

    (197) 0x428d95 VMOVSD	%XMM1,-0x30(%RAX,%R11,1)

    (197) 0x428d9c VMOVSD	%XMM0,-0x28(%R9,%R11,1)

    (197) 0x428da3 VMOVSD	%XMM1,-0x28(%RAX,%R11,1)

    (197) 0x428daa VMOVSD	%XMM0,-0x20(%R9,%R11,1)

    (197) 0x428db1 VMOVSD	%XMM1,-0x20(%RAX,%R11,1)

    (197) 0x428db8 VMOVSD	%XMM0,-0x18(%R9,%R11,1)

    (197) 0x428dbf VMOVSD	%XMM1,-0x18(%RAX,%R11,1)

    (197) 0x428dc6 VMOVSD	%XMM0,-0x10(%R9,%R11,1)

    (197) 0x428dcd VMOVSD	%XMM1,-0x10(%RAX,%R11,1)

    (197) 0x428dd4 VMOVSD	%XMM0,-0x8(%R9,%R11,1)

    (197) 0x428ddb VMOVSD	%XMM1,-0x8(%RAX,%R11,1)

    (197) 0x428de2 VMOVSD	%XMM0,(%R9,%R11,1)

    (197) 0x428de8 VMOVSD	%XMM1,(%RAX,%R11,1)

    (197) 0x428dee ADD	$0x40,%R11

    (197) 0x428df2 INC	%R12

    (197) 0x428df5 JNE	428d80

  (196) 0x428df7 CMP	$0x3,%RBX

  (196) 0x428dfb JGE	428e30

  (196) 0x428dfd TEST	%RBX,%RBX

  (196) 0x428e00 JLE	428ea0

  (196) 0x428e06 MOV	-0x38(%RBP),%RCX

  (196) 0x428e0a LEA	(%RDX,%RCX,1),%R11

  (196) 0x428e0e SUB	-0x30(%RBP),%R11

  (196) 0x428e12 MOV	%R8,%R12

  (196) 0x428e15 IMUL	%R11,%R12

  (196) 0x428e19 IMUL	%R10,%R11

  (196) 0x428e1d CMP	$0x1,%RBX

  (196) 0x428e21 JNE	428d11

  (196) 0x428e27 JMP	428d25

  (196) 0x428e30 CMP	$0x5,%RBX

  (196) 0x428e34 JGE	428e60

  (196) 0x428e36 MOV	-0x38(%RBP),%RCX

  (196) 0x428e3a LEA	(%RDX,%RCX,1),%R11

  (196) 0x428e3e SUB	-0x30(%RBP),%R11

  (196) 0x428e42 MOV	%R8,%R12

  (196) 0x428e45 IMUL	%R11,%R12

  (196) 0x428e49 IMUL	%R10,%R11

  (196) 0x428e4d CMP	$0x4,%RBX

  (196) 0x428e51 JE	428ce9

  (196) 0x428e57 JMP	428cfd

  (196) 0x428e60 JE	428cbe

  (196) 0x428e66 CMP	$0x6,%RBX

  (196) 0x428e6a JNE	428d4b

  (196) 0x428e70 MOV	-0x38(%RBP),%RCX

  (196) 0x428e74 LEA	(%RDX,%RCX,1),%R11

  (196) 0x428e78 SUB	-0x30(%RBP),%R11

  (196) 0x428e7c MOV	%R8,%R12

  (196) 0x428e7f IMUL	%R11,%R12

  (196) 0x428e83 MOV	-0x80(%RBP),%RCX

  (196) 0x428e87 VMOVSD	%XMM0,(%RCX,%R12,1)

  (196) 0x428e8d IMUL	%R10,%R11

  (196) 0x428e91 MOV	-0x78(%RBP),%RCX

  (196) 0x428e95 VMOVSD	%XMM1,(%RCX,%R11,1)

  (196) 0x428e9b JMP	428cd5

  (196) 0x428ea0 MOV	-0x88(%RBP),%RCX

  (196) 0x428ea7 CMP	%RCX,-0x90(%RBP)

  (196) 0x428eae JNE	428d4b

  (196) 0x428eb4 MOV	-0x38(%RBP),%RCX

  (196) 0x428eb8 LEA	(%RDX,%RCX,1),%R11

  (196) 0x428ebc SUB	-0x30(%RBP),%R11

  (196) 0x428ec0 MOV	%R8,%R12

  (196) 0x428ec3 IMUL	%R11,%R12

  (196) 0x428ec7 IMUL	%R10,%R11

  (196) 0x428ecb JMP	428d39

0x428ed0 MOV	0x10(%RBP),%RAX

0x428ed4 CMP	(%RAX),%EDX

0x428ed6 JNE	428750

0x428edc MOV	%R11,%RBX

0x428edf MOV	%R11,%RAX

0x428ee2 SUB	-0x50(%RBP),%RAX

0x428ee6 MOV	0xb8(%RBP),%RCX

0x428eed VMOVSD	(%RCX,%RAX,8),%XMM0

0x428ef2 VUCOMISD	%XMM2,%XMM0

0x428ef6 JNE	428750

0x428efc JP	428750

0x428f02 MOV	0xb0(%RBP),%RCX

0x428f09 MOV	-0x70(%RBP),%RDX

0x428f0d VMOVSD	(%RCX,%RDX,8),%XMM0

0x428f12 VUCOMISD	%XMM3,%XMM0

0x428f16 JNE	428750

0x428f1c JP	428750

0x428f22 MOV	0xe0(%RBP),%RCX

0x428f29 MOV	(%RCX),%RCX

0x428f2c MOV	-0x70(%RBP),%R10

0x428f30 IMUL	%R10,%RCX

0x428f34 ADD	0x90(%RBP),%RCX

0x428f3b MOV	0x68(%RBP),%RDX

0x428f3f MOV	-0x40(%RBP),%R8

0x428f43 VMOVSD	-0x8(%RDX,%R8,8),%XMM0

0x428f4a VMOVSD	%XMM0,(%RCX,%RAX,8)

0x428f4f MOV	0xf0(%RBP),%RCX

0x428f56 MOV	(%RCX),%RCX

0x428f59 IMUL	%R10,%RCX

0x428f5d ADD	0x98(%RBP),%RCX

0x428f64 MOV	0x70(%RBP),%RDX

0x428f68 VMOVSD	-0x8(%RDX,%R8,8),%XMM0

0x428f6f VMOVSD	%XMM0,(%RCX,%RAX,8)

0x428f74 MOV	0x60(%RBP),%RAX

0x428f78 VMOVSD	-0x8(%RAX,%R8,8),%XMM0

0x428f7f MOV	0x100(%RBP),%RAX

0x428f86 MOV	(%RAX),%R12

0x428f89 MOV	0x58(%RBP),%RAX

0x428f8d VMOVSD	-0x8(%RAX,%R8,8),%XMM1

0x428f94 MOV	0x110(%RBP),%RAX

0x428f9b MOV	(%RAX),%R10

0x428f9e INC	%RBX

0x428fa1 CMP	%RDI,%RBX

0x428fa4 CMOVLE	%RDI,%RBX

0x428fa8 SUB	%RDI,%RBX

0x428fab LEA	0x1(%RBX),%R13

0x428faf MOV	%R13,%RAX

0x428fb2 AND	$-0x8,%RAX

0x428fb6 MOV	%RBX,-0x90(%RBP)

0x428fbd SUB	%RAX,%RBX

0x428fc0 MOV	%RAX,-0x88(%RBP)

0x428fc7 ADD	%RAX,%RDI

0x428fca SUB	-0x50(%RBP),%RDI

0x428fce LEA	(%R14,%RDI,8),%RAX

0x428fd2 ADD	$0x30,%RAX

0x428fd6 MOV	%RAX,-0x80(%RBP)

0x428fda LEA	0x30(%R15,%RDI,8),%RAX

0x428fdf MOV	%RAX,-0x78(%RBP)

0x428fe3 MOV	-0xd0(%RBP),%RDX

0x428fea MOV	%RDX,%RAX

0x428fed IMUL	%R10,%RAX

0x428ff1 MOV	-0xc8(%RBP),%RCX

0x428ff8 ADD	%R9,%RCX

0x428ffb ADD	%RCX,%RAX

0x428ffe MOV	%RDX,%RCX

0x429001 IMUL	%R12,%RCX

0x429005 ADD	-0xc0(%RBP),%R9

0x42900c ADD	%RCX,%R9

0x42900f XOR	%EDX,%EDX

0x429011 JMP	4290ba

  (194) 0x429016 MOV	-0x38(%RBP),%RCX

  (194) 0x42901a LEA	(%RDX,%RCX,1),%R11

  (194) 0x42901e SUB	-0x30(%RBP),%R11

  (194) 0x429022 MOV	%R12,%R8

  (194) 0x429025 IMUL	%R11,%R8

  (194) 0x429029 IMUL	%R10,%R11

  (194) 0x42902d LEA	(%R14,%R8,1),%RCX

  (194) 0x429031 VMOVSD	%XMM0,0x28(%RCX,%RDI,8)

  (194) 0x429037 LEA	(%R15,%R11,1),%RCX

  (194) 0x42903b VMOVSD	%XMM1,0x28(%RCX,%RDI,8)

  (194) 0x429041 LEA	(%R14,%R8,1),%RCX

  (194) 0x429045 VMOVSD	%XMM0,0x20(%RCX,%RDI,8)

  (194) 0x42904b LEA	(%R15,%R11,1),%RCX

  (194) 0x42904f VMOVSD	%XMM1,0x20(%RCX,%RDI,8)

  (194) 0x429055 LEA	(%R14,%R8,1),%RCX

  (194) 0x429059 VMOVSD	%XMM0,0x18(%RCX,%RDI,8)

  (194) 0x42905f LEA	(%R15,%R11,1),%RCX

  (194) 0x429063 VMOVSD	%XMM1,0x18(%RCX,%RDI,8)

  (194) 0x429069 LEA	(%R14,%R8,1),%RCX

  (194) 0x42906d VMOVSD	%XMM0,0x10(%RCX,%RDI,8)

  (194) 0x429073 LEA	(%R15,%R11,1),%RCX

  (194) 0x429077 VMOVSD	%XMM1,0x10(%RCX,%RDI,8)

  (194) 0x42907d LEA	(%R14,%R8,1),%RCX

  (194) 0x429081 VMOVSD	%XMM0,0x8(%RCX,%RDI,8)

  (194) 0x429087 LEA	(%R15,%R11,1),%RCX

  (194) 0x42908b VMOVSD	%XMM1,0x8(%RCX,%RDI,8)

  (194) 0x429091 ADD	%R14,%R8

  (194) 0x429094 VMOVSD	%XMM0,(%R8,%RDI,8)

  (194) 0x42909a ADD	%R15,%R11

  (194) 0x42909d VMOVSD	%XMM1,(%R11,%RDI,8)

  (194) 0x4290a3 LEA	0x1(%RDX),%RCX

  (194) 0x4290a7 ADD	%R10,%RAX

  (194) 0x4290aa ADD	%R12,%R9

  (194) 0x4290ad CMP	$0x1,%RDX

  (194) 0x4290b1 MOV	%RCX,%RDX

  (194) 0x4290b4 JE	428750

  (194) 0x4290ba CMP	$0x8,%R13

  (194) 0x4290be JB	429147

  (194) 0x4290c4 MOV	$0x38,%R8D

  (194) 0x4290ca MOV	%RSI,%R11

  (194) 0x4290cd NOPL	(%RAX)

    (195) 0x4290d0 VMOVSD	%XMM0,-0x38(%R9,%R8,1)

    (195) 0x4290d7 VMOVSD	%XMM1,-0x38(%RAX,%R8,1)

    (195) 0x4290de VMOVSD	%XMM0,-0x30(%R9,%R8,1)

    (195) 0x4290e5 VMOVSD	%XMM1,-0x30(%RAX,%R8,1)

    (195) 0x4290ec VMOVSD	%XMM0,-0x28(%R9,%R8,1)

    (195) 0x4290f3 VMOVSD	%XMM1,-0x28(%RAX,%R8,1)

    (195) 0x4290fa VMOVSD	%XMM0,-0x20(%R9,%R8,1)

    (195) 0x429101 VMOVSD	%XMM1,-0x20(%RAX,%R8,1)

    (195) 0x429108 VMOVSD	%XMM0,-0x18(%R9,%R8,1)

    (195) 0x42910f VMOVSD	%XMM1,-0x18(%RAX,%R8,1)

    (195) 0x429116 VMOVSD	%XMM0,-0x10(%R9,%R8,1)

    (195) 0x42911d VMOVSD	%XMM1,-0x10(%RAX,%R8,1)

    (195) 0x429124 VMOVSD	%XMM0,-0x8(%R9,%R8,1)

    (195) 0x42912b VMOVSD	%XMM1,-0x8(%RAX,%R8,1)

    (195) 0x429132 VMOVSD	%XMM0,(%R9,%R8,1)

    (195) 0x429138 VMOVSD	%XMM1,(%RAX,%R8,1)

    (195) 0x42913e ADD	$0x40,%R8

    (195) 0x429142 INC	%R11

    (195) 0x429145 JNE	4290d0

  (194) 0x429147 CMP	$0x3,%RBX

  (194) 0x42914b JGE	429180

  (194) 0x42914d TEST	%RBX,%RBX

  (194) 0x429150 JLE	4291f0

  (194) 0x429156 MOV	-0x38(%RBP),%RCX

  (194) 0x42915a LEA	(%RDX,%RCX,1),%R11

  (194) 0x42915e SUB	-0x30(%RBP),%R11

  (194) 0x429162 MOV	%R12,%R8

  (194) 0x429165 IMUL	%R11,%R8

  (194) 0x429169 IMUL	%R10,%R11

  (194) 0x42916d CMP	$0x1,%RBX

  (194) 0x429171 JNE	429069

  (194) 0x429177 JMP	42907d

  (194) 0x429180 CMP	$0x5,%RBX

  (194) 0x429184 JGE	4291b0

  (194) 0x429186 MOV	-0x38(%RBP),%RCX

  (194) 0x42918a LEA	(%RDX,%RCX,1),%R11

  (194) 0x42918e SUB	-0x30(%RBP),%R11

  (194) 0x429192 MOV	%R12,%R8

  (194) 0x429195 IMUL	%R11,%R8

  (194) 0x429199 IMUL	%R10,%R11

  (194) 0x42919d CMP	$0x4,%RBX

  (194) 0x4291a1 JE	429041

  (194) 0x4291a7 JMP	429055

  (194) 0x4291b0 JE	429016

  (194) 0x4291b6 CMP	$0x6,%RBX

  (194) 0x4291ba JNE	4290a3

  (194) 0x4291c0 MOV	-0x38(%RBP),%RCX

  (194) 0x4291c4 LEA	(%RDX,%RCX,1),%R11

  (194) 0x4291c8 SUB	-0x30(%RBP),%R11

  (194) 0x4291cc MOV	%R12,%R8

  (194) 0x4291cf IMUL	%R11,%R8

  (194) 0x4291d3 MOV	-0x80(%RBP),%RCX

  (194) 0x4291d7 VMOVSD	%XMM0,(%RCX,%R8,1)

  (194) 0x4291dd IMUL	%R10,%R11

  (194) 0x4291e1 MOV	-0x78(%RBP),%RCX

  (194) 0x4291e5 VMOVSD	%XMM1,(%RCX,%R11,1)

  (194) 0x4291eb JMP	42902d

  (194) 0x4291f0 MOV	-0x88(%RBP),%RCX

  (194) 0x4291f7 CMP	%RCX,-0x90(%RBP)

  (194) 0x4291fe JNE	4290a3

  (194) 0x429204 MOV	-0x38(%RBP),%RCX

  (194) 0x429208 LEA	(%RDX,%RCX,1),%R11

  (194) 0x42920c SUB	-0x30(%RBP),%R11

  (194) 0x429210 MOV	%R12,%R8

  (194) 0x429213 IMUL	%R11,%R8

  (194) 0x429217 IMUL	%R10,%R11

  (194) 0x42921b JMP	429091

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 87 - 163

--------------------------------------------------------------------------------

87:     DO k=y_min-2,y_max+2

[...]

128:         DO j=x_min-2,x_max+2

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

138:                   ENDDO

139:                 ENDDO

140:               ENDIF

141:             ENDIF

142:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

145:               energy0(j,k)=state_energy(state)

146:               density0(j,k)=state_density(state)

147:               DO kt=k,k+1

148:                 DO jt=j,j+1

149:                   xvel0(jt,kt)=state_xvel(state)

150:                   yvel0(jt,kt)=state_yvel(state)

151:                 ENDDO

152:               ENDDO

153:             ENDIF

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

156:               energy0(j,k)=state_energy(state)

157:               density0(j,k)=state_density(state)

158:               DO kt=k,k+1

159:                 DO jt=j,j+1

160:                   xvel0(jt,kt)=state_xvel(state)

161:                   yvel0(jt,kt)=state_yvel(state)

162:                 ENDDO

163:               ENDDO

Coverage (%)	Name	Source Location	Module
►95.50+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►4.50+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:50	exec
○	start	start.f90:107	exec
○	initialise	initialise.f90:141	exec
○	clover_leaf	clover_leaf.f90:49	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.35
CQA speedup if FP arith vectorized	2.35
CQA speedup if fully vectorized	12.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P6, P7, P8, P9,
Function	generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2
Source	generate_chunk_kernel.f90:87-87,generate_chunk_kernel.f90:128-133,generate_chunk_kernel.f90:136-137,generate_chunk_kernel.f90:142-146,generate_chunk_kernel.f90:149-150,generate_chunk_kernel.f90:154-157,generate_chunk_kernel.f90:160-161
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	36.50
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	15.50
CQA cycles if fully vectorized	3.00
Front-end cycles	33.38
P0 cycles	17.67
P1 cycles	17.67
P2 cycles	17.67
P3 cycles	17.67
P4 cycles	17.67
P5 cycles	17.67
P6 cycles	36.50
P7 cycles	36.50
P8 cycles	36.50
P9 cycles	36.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	4.50
P13 cycles	4.50
P14 cycles	6.50
P15 cycles	6.50
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	253.00
Nb uops	267.00
Nb loads	122.00
Nb stores	21.00
Nb stack references	39.00
FLOP/cycle	0.16
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.68
Bytes prefetched	0.00
Bytes loaded	956.00
Bytes stored	164.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.13
Vector-efficiency ratio load	11.85
Vector-efficiency ratio store	12.20
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	11.51

Metric	Value
CQA speedup if no scalar integer	2.35
CQA speedup if FP arith vectorized	2.35
CQA speedup if fully vectorized	12.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P6, P7, P8, P9,
Function	generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2
Source	generate_chunk_kernel.f90:87-87,generate_chunk_kernel.f90:128-133,generate_chunk_kernel.f90:136-137,generate_chunk_kernel.f90:142-146,generate_chunk_kernel.f90:149-150,generate_chunk_kernel.f90:154-157,generate_chunk_kernel.f90:160-161
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	36.50
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	15.50
CQA cycles if fully vectorized	3.00
Front-end cycles	33.38
P0 cycles	17.67
P1 cycles	17.67
P2 cycles	17.67
P3 cycles	17.67
P4 cycles	17.67
P5 cycles	17.67
P6 cycles	36.50
P7 cycles	36.50
P8 cycles	36.50
P9 cycles	36.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	4.50
P13 cycles	4.50
P14 cycles	6.50
P15 cycles	6.50
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	253.00
Nb uops	267.00
Nb loads	122.00
Nb stores	21.00
Nb stack references	39.00
FLOP/cycle	0.16
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.68
Bytes prefetched	0.00
Bytes loaded	956.00
Bytes stored	164.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.13
Vector-efficiency ratio load	11.85
Vector-efficiency ratio store	12.20
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	11.51

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	generate_chunk_kernel.f90:87-163
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:87,128-163.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:87,128-133,136-137,142-146,149-150,154-157,160-161.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 64 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 36.50 to 15.50 cycles (2.35x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 36.50 to 3.00 cycles (12.17x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- use the vec-report option to understand why your loop was not vectorized. If "existence of vector dependences", try the IVDEP directive. If, using IVDEP, "vectorization possible but seems inefficient", try the VECTOR ALWAYS directive.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 36.50 to 33.38 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVG: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:128
CMOVLE: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:87
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:87
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:87
LEA: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:131
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:144
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:155
VUCOMISD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:130
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:130
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:131
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:131
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:144
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:155
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:155

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (1 inside FMA instructions)
2: multiply (1 inside FMA instructions)
1: square root

The binary loop is loading 956 bytes (119 double precision FP elements). The binary loop is storing 164 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	253
nb uops	267
loop length	1180
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	39
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.38 cycles
front end	33.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	17.67	17.67	17.67	17.67	17.67	17.67	36.50	36.50	36.50	36.50	1.50	1.50	4.50	4.50	6.50	6.50
cycles	17.67	17.67	17.67	17.67	17.67	17.67	36.50	36.50	36.50	36.50	1.50	1.50	4.50	4.50	6.50	6.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

8.50

Cycles summary

Front-end	33.38
Dispatch	36.50
DIV/SQRT	8.50
Overall L1	36.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	7%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

INT+FP

all	12%
load	11%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 36.50 cycles. At this rate:

10% of peak load performance is reached (26.19 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.49 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42877b

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x58(%RBP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0xd8(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x188(%RBP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV -0xf4(%RBP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JE 4286a0 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD %R8D,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%RDI,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMOVG %RCX,%RSI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
NEG %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x180(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R10,%RAX,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP -0xf0(%RBP),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %RCX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8D,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R10,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JNE 428960 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x830>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%R11),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB -0x50(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0xb8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD -0x8(%RAX,%RCX,8),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB -0x50(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%RCX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD (%RAX,%RDX,8),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x178(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX,%RCX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD -0x8(%RAX,%RCX,8),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%RCX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD (%RAX,%RCX,8),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xe0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x90(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x68(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xf0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x98(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x100(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%RDX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RDI,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVLE %RDI,%R12	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RDI,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%R12),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB -0x50(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R14,%RDI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x30,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x30(%R15,%RDI,8),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0xd0(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xc8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xc0(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 428b5f <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xa2f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP (%RAX),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 428ed0 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xda0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB -0x50(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0xa8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RCX,%RDX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD %XMM0,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
MOV 0x30(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RCX,%RDX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xe0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x90(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x68(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RCX,%R10,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xf0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x98(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RCX,%R10,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%R10,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x100(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%R10,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVLE %RDI,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RBX),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB -0x50(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R14,%RDI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x30,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x30(%R15,%RDI,8),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0xd0(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xc8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R9,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R8,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xc0(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 428d62 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xc32>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP (%RAX),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB -0x50(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0xb8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VUCOMISD %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JNE 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JP 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xb0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VUCOMISD %XMM3,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JNE 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JP 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xe0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R10,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x90(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x68(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RDX,%R8,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xf0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R10,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x98(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RDX,%R8,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%R8,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x100(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%R8,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVLE %RDI,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RBX),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB -0x50(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R14,%RDI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x30,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x30(%R15,%RDI,8),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0xd0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xc8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R12,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xc0(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4290ba <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xf8a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	generate_chunk_kernel.f90:87-163
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- use the vec-report option to understand why your loop was not vectorized. If "existence of vector dependences", try the IVDEP directive. If, using IVDEP, "vectorization possible but seems inefficient", try the VECTOR ALWAYS directive.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 36.50 to 33.38 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVG: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:128
CMOVLE: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:87
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:87
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:87
LEA: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:131
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:144
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:155
VUCOMISD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:130
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:130
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:131
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:131
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:144
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:155
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:155

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (1 inside FMA instructions)
2: multiply (1 inside FMA instructions)
1: square root

The binary loop is loading 956 bytes (119 double precision FP elements). The binary loop is storing 164 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	253
nb uops	267
loop length	1180
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	39
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.38 cycles
front end	33.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	17.67	17.67	17.67	17.67	17.67	17.67	36.50	36.50	36.50	36.50	1.50	1.50	4.50	4.50	6.50	6.50
cycles	17.67	17.67	17.67	17.67	17.67	17.67	36.50	36.50	36.50	36.50	1.50	1.50	4.50	4.50	6.50	6.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

8.50

Cycles summary

Front-end	33.38
Dispatch	36.50
DIV/SQRT	8.50
Overall L1	36.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	7%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

INT+FP

all	12%
load	11%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 36.50 cycles. At this rate:

10% of peak load performance is reached (26.19 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.49 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42877b

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x58(%RBP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0xd8(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x188(%RBP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV -0xf4(%RBP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JE 4286a0 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD %R8D,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%RDI,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMOVG %RCX,%RSI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SUB %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
NEG %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x180(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R10,%RAX,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP -0xf0(%RBP),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %RCX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8D,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R10,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JNE 428960 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x830>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%R11),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB -0x50(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0xb8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD -0x8(%RAX,%RCX,8),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB -0x50(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%RCX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD (%RAX,%RDX,8),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x178(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX,%RCX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD -0x8(%RAX,%RCX,8),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%RCX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD (%RAX,%RCX,8),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xe0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x90(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x68(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xf0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x98(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x100(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%RDX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RDI,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVLE %RDI,%R12	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RDI,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%R12),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB -0x50(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R14,%RDI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x30,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x30(%R15,%RDI,8),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0xd0(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xc8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xc0(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 428b5f <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xa2f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP (%RAX),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 428ed0 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xda0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB -0x50(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0xa8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RCX,%RDX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM3,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD %XMM0,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
MOV 0x30(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RCX,%RDX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xe0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x90(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x68(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RCX,%R10,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xf0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R8,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x98(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RCX,%R10,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%R10,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x100(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%R10,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVLE %RDI,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RBX),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB -0x50(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R14,%RDI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x30,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x30(%R15,%RDI,8),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0xd0(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xc8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R9,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R8,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xc0(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 428d62 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xc32>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP (%RAX),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB -0x50(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0xb8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VUCOMISD %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JNE 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JP 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xb0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VUCOMISD %XMM3,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JNE 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JP 428750 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xe0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R10,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x90(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x68(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RDX,%R8,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xf0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R10,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x98(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RDX,%R8,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%R8,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x100(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x8(%RAX,%R8,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVLE %RDI,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RBX),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB -0x50(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R14,%RDI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x30,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x30(%R15,%RDI,8),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0xd0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xc8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R12,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xc0(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4290ba <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xf8a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code