OV - exec - Loop 178

	Loop Id: 178	Module: exec	Source: field_summary_kernel.f90:58-71	Coverage: 0.29%

0x4265e0 VPADDQ	%XMM4,%XMM15,%XMM16

0x4265e6 VMOVQ	%XMM16,%R15

0x4265ec SUB	%RDX,%R15

0x4265ef VMOVUPD	(%R12,%R15,8),%YMM16    [5]

0x4265f6 VMOVUPD	0x8(%R12,%R15,8),%YMM17    [5]

0x426601 VMOVUPD	(%R11,%R15,8),%YMM18    [1]

0x426608 VMOVUPD	0x8(%R11,%R15,8),%YMM19    [1]

0x426613 VMOVUPD	(%R8,%R15,8),%YMM20    [7]

0x42661a VMOVUPD	0x8(%R8,%R15,8),%YMM21    [7]

0x426625 VMOVUPD	(%R9,%R15,8),%YMM22    [8]

0x42662c VMOVUPD	0x8(%R9,%R15,8),%YMM23    [8]

0x426637 VMOVUPD	(%RBX,%R15,8),%YMM24    [4]

0x42663e VMULPD	(%R14,%R15,8),%YMM24,%YMM25    [2]

0x426645 VFMADD231PD	(%RDI,%R15,8),%YMM25,%YMM12    [3]

0x42664c VFMADD231PD	(%RCX,%R15,8),%YMM24,%YMM14    [6]

0x426653 VMULPD	%YMM16,%YMM16,%YMM16

0x426659 VFMADD213PD	%YMM16,%YMM18,%YMM18

0x42665f VFMADD231PD	%YMM17,%YMM17,%YMM18

0x426665 VFMADD231PD	%YMM19,%YMM19,%YMM18

0x42666b VFMADD213PD	%YMM18,%YMM20,%YMM20

0x426671 VFMADD213PD	%YMM20,%YMM22,%YMM22

0x426677 VFMADD231PD	%YMM21,%YMM21,%YMM22

0x42667d VFMADD231PD	%YMM23,%YMM23,%YMM22

0x426683 VADDPD	%YMM24,%YMM10,%YMM10

0x426689 VADDPD	%YMM25,%YMM11,%YMM11

0x42668f VMULPD	%YMM22,%YMM25,%YMM16

0x426695 VFMADD231PD	%YMM8,%YMM16,%YMM13

0x42669b VPADDQ	%YMM9,%YMM15,%YMM15

0x4266a0 ADD	$0x4,%RSI

0x4266a4 CMP	%R10,%RSI

0x4266a7 JB	4265e0

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 58 - 71

--------------------------------------------------------------------------------

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

Coverage (%)	Name	Source Location	Module
►51.02+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►36.68+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►5.73+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
►3.29+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	field_summary_kernel	field_summary_kernel.f90:77	exec
○	field_summary	field_summary.f90:70	exec
○	hydro	hydro.f90:81	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.40+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.73
Bottlenecks	P10, P11,
Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source	field_summary_kernel.f90:58-71
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	6.50
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	3.25
Front-end cycles	3.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	6.50
P11 cycles	6.50
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	30.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	15.38
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	40.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	59.08
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	96.30
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	47.69
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	43.75
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.73
Bottlenecks	P10, P11,
Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source	field_summary_kernel.f90:58-71
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	6.50
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	3.25
Front-end cycles	3.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	6.50
P11 cycles	6.50
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	30.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	15.38
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	40.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	59.08
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	96.30
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	47.69
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	43.75
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	field_summary_kernel.f90:58-71
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:58-71.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.50 to 3.75 cycles (1.73x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

FMA

Detected 40 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

15 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 100 FP arithmetical operations:

48: addition or subtraction (40 inside FMA instructions)
52: multiply (40 inside FMA instructions)

The binary loop is loading 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	31
nb uops	30
loop length	205
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	18
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.67

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	3.00	3.00	3.00	3.00	6.50	6.50	2.00	2.00	0.50	0.50
cycles	0.50	0.50	0.50	0.50	0.50	0.50	3.00	3.00	3.00	3.00	6.50	6.50	2.00	2.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	3.75
Dispatch	6.50
Data deps.	4.00
Overall L1	6.50

Vectorization ratios

INT

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	96%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	47%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	43%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

23% of peak load performance is reached (59.08 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4265e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VPADDQ %XMM4,%XMM15,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVQ %XMM16,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SUB %RDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R12,%R15,8),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x8(%R12,%R15,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R11,%R15,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x8(%R11,%R15,8),%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R8,%R15,8),%YMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x8(%R8,%R15,8),%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R9,%R15,8),%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x8(%R9,%R15,8),%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RBX,%R15,8),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD (%R14,%R15,8),%YMM24,%YMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD (%RDI,%R15,8),%YMM25,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD (%RCX,%R15,8),%YMM24,%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM16,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM16,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM17,%YMM17,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM19,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM18,%YMM20,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM20,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM21,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM23,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM24,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM25,%YMM11,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM22,%YMM25,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM16,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPADDQ %YMM9,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
ADD $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 4265e0 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x430>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	field_summary_kernel.f90:58-71
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

FMA

Detected 40 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

15 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 100 FP arithmetical operations:

48: addition or subtraction (40 inside FMA instructions)
52: multiply (40 inside FMA instructions)

The binary loop is loading 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	31
nb uops	30
loop length	205
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	18
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.67

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	3.00	3.00	3.00	3.00	6.50	6.50	2.00	2.00	0.50	0.50
cycles	0.50	0.50	0.50	0.50	0.50	0.50	3.00	3.00	3.00	3.00	6.50	6.50	2.00	2.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	3.75
Dispatch	6.50
Data deps.	4.00
Overall L1	6.50

Vectorization ratios

INT

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	96%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	47%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	43%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

23% of peak load performance is reached (59.08 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4265e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VPADDQ %XMM4,%XMM15,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVQ %XMM16,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SUB %RDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R12,%R15,8),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x8(%R12,%R15,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R11,%R15,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x8(%R11,%R15,8),%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R8,%R15,8),%YMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x8(%R8,%R15,8),%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R9,%R15,8),%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x8(%R9,%R15,8),%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RBX,%R15,8),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD (%R14,%R15,8),%YMM24,%YMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD (%RDI,%R15,8),%YMM25,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD (%RCX,%R15,8),%YMM24,%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM16,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM16,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM17,%YMM17,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM19,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM18,%YMM20,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM20,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM21,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM23,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM24,%YMM10,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM25,%YMM11,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM22,%YMM25,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM16,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPADDQ %YMM9,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
ADD $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 4265e0 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x430>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code