OV - exec - Loop 167

	Loop Id: 167	Module: exec	Source: calc_dt_kernel.f90:92-129	Coverage: 3.31%

0x424ad0 MOV	-0x190(%RBP),%RDI    [8]

0x424ad7 VMOVUPD	(%RDI,%RDX,8),%YMM26    [10]

0x424ade VMOVUPD	(%R10,%RDX,8),%YMM27    [2]

0x424ae5 VMOVUPD	(%R14,%RDX,8),%YMM28    [4]

0x424aec VADDPD	%YMM28,%YMM28,%YMM28

0x424af2 VDIVPD	(%RAX,%RDX,8),%YMM28,%YMM28    [1]

0x424af9 VFMADD231PD	%YMM27,%YMM27,%YMM28

0x424aff VSQRTPD	%YMM28,%YMM27

0x424b05 VCMPPD	$0x2,%YMM27,%YMM10,%K2

0x424b0c VBLENDMPD	%YMM27,%YMM10,%YMM27{%K2}

0x424b12 VCMPPD	$0x2,%YMM11,%YMM26,%K2

0x424b19 VBLENDMPD	%YMM26,%YMM11,%YMM26{%K2}

0x424b1f VMULPD	%YMM26,%YMM12,%YMM26

0x424b25 VDIVPD	%YMM27,%YMM26,%YMM26

0x424b2b VMULPD	%YMM14,%YMM18,%YMM27

0x424b31 VANDPD	%YMM2,%YMM22,%YMM22

0x424b37 VANDPD	%YMM2,%YMM23,%YMM23

0x424b3d VMULPD	%YMM10,%YMM24,%YMM24

0x424b43 VCMPPD	$0x2,%YMM23,%YMM24,%K2

0x424b4a VBLENDMPD	%YMM23,%YMM24,%YMM23{%K2}

0x424b50 VCMPPD	$0x2,%YMM22,%YMM23,%K2

0x424b57 VMOVAPD	%YMM22,%YMM23{%K2}

0x424b5d VDIVPD	%YMM23,%YMM27,%YMM22

0x424b63 VMULPD	%YMM15,%YMM18,%YMM18

0x424b69 VANDPD	%YMM2,%YMM19,%YMM19

0x424b6f VANDPD	%YMM2,%YMM21,%YMM21

0x424b75 VCMPPD	$0x2,%YMM21,%YMM24,%K2

0x424b7c VMOVAPD	%YMM21,%YMM24{%K2}

0x424b82 VCMPPD	$0x2,%YMM19,%YMM24,%K2

0x424b89 VMOVAPD	%YMM19,%YMM24{%K2}

0x424b8f VDIVPD	%YMM24,%YMM18,%YMM19

0x424b95 VBROADCASTSD	%XMM25,%YMM18

0x424b9b VXORPD	%YMM3,%YMM18,%YMM21

0x424ba1 VBROADCASTSD	%XMM20,%YMM18

0x424ba7 VDIVPD	%YMM17,%YMM21,%YMM18{%K1}

0x424bad VCMPPD	$0x2,%YMM18,%YMM19,%K1

0x424bb4 VMOVAPD	%YMM19,%YMM18{%K1}

0x424bba VCMPPD	$0x2,%YMM18,%YMM22,%K1

0x424bc1 VMOVAPD	%YMM22,%YMM18{%K1}

0x424bc7 VCMPPD	$0x2,%YMM18,%YMM26,%K1

0x424bce VMOVAPD	%YMM26,%YMM18{%K1}

0x424bd4 VCMPPD	$0x2,%YMM18,%YMM13,%K1

0x424bdb VMOVAPD	%YMM13,%YMM18{%K1}

0x424be1 ADD	$0x4,%RDX

0x424be5 VMOVAPD	%YMM18,%YMM13

0x424beb CMP	-0x40(%RBP),%RDX    [8]

0x424bef JAE	424cc0

0x424bf5 VMOVUPD	-0x8(%R15,%RDX,8),%YMM17    [5]

0x424c00 VMOVUPD	(%R15,%RDX,8),%YMM18    [5]

0x424c07 VADDPD	-0x8(%RBX,%RDX,8),%YMM17,%YMM17    [6]

0x424c12 VMULPD	-0x8(%R8,%RDX,8),%YMM17,%YMM22    [13]

0x424c1d VADDPD	(%RBX,%RDX,8),%YMM18,%YMM17    [6]

0x424c24 VMULPD	(%R8,%RDX,8),%YMM17,%YMM23    [13]

0x424c2b VMOVUPD	(%R12,%RDX,8),%YMM24    [9]

0x424c32 VADDPD	%YMM24,%YMM24,%YMM18

0x424c38 VMOVUPD	(%R9,%RDX,8),%YMM17    [14]

0x424c3f VADDPD	-0x8(%R9,%RDX,8),%YMM17,%YMM17    [14]

0x424c4a VMULPD	(%R13,%RDX,8),%YMM17,%YMM19    [3]

0x424c52 VMOVUPD	(%RSI,%RDX,8),%YMM17    [15]

0x424c59 VADDPD	-0x8(%RSI,%RDX,8),%YMM17,%YMM17    [15]

0x424c64 VMULPD	(%RCX,%RDX,8),%YMM17,%YMM21    [7]

0x424c6b VADDPD	%YMM19,%YMM22,%YMM17

0x424c71 VSUBPD	%YMM17,%YMM23,%YMM17

0x424c77 VADDPD	%YMM21,%YMM17,%YMM17

0x424c7d VDIVPD	%YMM18,%YMM17,%YMM17

0x424c83 VCMPPD	$0x5,%YMM16,%YMM17,%K0

0x424c8a KORTESTB	%K0,%K0

0x424c8e JE	424c9a

0x424c90 MOV	0x78(%RBP),%RDI    [8]

0x424c94 VMOVSD	(%RDI),%XMM20    [12]

0x424c9a VCMPPD	$0x1,%YMM16,%YMM17,%K1

0x424ca1 KORTESTB	%K1,%K1

0x424ca5 JE	424ad0

0x424cab MOV	0x58(%RBP),%RDI    [8]

0x424caf VMOVSD	(%RDI),%XMM25    [11]

0x424cb5 JMP	424ad0

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 92 - 129

--------------------------------------------------------------------------------

92:     DO k=y_min,y_max

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

Coverage (%)	Name	Source Location	Module
►50.82+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►36.74+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►5.62+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
►4.15+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	calc_dt_kernel	calc_dt_kernel.f90:89	exec
○	calc_dt	calc_dt.f90:49	exec
○	timestep	timestep.f90:85	exec
○	hydro	hydro.f90:54	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.33+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.65
Bottlenecks
Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source	calc_dt_kernel.f90:92-129
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	32.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	16.25
CQA cycles if fully vectorized	16.25
Front-end cycles	9.44
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	5.25
P7 cycles	5.25
P8 cycles	5.25
P9 cycles	5.25
P10 cycles	12.25
P11 cycles	12.25
P12 cycles	12.25
P13 cycles	12.25
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	32.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	73.50
Nb uops	75.50
Nb loads	21.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	3.20
Nb FLOP add-sub	36.00
Nb FLOP mul	32.00
Nb FLOP fma	4.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.72
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	95.32
Vectorization ratio load	94.59
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	93.33
Vector-efficiency ratio all	48.25
Vector-efficiency ratio load	47.97
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.65
Bottlenecks	P10, P11,
Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source	calc_dt_kernel.f90:92-129
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	32.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	16.25
CQA cycles if fully vectorized	16.25
Front-end cycles	9.75
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	1.33
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	5.75
P7 cycles	5.75
P8 cycles	5.75
P9 cycles	5.75
P10 cycles	12.25
P11 cycles	12.25
P12 cycles	12.25
P13 cycles	12.25
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	32.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	78.00
Nb loads	23.00
Nb stores	0.00
Nb stack references	4.00
FLOP/cycle	3.20
Nb FLOP add-sub	36.00
Nb FLOP mul	32.00
Nb FLOP fma	4.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.22
Bytes prefetched	0.00
Bytes loaded	592.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	93.85
Vectorization ratio load	89.47
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	93.33
Vector-efficiency ratio all	47.69
Vector-efficiency ratio load	46.05
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.65
Bottlenecks	P10, P11,
Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source	calc_dt_kernel.f90:92-129
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	32.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	16.25
CQA cycles if fully vectorized	16.25
Front-end cycles	9.38
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	5.25
P7 cycles	5.25
P8 cycles	5.25
P9 cycles	5.25
P10 cycles	12.25
P11 cycles	12.25
P12 cycles	12.25
P13 cycles	12.25
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	32.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	73.00
Nb uops	75.00
Nb loads	21.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	3.20
Nb FLOP add-sub	36.00
Nb FLOP mul	32.00
Nb FLOP fma	4.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.72
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	95.31
Vectorization ratio load	94.44
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	93.33
Vector-efficiency ratio all	48.24
Vector-efficiency ratio load	47.92
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.65
Bottlenecks	P10, P11,
Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source	calc_dt_kernel.f90:92-129
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	32.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	16.25
CQA cycles if fully vectorized	16.25
Front-end cycles	9.50
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	1.33
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	5.25
P7 cycles	5.25
P8 cycles	5.25
P9 cycles	5.25
P10 cycles	12.25
P11 cycles	12.25
P12 cycles	12.25
P13 cycles	12.25
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	32.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	74.00
Nb uops	76.00
Nb loads	21.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	3.20
Nb FLOP add-sub	36.00
Nb FLOP mul	32.00
Nb FLOP fma	4.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.72
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	95.31
Vectorization ratio load	94.44
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	93.33
Vector-efficiency ratio all	48.24
Vector-efficiency ratio load	47.92
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.65
Bottlenecks	P10, P11,
Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source	calc_dt_kernel.f90:92-129
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	32.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	16.25
CQA cycles if fully vectorized	16.25
Front-end cycles	9.13
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	4.75
P7 cycles	4.75
P8 cycles	4.75
P9 cycles	4.75
P10 cycles	12.25
P11 cycles	12.25
P12 cycles	12.25
P13 cycles	12.25
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	32.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	73.00
Nb loads	19.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	3.20
Nb FLOP add-sub	36.00
Nb FLOP mul	32.00
Nb FLOP fma	4.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.23
Bytes prefetched	0.00
Bytes loaded	560.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	96.83
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	93.33
Vector-efficiency ratio all	48.81
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	calc_dt_kernel.f90:92-129
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92-129.

It is main loop of related source loop which is unrolled by 4 (including vectorization).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

94% of SSE/AVX loads are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.50 to 12.25 cycles (2.65x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KORTESTB: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

37 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 104 FP arithmetical operations:

40: addition or subtraction (4 inside FMA instructions)
36: multiply (4 inside FMA instructions)
24: divide
4: square root

The binary loop is loading 576 bytes (72 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	73.50
nb uops	75.50
loop length	477.50
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	19
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	9.44 cycles
front end	9.44 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	1.17	1.17	1.17	5.25	5.25	5.25	5.25	12.25	12.25	12.25	12.25	1.00	1.00
cycles	0.67	0.67	0.67	1.17	1.17	1.17	5.25	5.25	5.25	5.25	12.25	12.25	12.25	12.25	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	32.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.44
Dispatch	12.25
DIV/SQRT	32.50
Data deps.	0.00
Overall L1	32.50

Vectorization ratios

all	95%
load	94%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

Vector efficiency ratios

all	48%
load	47%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.50 cycles. At this rate:

6% of peak load performance is reached (17.72 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	calc_dt_kernel.f90:92-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions).

Details

93% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

89% of SSE/AVX loads are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 32.50 to 12.25 cycles (2.65x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.50 to 12.25 cycles (2.65x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KORTESTB: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

37 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 104 FP arithmetical operations:

40: addition or subtraction (4 inside FMA instructions)
36: multiply (4 inside FMA instructions)
24: divide
4: square root

The binary loop is loading 592 bytes (74 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	78
loop length	490
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	19
used zmm registers	0
nb stack references	4
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	1.33	1.33	1.33	5.75	5.75	5.75	5.75	12.25	12.25	12.25	12.25	1.00	1.00
cycles	0.67	0.67	0.67	1.33	1.33	1.33	5.75	5.75	5.75	5.75	12.25	12.25	12.25	12.25	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	32.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.75
Dispatch	12.25
DIV/SQRT	32.50
Data deps.	0.00
Overall L1	32.50

Vectorization ratios

all	93%
load	89%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

Vector efficiency ratios

all	47%
load	46%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.50 cycles. At this rate:

7% of peak load performance is reached (18.22 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 424bf5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x190(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD (%RDI,%RDX,8),%YMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R10,%RDX,8),%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R14,%RDX,8),%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM28,%YMM28,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD (%RAX,%RDX,8),%YMM28,%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VFMADD231PD %YMM27,%YMM27,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM28,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (50.0%)
VCMPPD $0x2,%YMM27,%YMM10,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM27,%YMM10,%YMM27{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM11,%YMM26,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM26,%YMM11,%YMM26{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM26,%YMM12,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM27,%YMM26,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM14,%YMM18,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM2,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM2,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM10,%YMM24,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x2,%YMM23,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM23,%YMM24,%YMM23{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM22,%YMM23,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM23{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VDIVPD %YMM23,%YMM27,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM15,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM2,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM2,%YMM21,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM21,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM21,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM19,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VDIVPD %YMM24,%YMM18,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VBROADCASTSD %XMM25,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VXORPD %YMM3,%YMM18,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VBROADCASTSD %XMM20,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VDIVPD %YMM17,%YMM21,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM22,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM26,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM26,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM13,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM13,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %YMM18,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
CMP -0x40(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JAE 424cc0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x750>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD -0x8(%R15,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R15,%RDX,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%RBX,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD -0x8(%R8,%RDX,8),%YMM17,%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD (%RBX,%RDX,8),%YMM18,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R8,%RDX,8),%YMM17,%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R12,%RDX,8),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM24,%YMM24,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD (%R9,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%R9,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R13,%RDX,8),%YMM17,%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%RSI,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%RCX,%RDX,8),%YMM17,%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM19,%YMM22,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM17,%YMM23,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM21,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VCMPPD $0x5,%YMM16,%YMM17,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 424c9a <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x72a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VCMPPD $0x1,%YMM16,%YMM17,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KORTESTB %K1,%K1	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 424ad0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x560>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x58(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 424ad0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x560>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	calc_dt_kernel.f90:92-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

94% of SSE/AVX loads are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.50 to 12.25 cycles (2.65x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KORTESTB: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

37 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 104 FP arithmetical operations:

40: addition or subtraction (4 inside FMA instructions)
36: multiply (4 inside FMA instructions)
24: divide
4: square root

The binary loop is loading 576 bytes (72 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	73
nb uops	75
loop length	475
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	19
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.38 cycles
front end	9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	1.00	1.00	1.00	5.25	5.25	5.25	5.25	12.25	12.25	12.25	12.25	1.00	1.00
cycles	0.67	0.67	0.67	1.00	1.00	1.00	5.25	5.25	5.25	5.25	12.25	12.25	12.25	12.25	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	32.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.38
Dispatch	12.25
DIV/SQRT	32.50
Data deps.	0.00
Overall L1	32.50

Vectorization ratios

all	95%
load	94%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

Vector efficiency ratios

all	48%
load	47%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.50 cycles. At this rate:

6% of peak load performance is reached (17.72 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 424bf5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x190(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD (%RDI,%RDX,8),%YMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R10,%RDX,8),%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R14,%RDX,8),%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM28,%YMM28,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD (%RAX,%RDX,8),%YMM28,%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VFMADD231PD %YMM27,%YMM27,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM28,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (50.0%)
VCMPPD $0x2,%YMM27,%YMM10,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM27,%YMM10,%YMM27{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM11,%YMM26,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM26,%YMM11,%YMM26{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM26,%YMM12,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM27,%YMM26,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM14,%YMM18,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM2,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM2,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM10,%YMM24,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x2,%YMM23,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM23,%YMM24,%YMM23{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM22,%YMM23,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM23{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VDIVPD %YMM23,%YMM27,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM15,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM2,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM2,%YMM21,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM21,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM21,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM19,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VDIVPD %YMM24,%YMM18,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VBROADCASTSD %XMM25,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VXORPD %YMM3,%YMM18,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VBROADCASTSD %XMM20,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VDIVPD %YMM17,%YMM21,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM22,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM26,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM26,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM13,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM13,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %YMM18,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
CMP -0x40(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JAE 424cc0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x750>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD -0x8(%R15,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R15,%RDX,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%RBX,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD -0x8(%R8,%RDX,8),%YMM17,%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD (%RBX,%RDX,8),%YMM18,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R8,%RDX,8),%YMM17,%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R12,%RDX,8),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM24,%YMM24,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD (%R9,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%R9,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R13,%RDX,8),%YMM17,%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%RSI,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%RCX,%RDX,8),%YMM17,%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM19,%YMM22,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM17,%YMM23,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM21,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VCMPPD $0x5,%YMM16,%YMM17,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 424c9a <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x72a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VCMPPD $0x1,%YMM16,%YMM17,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KORTESTB %K1,%K1	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 424ad0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x560>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	calc_dt_kernel.f90:92-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

94% of SSE/AVX loads are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.50 to 12.25 cycles (2.65x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KORTESTB: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

37 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 104 FP arithmetical operations:

40: addition or subtraction (4 inside FMA instructions)
36: multiply (4 inside FMA instructions)
24: divide
4: square root

The binary loop is loading 576 bytes (72 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	74
nb uops	76
loop length	480
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	19
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	1.33	1.33	1.33	5.25	5.25	5.25	5.25	12.25	12.25	12.25	12.25	1.00	1.00
cycles	0.67	0.67	0.67	1.33	1.33	1.33	5.25	5.25	5.25	5.25	12.25	12.25	12.25	12.25	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	32.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.50
Dispatch	12.25
DIV/SQRT	32.50
Data deps.	0.00
Overall L1	32.50

Vectorization ratios

all	95%
load	94%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

Vector efficiency ratios

all	48%
load	47%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.50 cycles. At this rate:

6% of peak load performance is reached (17.72 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 424bf5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x190(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD (%RDI,%RDX,8),%YMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R10,%RDX,8),%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R14,%RDX,8),%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM28,%YMM28,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD (%RAX,%RDX,8),%YMM28,%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VFMADD231PD %YMM27,%YMM27,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM28,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (50.0%)
VCMPPD $0x2,%YMM27,%YMM10,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM27,%YMM10,%YMM27{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM11,%YMM26,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM26,%YMM11,%YMM26{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM26,%YMM12,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM27,%YMM26,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM14,%YMM18,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM2,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM2,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM10,%YMM24,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x2,%YMM23,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM23,%YMM24,%YMM23{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM22,%YMM23,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM23{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VDIVPD %YMM23,%YMM27,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM15,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM2,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM2,%YMM21,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM21,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM21,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM19,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VDIVPD %YMM24,%YMM18,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VBROADCASTSD %XMM25,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VXORPD %YMM3,%YMM18,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VBROADCASTSD %XMM20,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VDIVPD %YMM17,%YMM21,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM22,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM26,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM26,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM13,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM13,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %YMM18,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
CMP -0x40(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JAE 424cc0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x750>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD -0x8(%R15,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R15,%RDX,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%RBX,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD -0x8(%R8,%RDX,8),%YMM17,%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD (%RBX,%RDX,8),%YMM18,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R8,%RDX,8),%YMM17,%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R12,%RDX,8),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM24,%YMM24,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD (%R9,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%R9,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R13,%RDX,8),%YMM17,%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%RSI,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%RCX,%RDX,8),%YMM17,%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM19,%YMM22,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM17,%YMM23,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM21,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VCMPPD $0x5,%YMM16,%YMM17,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 424c9a <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x72a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VCMPPD $0x1,%YMM16,%YMM17,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KORTESTB %K1,%K1	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 424ad0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x560>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x58(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 424ad0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x560>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2
Source file and lines	calc_dt_kernel.f90:92-129
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 48% of vector register length is used (average across all SSE/AVX instructions).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with no-prec-div or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.50 to 12.25 cycles (2.65x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KORTESTB: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92

Type of elements and instruction set

37 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 104 FP arithmetical operations:

40: addition or subtraction (4 inside FMA instructions)
36: multiply (4 inside FMA instructions)
24: divide
4: square root

The binary loop is loading 560 bytes (70 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	71
nb uops	73
loop length	465
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	19
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.13 cycles
front end	9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	1.00	1.00	1.00	4.75	4.75	4.75	4.75	12.25	12.25	12.25	12.25	1.00	1.00
cycles	0.67	0.67	0.67	1.00	1.00	1.00	4.75	4.75	4.75	4.75	12.25	12.25	12.25	12.25	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	32.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.13
Dispatch	12.25
DIV/SQRT	32.50
Data deps.	0.00
Overall L1	32.50

Vectorization ratios

all	96%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

Vector efficiency ratios

all	48%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.50 cycles. At this rate:

6% of peak load performance is reached (17.23 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 424bf5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x190(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD (%RDI,%RDX,8),%YMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R10,%RDX,8),%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R14,%RDX,8),%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM28,%YMM28,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD (%RAX,%RDX,8),%YMM28,%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VFMADD231PD %YMM27,%YMM27,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM28,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (50.0%)
VCMPPD $0x2,%YMM27,%YMM10,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM27,%YMM10,%YMM27{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM11,%YMM26,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM26,%YMM11,%YMM26{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM26,%YMM12,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM27,%YMM26,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM14,%YMM18,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM2,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM2,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM10,%YMM24,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x2,%YMM23,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBLENDMPD %YMM23,%YMM24,%YMM23{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM22,%YMM23,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM23{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VDIVPD %YMM23,%YMM27,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM15,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM2,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM2,%YMM21,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VCMPPD $0x2,%YMM21,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM21,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM19,%YMM24,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VDIVPD %YMM24,%YMM18,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VBROADCASTSD %XMM25,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VXORPD %YMM3,%YMM18,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VBROADCASTSD %XMM20,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VDIVPD %YMM17,%YMM21,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM22,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM26,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM26,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VCMPPD $0x2,%YMM18,%YMM13,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM13,%YMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %YMM18,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
CMP -0x40(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JAE 424cc0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x750>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD -0x8(%R15,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R15,%RDX,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%RBX,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD -0x8(%R8,%RDX,8),%YMM17,%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD (%RBX,%RDX,8),%YMM18,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R8,%RDX,8),%YMM17,%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R12,%RDX,8),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM24,%YMM24,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD (%R9,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%R9,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R13,%RDX,8),%YMM17,%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%RDX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD -0x8(%RSI,%RDX,8),%YMM17,%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%RCX,%RDX,8),%YMM17,%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM19,%YMM22,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM17,%YMM23,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM21,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VDIVPD %YMM18,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VCMPPD $0x5,%YMM16,%YMM17,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 424c9a <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x72a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VCMPPD $0x1,%YMM16,%YMM17,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KORTESTB %K1,%K1	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 424ad0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x560>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end