OV - exec - Function ideal_gas_kernel_module_mp_ideal_gas_kernel

	Function: ideal_gas_kernel_module_mp_ideal_gas_kernel_.DIR.OMP.PARALLEL.2	Module: exec	Source: ideal_gas_kernel.f90:45-58	Coverage (incl. loops): 5.21% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90: 45 - 58

--------------------------------------------------------------------------------

45:     !$OMP PARALLEL

46:     !$OMP DO PRIVATE(v,pressurebyenergy,pressurebyvolume,sound_speed_squared)

47:     DO k=y_min,y_max

48:     !$OMP SIMD

49:       DO j=x_min,x_max

50:         v=1.0_8/density(j,k)

51:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

52:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

53:         pressurebyvolume=-density(j,k)*pressure(j,k)

54:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

55:         soundspeed(j,k)=SQRT(sound_speed_squared)

56:       ENDDO

57:     ENDDO

58:   !$OMP END DO

0x42a940 PUSH	%RBP

0x42a941 MOV	%RSP,%RBP

0x42a944 PUSH	%R15

0x42a946 PUSH	%R14

0x42a948 PUSH	%R13

0x42a94a PUSH	%R12

0x42a94c PUSH	%RBX

0x42a94d SUB	$0x98,%RSP

0x42a954 MOV	%R9,-0x60(%RBP)

0x42a958 MOV	%R8,-0x58(%RBP)

0x42a95c MOV	%RCX,%RBX

0x42a95f MOV	0x58(%RBP),%RAX

0x42a963 MOV	%RAX,-0xb8(%RBP)

0x42a96a MOV	0x50(%RBP),%RAX

0x42a96e MOV	%RAX,-0xb0(%RBP)

0x42a975 MOV	0x48(%RBP),%RAX

0x42a979 MOV	%RAX,-0xa8(%RBP)

0x42a980 MOV	0x40(%RBP),%RAX

0x42a984 MOV	%RAX,-0xa0(%RBP)

0x42a98b MOV	0x38(%RBP),%R13

0x42a98f MOV	0x30(%RBP),%R14

0x42a993 MOV	0x28(%RBP),%R12D

0x42a997 MOV	0x20(%RBP),%EAX

0x42a99a SUB	%R12D,%EAX

0x42a99d MOV	0x18(%RBP),%RCX

0x42a9a1 MOV	%RCX,-0x50(%RBP)

0x42a9a5 MOV	0x10(%RBP),%RCX

0x42a9a9 MOV	%RCX,-0x48(%RBP)

0x42a9ad MOVL	$0,-0x40(%RBP)

0x42a9b4 JS	42aa1d

0x42a9b6 MOV	%RDX,%R15

0x42a9b9 MOV	%RDI,-0x70(%RBP)

0x42a9bd MOV	(%RDI),%ESI

0x42a9bf MOVL	$0,-0x34(%RBP)

0x42a9c6 MOV	%EAX,-0x30(%RBP)

0x42a9c9 MOVL	$0x1,-0x3c(%RBP)

0x42a9d0 SUB	$0x8,%RSP

0x42a9d4 LEA	-0x3c(%RBP),%RAX

0x42a9d8 LEA	-0x40(%RBP),%RCX

0x42a9dc LEA	-0x34(%RBP),%R8

0x42a9e0 LEA	-0x30(%RBP),%R9

0x42a9e4 MOV	$0x538e70,%EDI

0x42a9e9 MOV	%ESI,-0x38(%RBP)

0x42a9ec MOV	$0x22,%EDX

0x42a9f1 PUSH	$0x1

0x42a9f3 PUSH	$0x1

0x42a9f5 PUSH	%RAX

0x42a9f6 CALL	404670 <__kmpc_for_static_init_4@plt>

0x42a9fb ADD	$0x20,%RSP

0x42a9ff MOV	-0x34(%RBP),%EAX

0x42aa02 MOV	-0x30(%RBP),%ECX

0x42aa05 SUB	%EAX,%ECX

0x42aa07 JAE	42aa3a

0x42aa09 MOV	$0x538e90,%EDI

0x42aa0e MOV	-0x38(%RBP),%ESI

0x42aa11 VZEROUPPER

0x42aa14 CALL	404230 <__kmpc_for_static_fini@plt>

0x42aa19 MOV	-0x70(%RBP),%RDI

0x42aa1d MOV	(%RDI),%ESI

0x42aa1f MOV	$0x538eb0,%EDI

0x42aa24 ADD	$0x98,%RSP

0x42aa2b POP	%RBX

0x42aa2c POP	%R12

0x42aa2e POP	%R13

0x42aa30 POP	%R14

0x42aa32 POP	%R15

0x42aa34 POP	%RBP

0x42aa35 JMP	404740

0x42aa3a SAL	$0x20,%RBX

0x42aa3e MOV	%ECX,-0x2c(%RBP)

0x42aa41 MOV	%RBX,%RSI

0x42aa44 MOV	$-0x200000000,%RBX

0x42aa4e LEA	(%RSI,%RBX,1),%RDX

0x42aa52 MOV	%RDX,%R11

0x42aa55 SAR	$0x20,%R11

0x42aa59 SAL	$0x20,%R15

0x42aa5d ADD	%R15,%RBX

0x42aa60 MOVSXD	(%R13),%R10

0x42aa64 MOV	(%R14),%ECX

0x42aa67 SUB	%R10D,%ECX

0x42aa6a MOV	%RCX,-0xc0(%RBP)

0x42aa71 INC	%ECX

0x42aa73 CMP	$0x2,%ECX

0x42aa76 MOV	$0x1,%R8D

0x42aa7c CMOVGE	%ECX,%R8D

0x42aa80 MOV	%R8,-0x68(%RBP)

0x42aa84 AND	$0x7ffffffc,%R8D

0x42aa8b TEST	%RDX,%RDX

0x42aa8e MOV	$-0x1,%RCX

0x42aa95 CMOVNS	%RDX,%RCX

0x42aa99 TEST	%RCX,%RCX

0x42aa9c MOV	$0x1,%R13D

0x42aaa2 CMOVG	%R13,%RCX

0x42aaa6 MOV	$0x200000000,%R9

0x42aab0 MOV	%R9,%RDI

0x42aab3 SUB	%RSI,%RDI

0x42aab6 CMP	%RDI,%RDX

0x42aab9 CMOVG	%RDX,%RDI

0x42aabd SHR	$0x20,%RDI

0x42aac1 IMUL	%RCX,%RDI

0x42aac5 LEA	(,%R10,8),%R14

0x42aacd SAL	$0x3,%RDI

0x42aad1 SUB	%RDI,%R14

0x42aad4 MOV	$-0x1,%RCX

0x42aadb TEST	%RBX,%RBX

0x42aade CMOVNS	%RBX,%RCX

0x42aae2 TEST	%RCX,%RCX

0x42aae5 CMOVG	%R13,%RCX

0x42aae9 SUB	%R15,%R9

0x42aaec CMP	%R9,%RBX

0x42aaef CMOVG	%RBX,%R9

0x42aaf3 MOV	-0x2c(%RBP),%EBX

0x42aaf6 MOV	-0x58(%RBP),%RDX

0x42aafa ADD	%R14,%RDX

0x42aafd MOV	%RDX,-0x88(%RBP)

0x42ab04 SHR	$0x20,%R9

0x42ab08 IMUL	%RCX,%R9

0x42ab0c NEG	%R9

0x42ab0f ADD	%R12D,%EAX

0x42ab12 MOV	-0x60(%RBP),%RCX

0x42ab16 ADD	%R14,%RCX

0x42ab19 MOV	%RCX,-0x80(%RBP)

0x42ab1d MOV	-0x48(%RBP),%RCX

0x42ab21 ADD	%R14,%RCX

0x42ab24 MOV	%RCX,-0x78(%RBP)

0x42ab28 ADD	-0x50(%RBP),%R14

0x42ab2c MOV	%R14,-0x90(%RBP)

0x42ab33 SUB	%R11,%R10

0x42ab36 MOV	%R10,-0x98(%RBP)

0x42ab3d XOR	%R12D,%R12D

0x42ab40 VMOVSD	0xcb760(%RIP),%XMM0

0x42ab48 VMOVSD	0xd1bb8(%RIP),%XMM1

0x42ab50 VMOVSD	0xd1bb8(%RIP),%XMM2

0x42ab58 VBROADCASTSD	0xcb747(%RIP),%YMM3

0x42ab61 VBROADCASTSD	0xd1b9e(%RIP),%YMM4

0x42ab6a VBROADCASTSD	0xd1b9d(%RIP),%YMM5

0x42ab73 JMP	42ab93

0x42ab75 NOPW	%CS:(%RAX,%RAX,1)

(231) 0x42ab80 LEA	0x1(%R12),%ECX

(231) 0x42ab85 INC	%EAX

(231) 0x42ab87 CMP	%EBX,%R12D

(231) 0x42ab8a MOV	%ECX,%R12D

(231) 0x42ab8d JE	42aa09

(231) 0x42ab93 CMPL	$0,-0xc0(%RBP)

(231) 0x42ab9a JS	42ab80

(231) 0x42ab9c MOVSXD	%EAX,%R11

(231) 0x42ab9f ADD	%R9,%R11

(231) 0x42aba2 MOV	-0xa0(%RBP),%RCX

(231) 0x42aba9 MOV	(%RCX),%RCX

(231) 0x42abac MOV	-0xa8(%RBP),%RDX

(231) 0x42abb3 MOV	(%RDX),%R15

(231) 0x42abb6 MOV	-0xb0(%RBP),%RDX

(231) 0x42abbd MOV	(%RDX),%R10

(231) 0x42abc0 MOV	-0xb8(%RBP),%RDX

(231) 0x42abc7 MOV	(%RDX),%RDX

(231) 0x42abca TEST	%R8,%R8

(231) 0x42abcd JE	42ac60

(231) 0x42abd3 MOV	%RDX,%RDI

(231) 0x42abd6 IMUL	%R11,%RDI

(231) 0x42abda ADD	-0x88(%RBP),%RDI

(231) 0x42abe1 MOV	%R10,%R14

(231) 0x42abe4 IMUL	%R11,%R14

(231) 0x42abe8 ADD	-0x80(%RBP),%R14

(231) 0x42abec MOV	%R15,%R13

(231) 0x42abef IMUL	%R11,%R13

(231) 0x42abf3 ADD	-0x78(%RBP),%R13

(231) 0x42abf7 MOV	%RCX,%RBX

(231) 0x42abfa IMUL	%R11,%RBX

(231) 0x42abfe ADD	-0x90(%RBP),%RBX

(231) 0x42ac05 XOR	%ESI,%ESI

(231) 0x42ac07 NOPW	(%RAX,%RAX,1)

  (233) 0x42ac10 VMOVUPD	(%RBX,%RSI,8),%YMM6

  (233) 0x42ac15 VMULPD	%YMM4,%YMM6,%YMM7

  (233) 0x42ac19 VMULPD	(%R13,%RSI,8),%YMM7,%YMM7

  (233) 0x42ac20 VDIVPD	%YMM6,%YMM3,%YMM8

  (233) 0x42ac24 VMOVUPD	%YMM7,(%R14,%RSI,8)

  (233) 0x42ac2a VMULPD	%YMM8,%YMM8,%YMM8

  (233) 0x42ac2f VMULPD	%YMM5,%YMM6,%YMM6

  (233) 0x42ac33 VMULPD	%YMM7,%YMM6,%YMM6

  (233) 0x42ac37 VMULPD	%YMM6,%YMM8,%YMM6

  (233) 0x42ac3b VSQRTPD	%YMM6,%YMM6

  (233) 0x42ac3f VMOVUPD	%YMM6,(%RDI,%RSI,8)

  (233) 0x42ac44 ADD	$0x4,%RSI

  (233) 0x42ac48 CMP	%R8,%RSI

  (233) 0x42ac4b JB	42ac10

(231) 0x42ac4d MOV	%R8,%R13

(231) 0x42ac50 CMP	-0x68(%RBP),%R8

(231) 0x42ac54 MOV	-0x2c(%RBP),%EBX

(231) 0x42ac57 JE	42ab80

(231) 0x42ac5d JMP	42ac63

0x42ac5f NOP

(231) 0x42ac60 XOR	%R13D,%R13D

(231) 0x42ac63 MOV	-0x68(%RBP),%RDI

(231) 0x42ac67 SUB	%R13,%RDI

(231) 0x42ac6a IMUL	%R11,%RDX

(231) 0x42ac6e ADD	-0x98(%RBP),%R13

(231) 0x42ac75 LEA	(%RDX,%R13,8),%RDX

(231) 0x42ac79 ADD	-0x58(%RBP),%RDX

(231) 0x42ac7d IMUL	%R11,%R10

(231) 0x42ac81 LEA	(%R10,%R13,8),%R14

(231) 0x42ac85 ADD	-0x60(%RBP),%R14

(231) 0x42ac89 IMUL	%R11,%R15

(231) 0x42ac8d LEA	(%R15,%R13,8),%R10

(231) 0x42ac91 ADD	-0x48(%RBP),%R10

(231) 0x42ac95 IMUL	%R11,%RCX

(231) 0x42ac99 LEA	(%RCX,%R13,8),%RCX

(231) 0x42ac9d ADD	-0x50(%RBP),%RCX

(231) 0x42aca1 XOR	%ESI,%ESI

(231) 0x42aca3 NOPW	%CS:(%RAX,%RAX,1)

  (232) 0x42acb0 VMOVSD	(%RCX,%RSI,8),%XMM6

  (232) 0x42acb5 VMULSD	%XMM1,%XMM6,%XMM7

  (232) 0x42acb9 VMULSD	(%R10,%RSI,8),%XMM7,%XMM7

  (232) 0x42acbf VDIVSD	%XMM6,%XMM0,%XMM8

  (232) 0x42acc3 VMOVSD	%XMM7,(%R14,%RSI,8)

  (232) 0x42acc9 VMULSD	%XMM8,%XMM8,%XMM8

  (232) 0x42acce VMULSD	%XMM2,%XMM6,%XMM6

  (232) 0x42acd2 VMULSD	%XMM7,%XMM6,%XMM6

  (232) 0x42acd6 VMULSD	%XMM6,%XMM8,%XMM6

  (232) 0x42acda VSQRTSD	%XMM6,%XMM6,%XMM6

  (232) 0x42acde VMOVSD	%XMM6,(%RDX,%RSI,8)

  (232) 0x42ace3 INC	%RSI

  (232) 0x42ace6 CMP	%RSI,%RDI

  (232) 0x42ace9 JNE	42acb0

(231) 0x42aceb JMP	42ab80

Coverage (%)	Name	Source Location	Module
►51.19+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►36.60+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►5.64+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
►2.34+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
►1.98+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	ideal_gas_kernel	ideal_gas_kernel.f90:61	exec
○	ideal_gas	ideal_gas.f90:51	exec
○	timestep	timestep.f90:62	exec
○	hydro	hydro.f90:54	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.91+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	ideal_gas_kernel	ideal_gas_kernel.f90:61	exec
○	ideal_gas	ideal_gas.f90:51	exec
○	pdv	PdV.f90:126	exec
○	hydro	hydro.f90:56	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	ideal_gas_kernel.f90:45-58
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-58.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.00 to 1.75 cycles (10.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:58
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:48

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVG: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:47
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:47
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:47
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:47
CMOVGE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:49

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 192 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	139
nb uops	144
loop length	577
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	0
nb stack references	32

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.67	11.67	11.67	11.67	11.67	11.67	13.25	13.25	13.25	13.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	11.67	11.67	11.67	11.67	11.67	11.67	13.25	13.25	13.25	13.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.00
Dispatch	13.25
Overall L1	18.00

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	10%
load	10%
store	10%
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	10%
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

4% of peak load performance is reached (10.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.00 to 13.25 cycles (1.36x speedup).

ASM code

In the binary file, the address of the function is: 42a940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x38(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x18(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
JS 42aa1d <ideal_gas_kernel_module_mp_ideal_gas_kernel_.DIR.OMP.PARALLEL.2+0xdd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x3c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x538e70,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404670 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x34(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x30(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
SUB %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42aa3a <ideal_gas_kernel_module_mp_ideal_gas_kernel_.DIR.OMP.PARALLEL.2+0xfa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV $0x538e90,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404230 <__kmpc_for_static_fini@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV $0x538eb0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 404740 <__kmpc_barrier@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
SAL $0x20,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %ECX,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $-0x200000000,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RBX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAR $0x20,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
SAL $0x20,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
ADD %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD (%R13),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV (%R14),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
SUB %R10D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP $0x2,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x1,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVGE %ECX,%R8D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV %R8,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
AND $0x7ffffffc,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVNS %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
TEST %RCX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMOVG %R13,%RCX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x200000000,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %RDX,%RDI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
SHR $0x20,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
IMUL %RCX,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (,%R10,8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SAL $0x3,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
SUB %RDI,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVNS %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
TEST %RCX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %R13,%RCX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
SUB %R15,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMP %R9,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %RBX,%R9	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x2c(%RBP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
ADD %R14,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SHR $0x20,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
IMUL %RCX,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
NEG %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
ADD %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
ADD %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD -0x50(%RBP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R14,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB %R11,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R10,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVSD 0xcb760(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0xd1bb8(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0xd1bb8(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VBROADCASTSD 0xcb747(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
VBROADCASTSD 0xd1b9e(%RIP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
VBROADCASTSD 0xd1b9d(%RIP),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 42ab93 <ideal_gas_kernel_module_mp_ideal_gas_kernel_.DIR.OMP.PARALLEL.2+0x253>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	ideal_gas_kernel.f90:45-58
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:58
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:48

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVG: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:47
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:47
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:47
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:47
CMOVGE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:49

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 192 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	139
nb uops	144
loop length	577
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	0
nb stack references	32

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.67	11.67	11.67	11.67	11.67	11.67	13.25	13.25	13.25	13.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	11.67	11.67	11.67	11.67	11.67	11.67	13.25	13.25	13.25	13.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.00
Dispatch	13.25
Overall L1	18.00

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	10%
load	10%
store	10%
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	10%
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

4% of peak load performance is reached (10.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42a940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x38(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x18(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
JS 42aa1d <ideal_gas_kernel_module_mp_ideal_gas_kernel_.DIR.OMP.PARALLEL.2+0xdd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x3c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x538e70,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404670 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x34(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x30(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
SUB %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42aa3a <ideal_gas_kernel_module_mp_ideal_gas_kernel_.DIR.OMP.PARALLEL.2+0xfa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV $0x538e90,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404230 <__kmpc_for_static_fini@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV $0x538eb0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 404740 <__kmpc_barrier@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
SAL $0x20,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %ECX,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $-0x200000000,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RBX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAR $0x20,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
SAL $0x20,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
ADD %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD (%R13),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV (%R14),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
SUB %R10D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP $0x2,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x1,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVGE %ECX,%R8D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV %R8,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
AND $0x7ffffffc,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVNS %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
TEST %RCX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMOVG %R13,%RCX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x200000000,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %RDX,%RDI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
SHR $0x20,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
IMUL %RCX,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (,%R10,8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SAL $0x3,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
SUB %RDI,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $-0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVNS %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
TEST %RCX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %R13,%RCX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
SUB %R15,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMP %R9,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %RBX,%R9	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x2c(%RBP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
ADD %R14,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SHR $0x20,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
IMUL %RCX,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
NEG %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
ADD %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
ADD %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD -0x50(%RBP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R14,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB %R11,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R10,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVSD 0xcb760(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0xd1bb8(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0xd1bb8(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VBROADCASTSD 0xcb747(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
VBROADCASTSD 0xd1b9e(%RIP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
VBROADCASTSD 0xd1b9d(%RIP),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 42ab93 <ideal_gas_kernel_module_mp_ideal_gas_kernel_.DIR.OMP.PARALLEL.2+0x253>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼ideal_gas_kernel_module_mp_ideal_gas_kernel_.DIR.OMP.PARALLEL.2–	5.21	2.07
▼Loop 231 - ideal_gas_kernel.f90:47-55 - exec–	0.00	0.01
○Loop 233 - ideal_gas_kernel.f90:49-55 - exec	5.20	2.06
○Loop 232 - ideal_gas_kernel.f90:49-55 - exec	0.00	0.00

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