OV - exec - Function calc_dt_kernel_module_mp_calc_dt_kernel

	Function: calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2	Module: exec	Source: calc_dt_kernel.f90:89-133	Coverage (incl. loops): 3.32% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 133

--------------------------------------------------------------------------------

89:     !$OMP PARALLEL

90:

91:     !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val)

92:     DO k=y_min,y_max

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

130:

131:       ENDDO

132:     ENDDO

133:     !$OMP END DO

0x424570 PUSH	%RBP

0x424571 MOV	%RSP,%RBP

0x424574 PUSH	%R15

0x424576 PUSH	%R14

0x424578 PUSH	%R13

0x42457a PUSH	%R12

0x42457c PUSH	%RBX

0x42457d SUB	$0x168,%RSP

0x424584 MOV	%R9,-0x70(%RBP)

0x424588 MOV	0x90(%RBP),%EBX

0x42458e MOV	0x88(%RBP),%EAX

0x424594 SUB	%EBX,%EAX

0x424596 MOVL	$0,-0x5c(%RBP)

0x42459d JS	424696

0x4245a3 MOV	%RCX,%R14

0x4245a6 MOV	%RDX,%R13

0x4245a9 MOV	%R8,-0xa0(%RBP)

0x4245b0 MOV	%RDI,-0x68(%RBP)

0x4245b4 MOV	(%RDI),%ESI

0x4245b6 MOVL	$0,-0x30(%RBP)

0x4245bd MOV	%EAX,-0x2c(%RBP)

0x4245c0 MOVL	$0x1,-0x58(%RBP)

0x4245c7 SUB	$0x8,%RSP

0x4245cb LEA	-0x58(%RBP),%RAX

0x4245cf LEA	-0x5c(%RBP),%RCX

0x4245d3 LEA	-0x30(%RBP),%R8

0x4245d7 LEA	-0x2c(%RBP),%R9

0x4245db MOV	$0x5383d0,%EDI

0x4245e0 MOV	%ESI,-0x4c(%RBP)

0x4245e3 MOV	$0x22,%EDX

0x4245e8 PUSH	$0x1

0x4245ea PUSH	$0x1

0x4245ec PUSH	%RAX

0x4245ed CALL	404670 <__kmpc_for_static_init_4@plt>

0x4245f2 ADD	$0x20,%RSP

0x4245f6 MOV	-0x30(%RBP),%R8D

0x4245fa MOV	-0x2c(%RBP),%EAX

0x4245fd SUB	%R8D,%EAX

0x424600 MOV	%EAX,-0x50(%RBP)

0x424603 JAE	4246b4

0x424609 VMOVSD	0xd60ff(%RIP),%XMM10

0x424611 VMOVSD	%XMM10,-0x98(%RBP)

0x424619 MOV	$0x5383f0,%EDI

0x42461e MOV	-0x4c(%RBP),%ESI

0x424621 VZEROUPPER

0x424624 CALL	404230 <__kmpc_for_static_fini@plt>

0x424629 MOV	-0x68(%RBP),%RBX

0x42462d MOV	(%RBX),%ESI

0x42462f SUB	$0x8,%RSP

0x424633 MOV	$0x591060,%RAX

0x42463a LEA	-0x98(%RBP),%R8

0x424641 MOV	$0x538410,%EDI

0x424646 MOV	$0x424560,%R9D

0x42464c MOV	$0x1,%EDX

0x424651 MOV	$0x8,%ECX

0x424656 PUSH	%RAX

0x424657 CALL	404830 <__kmpc_reduce@plt>

0x42465c MOV	%RBX,%RDI

0x42465f ADD	$0x10,%RSP

0x424663 CMP	$0x1,%EAX

0x424666 MOV	-0xa0(%RBP),%RAX

0x42466d JNE	424696

0x42466f VMOVSD	-0x98(%RBP),%XMM0

0x424677 VMINSD	(%RAX),%XMM0,%XMM0

0x42467b VMOVSD	%XMM0,(%RAX)

0x42467f MOV	(%RDI),%ESI

0x424681 MOV	$0x591060,%RDX

0x424688 MOV	$0x538430,%EDI

0x42468d CALL	4049b0 <__kmpc_end_reduce@plt>

0x424692 MOV	-0x68(%RBP),%RDI

0x424696 MOV	(%RDI),%ESI

0x424698 MOV	$0x538450,%EDI

0x42469d CALL	404740 <__kmpc_barrier@plt>

0x4246a2 ADD	$0x168,%RSP

0x4246a9 POP	%RBX

0x4246aa POP	%R12

0x4246ac POP	%R13

0x4246ae POP	%R14

0x4246b0 POP	%R15

0x4246b2 POP	%RBP

0x4246b3 RET

0x4246b4 MOV	0xa0(%RBP),%RSI

0x4246bb MOV	0x98(%RBP),%RCX

0x4246c2 SAL	$0x20,%R14

0x4246c6 MOV	$-0x200000000,%RAX

0x4246d0 LEA	(%R14,%RAX,1),%RDX

0x4246d4 MOV	%RDX,%R9

0x4246d7 SAR	$0x20,%R9

0x4246db SAL	$0x20,%R13

0x4246df ADD	%R13,%RAX

0x4246e2 MOV	%RAX,%R10

0x4246e5 SAR	$0x20,%R10

0x4246e9 MOVSXD	(%RSI),%R11

0x4246ec MOV	(%RCX),%ECX

0x4246ee SUB	%R11D,%ECX

0x4246f1 ADD	%EBX,%R8D

0x4246f4 MOV	%RCX,-0x170(%RBP)

0x4246fb INC	%ECX

0x4246fd CMP	$0x2,%ECX

0x424700 MOV	$0x1,%ESI

0x424705 CMOVGE	%ECX,%ESI

0x424708 MOV	%RSI,-0x78(%RBP)

0x42470c AND	$0x7ffffffc,%ESI

0x424712 MOV	%RSI,-0x40(%RBP)

0x424716 TEST	%RDX,%RDX

0x424719 MOV	$-0x1,%RSI

0x424720 CMOVNS	%RDX,%RSI

0x424724 TEST	%RSI,%RSI

0x424727 MOV	$0x1,%EDI

0x42472c CMOVG	%RDI,%RSI

0x424730 MOV	$0x200000000,%RBX

0x42473a MOV	%RBX,%RCX

0x42473d SUB	%R14,%RCX

0x424740 CMP	%RCX,%RDX

0x424743 CMOVG	%RDX,%RCX

0x424747 LEA	(,%R11,8),%R14

0x42474f SHR	$0x20,%RCX

0x424753 IMUL	%RSI,%RCX

0x424757 SAL	$0x3,%RCX

0x42475b SUB	%RCX,%R14

0x42475e MOV	$0x1,%EDX

0x424763 MOV	%R10,-0x128(%RBP)

0x42476a SUB	%R10,%RDX

0x42476d MOV	%RDX,-0x118(%RBP)

0x424774 TEST	%RAX,%RAX

0x424777 MOV	$-0x1,%RDX

0x42477e CMOVNS	%RAX,%RDX

0x424782 TEST	%RDX,%RDX

0x424785 CMOVG	%RDI,%RDX

0x424789 SUB	%R13,%RBX

0x42478c MOV	0x50(%RBP),%RSI

0x424790 CMP	%RBX,%RAX

0x424793 CMOVG	%RAX,%RBX

0x424797 MOV	0x48(%RBP),%RDI

0x42479b SHR	$0x20,%RBX

0x42479f IMUL	%RDX,%RBX

0x4247a3 MOV	$0x8,%EDX

0x4247a8 SUB	%RCX,%RDX

0x4247ab NEG	%RBX

0x4247ae MOV	%RBX,-0x120(%RBP)

0x4247b5 MOV	0x30(%RBP),%RCX

0x4247b9 MOV	0x28(%RBP),%R10

0x4247bd MOV	0x20(%RBP),%RBX

0x4247c1 MOV	0x18(%RBP),%R15

0x4247c5 MOV	0x10(%RBP),%R12

0x4247c9 MOV	-0x70(%RBP),%RAX

0x4247cd LEA	0x8(%RAX,%R14,1),%R13

0x4247d2 MOV	%R13,-0xe0(%RBP)

0x4247d9 LEA	0x8(%RSI,%R14,1),%R13

0x4247de MOV	%R13,-0xd8(%RBP)

0x4247e5 LEA	0x8(%R12,%R14,1),%R13

0x4247ea MOV	%R13,-0xd0(%RBP)

0x4247f1 LEA	(%RDI,%R14,1),%RDI

0x4247f5 MOV	%RDI,-0xc8(%RBP)

0x4247fc ADD	%R14,%RCX

0x4247ff MOV	%RCX,-0xc0(%RBP)

0x424806 LEA	(%R10,%R14,1),%RCX

0x42480a MOV	%RCX,-0xb8(%RBP)

0x424811 LEA	(%RBX,%R14,1),%RCX

0x424815 MOV	%RCX,-0xb0(%RBP)

0x42481c LEA	(%R15,%R14,1),%RCX

0x424820 MOV	%RCX,-0xa8(%RBP)

0x424827 ADD	0x40(%RBP),%R14

0x42482b MOV	%R14,-0x190(%RBP)

0x424832 ADD	%RDX,%RAX

0x424835 MOV	%RAX,-0xf8(%RBP)

0x42483c LEA	(%RSI,%RDX,1),%RAX

0x424840 MOV	%RAX,-0xf0(%RBP)

0x424847 ADD	%R12,%RDX

0x42484a MOV	%RDX,-0x100(%RBP)

0x424851 MOV	%R11,-0x108(%RBP)

0x424858 MOV	%R9,-0x110(%RBP)

0x42485f SUB	%R9,%R11

0x424862 MOV	%R11,-0xe8(%RBP)

0x424869 VMOVSD	0xd5e9f(%RIP),%XMM10

0x424871 VMOVDDUP	0xd2b8f(%RIP),%XMM0

0x424879 VMOVDDUP	0xd189f(%RIP),%XMM1

0x424881 VBROADCASTSD	0xd1896(%RIP),%YMM2

0x42488a VBROADCASTSD	0xd2b75(%RIP),%YMM3

0x424893 XOR	%EDX,%EDX

0x424895 MOV	%R8D,%ECX

0x424898 MOV	%R8,-0x178(%RBP)

0x42489f JMP	4248d1

0x4248a1 NOPW	%CS:(%RAX,%RAX,1)

(165) 0x4248b0 MOV	-0x188(%RBP),%RDX

(165) 0x4248b7 LEA	0x1(%RDX),%EAX

(165) 0x4248ba MOV	-0x54(%RBP),%ECX

(165) 0x4248bd INC	%ECX

(165) 0x4248bf CMP	-0x50(%RBP),%EDX

(165) 0x4248c2 MOV	%EAX,%EDX

(165) 0x4248c4 MOV	-0x178(%RBP),%R8

(165) 0x4248cb JE	424611

(165) 0x4248d1 CMPL	$0,-0x170(%RBP)

(165) 0x4248d8 MOV	%ECX,-0x54(%RBP)

(165) 0x4248db MOV	%RDX,-0x188(%RBP)

(165) 0x4248e2 JS	4248b0

(165) 0x4248e4 MOVSXD	%ECX,%RBX

(165) 0x4248e7 MOV	-0x118(%RBP),%RAX

(165) 0x4248ee LEA	(%RAX,%RBX,1),%RDI

(165) 0x4248f2 ADD	-0x120(%RBP),%RBX

(165) 0x4248f9 LEA	(%R8,%RDX,1),%EAX

(165) 0x4248fd MOVSXD	%EAX,%R11

(165) 0x424900 SUB	-0x128(%RBP),%R11

(165) 0x424907 MOV	0x38(%RBP),%RAX

(165) 0x42490b VMOVSD	(%RAX,%R11,8),%XMM4

(165) 0x424911 MOV	0xa8(%RBP),%RAX

(165) 0x424918 MOV	(%RAX),%R10

(165) 0x42491b MOV	0xb0(%RBP),%RAX

(165) 0x424922 MOV	(%RAX),%RAX

(165) 0x424925 MOV	%RAX,-0x38(%RBP)

(165) 0x424929 MOV	0x80(%RBP),%RAX

(165) 0x424930 VMOVSD	(%RAX),%XMM5

(165) 0x424934 MOV	0x70(%RBP),%RAX

(165) 0x424938 VMOVSD	(%RAX),%XMM6

(165) 0x42493c MOV	0xb8(%RBP),%RAX

(165) 0x424943 MOV	(%RAX),%R14

(165) 0x424946 MOV	0xc0(%RBP),%RAX

(165) 0x42494d MOV	(%RAX),%R15

(165) 0x424950 MOV	0xc8(%RBP),%RAX

(165) 0x424957 MOV	(%RAX),%R8

(165) 0x42495a MOV	0x68(%RBP),%RAX

(165) 0x42495e VMOVSD	(%RAX),%XMM7

(165) 0x424962 MOV	0xd0(%RBP),%RAX

(165) 0x424969 MOV	(%RAX),%R12

(165) 0x42496c MOV	0xd8(%RBP),%RAX

(165) 0x424973 MOV	(%RAX),%R9

(165) 0x424976 MOV	0xe0(%RBP),%RAX

(165) 0x42497d MOV	(%RAX),%R13

(165) 0x424980 MOV	0x60(%RBP),%RAX

(165) 0x424984 VMOVSD	(%RAX),%XMM8

(165) 0x424988 VXORPD	%XMM0,%XMM5,%XMM9

(165) 0x42498c CMPQ	$0,-0x40(%RBP)

(165) 0x424991 MOV	%R10,-0x48(%RBP)

(165) 0x424995 MOV	%R12,-0x180(%RBP)

(165) 0x42499c JE	424d60

(165) 0x4249a2 VBROADCASTSD	%XMM10,%YMM13

(165) 0x4249a7 VBROADCASTSD	%XMM5,%YMM10

(165) 0x4249ac VBROADCASTSD	%XMM4,%YMM11

(165) 0x4249b1 VBROADCASTSD	%XMM6,%YMM12

(165) 0x4249b6 LEA	0x1(%R11),%RCX

(165) 0x4249ba MOV	%R15,%RAX

(165) 0x4249bd IMUL	%RCX,%RAX

(165) 0x4249c1 MOV	%RAX,-0x130(%RBP)

(165) 0x4249c8 MOV	%R15,%RAX

(165) 0x4249cb IMUL	%R11,%RAX

(165) 0x4249cf MOV	%RAX,-0x90(%RBP)

(165) 0x4249d6 MOV	%R8,%RAX

(165) 0x4249d9 IMUL	%R11,%RAX

(165) 0x4249dd MOV	%RAX,-0x80(%RBP)

(165) 0x4249e1 VBROADCASTSD	%XMM7,%YMM14

(165) 0x4249e6 IMUL	%R9,%R11

(165) 0x4249ea IMUL	%R9,%RCX

(165) 0x4249ee MOV	%RCX,-0x88(%RBP)

(165) 0x4249f5 VBROADCASTSD	%XMM8,%YMM15

(165) 0x4249fa VBROADCASTSD	%XMM9,%YMM16

(165) 0x424a00 MOV	%R9,%RSI

(165) 0x424a03 IMUL	%RDI,%RSI

(165) 0x424a07 MOV	-0xe0(%RBP),%RAX

(165) 0x424a0e ADD	%RAX,%RSI

(165) 0x424a11 MOV	%R9,-0x138(%RBP)

(165) 0x424a18 IMUL	%RBX,%R9

(165) 0x424a1c ADD	%RAX,%R9

(165) 0x424a1f MOV	%R8,-0x140(%RBP)

(165) 0x424a26 IMUL	%RBX,%R8

(165) 0x424a2a ADD	-0xd8(%RBP),%R8

(165) 0x424a31 MOV	%RBX,%RDX

(165) 0x424a34 MOV	%R15,%RBX

(165) 0x424a37 IMUL	%RDX,%RBX

(165) 0x424a3b MOV	-0xd0(%RBP),%RAX

(165) 0x424a42 ADD	%RAX,%RBX

(165) 0x424a45 MOV	%R15,-0x148(%RBP)

(165) 0x424a4c IMUL	%RDI,%R15

(165) 0x424a50 ADD	%RAX,%R15

(165) 0x424a53 MOV	%R13,%RCX

(165) 0x424a56 MOV	%RDI,-0x168(%RBP)

(165) 0x424a5d IMUL	%RDI,%RCX

(165) 0x424a61 MOV	-0xc8(%RBP),%RAX

(165) 0x424a68 ADD	%RAX,%RCX

(165) 0x424a6b MOV	%R13,-0x150(%RBP)

(165) 0x424a72 IMUL	%RDX,%R13

(165) 0x424a76 ADD	%RAX,%R13

(165) 0x424a79 IMUL	%RDX,%R12

(165) 0x424a7d ADD	-0xc0(%RBP),%R12

(165) 0x424a84 MOV	%R14,-0x158(%RBP)

(165) 0x424a8b MOV	%R14,%RAX

(165) 0x424a8e IMUL	%RDX,%RAX

(165) 0x424a92 ADD	-0xb8(%RBP),%RAX

(165) 0x424a99 MOV	-0x38(%RBP),%R14

(165) 0x424a9d IMUL	%RDX,%R14

(165) 0x424aa1 ADD	-0xb0(%RBP),%R14

(165) 0x424aa8 MOV	%RDX,-0x160(%RBP)

(165) 0x424aaf IMUL	%RDX,%R10

(165) 0x424ab3 ADD	-0xa8(%RBP),%R10

(165) 0x424aba XOR	%EDX,%EDX

(165) 0x424abc JMP	424bf5

0x424ac1 NOPW	%CS:(%RAX,%RAX,1)

  (167) 0x424ad0 MOV	-0x190(%RBP),%RDI

  (167) 0x424ad7 VMOVUPD	(%RDI,%RDX,8),%YMM26

  (167) 0x424ade VMOVUPD	(%R10,%RDX,8),%YMM27

  (167) 0x424ae5 VMOVUPD	(%R14,%RDX,8),%YMM28

  (167) 0x424aec VADDPD	%YMM28,%YMM28,%YMM28

  (167) 0x424af2 VDIVPD	(%RAX,%RDX,8),%YMM28,%YMM28

  (167) 0x424af9 VFMADD231PD	%YMM27,%YMM27,%YMM28

  (167) 0x424aff VSQRTPD	%YMM28,%YMM27

  (167) 0x424b05 VCMPPD	$0x2,%YMM27,%YMM10,%K2

  (167) 0x424b0c VBLENDMPD	%YMM27,%YMM10,%YMM27{%K2}

  (167) 0x424b12 VCMPPD	$0x2,%YMM11,%YMM26,%K2

  (167) 0x424b19 VBLENDMPD	%YMM26,%YMM11,%YMM26{%K2}

  (167) 0x424b1f VMULPD	%YMM26,%YMM12,%YMM26

  (167) 0x424b25 VDIVPD	%YMM27,%YMM26,%YMM26

  (167) 0x424b2b VMULPD	%YMM14,%YMM18,%YMM27

  (167) 0x424b31 VANDPD	%YMM2,%YMM22,%YMM22

  (167) 0x424b37 VANDPD	%YMM2,%YMM23,%YMM23

  (167) 0x424b3d VMULPD	%YMM10,%YMM24,%YMM24

  (167) 0x424b43 VCMPPD	$0x2,%YMM23,%YMM24,%K2

  (167) 0x424b4a VBLENDMPD	%YMM23,%YMM24,%YMM23{%K2}

  (167) 0x424b50 VCMPPD	$0x2,%YMM22,%YMM23,%K2

  (167) 0x424b57 VMOVAPD	%YMM22,%YMM23{%K2}

  (167) 0x424b5d VDIVPD	%YMM23,%YMM27,%YMM22

  (167) 0x424b63 VMULPD	%YMM15,%YMM18,%YMM18

  (167) 0x424b69 VANDPD	%YMM2,%YMM19,%YMM19

  (167) 0x424b6f VANDPD	%YMM2,%YMM21,%YMM21

  (167) 0x424b75 VCMPPD	$0x2,%YMM21,%YMM24,%K2

  (167) 0x424b7c VMOVAPD	%YMM21,%YMM24{%K2}

  (167) 0x424b82 VCMPPD	$0x2,%YMM19,%YMM24,%K2

  (167) 0x424b89 VMOVAPD	%YMM19,%YMM24{%K2}

  (167) 0x424b8f VDIVPD	%YMM24,%YMM18,%YMM19

  (167) 0x424b95 VBROADCASTSD	%XMM25,%YMM18

  (167) 0x424b9b VXORPD	%YMM3,%YMM18,%YMM21

  (167) 0x424ba1 VBROADCASTSD	%XMM20,%YMM18

  (167) 0x424ba7 VDIVPD	%YMM17,%YMM21,%YMM18{%K1}

  (167) 0x424bad VCMPPD	$0x2,%YMM18,%YMM19,%K1

  (167) 0x424bb4 VMOVAPD	%YMM19,%YMM18{%K1}

  (167) 0x424bba VCMPPD	$0x2,%YMM18,%YMM22,%K1

  (167) 0x424bc1 VMOVAPD	%YMM22,%YMM18{%K1}

  (167) 0x424bc7 VCMPPD	$0x2,%YMM18,%YMM26,%K1

  (167) 0x424bce VMOVAPD	%YMM26,%YMM18{%K1}

  (167) 0x424bd4 VCMPPD	$0x2,%YMM18,%YMM13,%K1

  (167) 0x424bdb VMOVAPD	%YMM13,%YMM18{%K1}

  (167) 0x424be1 ADD	$0x4,%RDX

  (167) 0x424be5 VMOVAPD	%YMM18,%YMM13

  (167) 0x424beb CMP	-0x40(%RBP),%RDX

  (167) 0x424bef JAE	424cc0

  (167) 0x424bf5 VMOVUPD	-0x8(%R15,%RDX,8),%YMM17

  (167) 0x424c00 VMOVUPD	(%R15,%RDX,8),%YMM18

  (167) 0x424c07 VADDPD	-0x8(%RBX,%RDX,8),%YMM17,%YMM17

  (167) 0x424c12 VMULPD	-0x8(%R8,%RDX,8),%YMM17,%YMM22

  (167) 0x424c1d VADDPD	(%RBX,%RDX,8),%YMM18,%YMM17

  (167) 0x424c24 VMULPD	(%R8,%RDX,8),%YMM17,%YMM23

  (167) 0x424c2b VMOVUPD	(%R12,%RDX,8),%YMM24

  (167) 0x424c32 VADDPD	%YMM24,%YMM24,%YMM18

  (167) 0x424c38 VMOVUPD	(%R9,%RDX,8),%YMM17

  (167) 0x424c3f VADDPD	-0x8(%R9,%RDX,8),%YMM17,%YMM17

  (167) 0x424c4a VMULPD	(%R13,%RDX,8),%YMM17,%YMM19

  (167) 0x424c52 VMOVUPD	(%RSI,%RDX,8),%YMM17

  (167) 0x424c59 VADDPD	-0x8(%RSI,%RDX,8),%YMM17,%YMM17

  (167) 0x424c64 VMULPD	(%RCX,%RDX,8),%YMM17,%YMM21

  (167) 0x424c6b VADDPD	%YMM19,%YMM22,%YMM17

  (167) 0x424c71 VSUBPD	%YMM17,%YMM23,%YMM17

  (167) 0x424c77 VADDPD	%YMM21,%YMM17,%YMM17

  (167) 0x424c7d VDIVPD	%YMM18,%YMM17,%YMM17

  (167) 0x424c83 VCMPPD	$0x5,%YMM16,%YMM17,%K0

  (167) 0x424c8a KORTESTB	%K0,%K0

  (167) 0x424c8e JE	424c9a

  (167) 0x424c90 MOV	0x78(%RBP),%RDI

  (167) 0x424c94 VMOVSD	(%RDI),%XMM20

  (167) 0x424c9a VCMPPD	$0x1,%YMM16,%YMM17,%K1

  (167) 0x424ca1 KORTESTB	%K1,%K1

  (167) 0x424ca5 JE	424ad0

  (167) 0x424cab MOV	0x58(%RBP),%RDI

  (167) 0x424caf VMOVSD	(%RDI),%XMM25

  (167) 0x424cb5 JMP	424ad0

0x424cba NOPW	(%RAX,%RAX,1)

(165) 0x424cc0 VSHUFPD	$0x1,%XMM18,%XMM18,%XMM10

(165) 0x424cc7 VMINSD	%XMM18,%XMM10,%XMM11

(165) 0x424ccd VCMPSD	$0x3,%XMM18,%XMM18,%K1

(165) 0x424cd4 VMOVSD	%XMM10,%XMM11,%XMM11{%K1}

(165) 0x424cda VCMPSD	$0x3,%XMM11,%XMM11,%K1

(165) 0x424ce1 VEXTRACTF32X4	$0x1,%YMM18,%XMM10

(165) 0x424ce8 VMINSD	%XMM11,%XMM10,%XMM11

(165) 0x424ced VMOVSD	%XMM10,%XMM11,%XMM11{%K1}

(165) 0x424cf3 VCMPSD	$0x3,%XMM11,%XMM11,%K1

(165) 0x424cfa VSHUFPD	$0x1,%XMM10,%XMM10,%XMM12

(165) 0x424d00 VMINSD	%XMM11,%XMM12,%XMM10

(165) 0x424d05 VMOVSD	%XMM12,%XMM10,%XMM10{%K1}

(165) 0x424d0b MOV	-0x40(%RBP),%RAX

(165) 0x424d0f MOV	%RAX,%R10

(165) 0x424d12 CMP	-0x78(%RBP),%RAX

(165) 0x424d16 MOV	-0x168(%RBP),%RDI

(165) 0x424d1d MOV	-0x160(%RBP),%RBX

(165) 0x424d24 MOV	-0x158(%RBP),%R12

(165) 0x424d2b MOV	-0x150(%RBP),%R13

(165) 0x424d32 MOV	-0x148(%RBP),%R15

(165) 0x424d39 MOV	-0x140(%RBP),%R8

(165) 0x424d40 MOV	-0x138(%RBP),%R9

(165) 0x424d47 MOV	-0x130(%RBP),%RSI

(165) 0x424d4e JE	4248b0

(165) 0x424d54 JMP	424d9c

0x424d56 NOPW	%CS:(%RAX,%RAX,1)

(165) 0x424d60 MOV	%R9,%RAX

(165) 0x424d63 IMUL	%R11,%RAX

(165) 0x424d67 MOV	%R14,%R12

(165) 0x424d6a LEA	0x1(%R11),%RSI

(165) 0x424d6e MOV	%R9,%RCX

(165) 0x424d71 IMUL	%RSI,%RCX

(165) 0x424d75 MOV	%RCX,-0x88(%RBP)

(165) 0x424d7c MOV	%R15,%RCX

(165) 0x424d7f IMUL	%R11,%RCX

(165) 0x424d83 MOV	%RCX,-0x90(%RBP)

(165) 0x424d8a IMUL	%R15,%RSI

(165) 0x424d8e IMUL	%R8,%R11

(165) 0x424d92 MOV	%R11,-0x80(%RBP)

(165) 0x424d96 MOV	%RAX,%R11

(165) 0x424d99 XOR	%R10D,%R10D

(165) 0x424d9c MOV	-0x70(%RBP),%RDX

(165) 0x424da0 ADD	%RDX,%R11

(165) 0x424da3 MOV	-0x108(%RBP),%RAX

(165) 0x424daa ADD	%R10,%RAX

(165) 0x424dad MOV	%RAX,%RCX

(165) 0x424db0 SUB	-0x110(%RBP),%RCX

(165) 0x424db7 VMOVSD	(%R11,%RCX,8),%XMM11

(165) 0x424dbd MOV	-0x88(%RBP),%R11

(165) 0x424dc4 ADD	%RDX,%R11

(165) 0x424dc7 VMOVSD	(%R11,%RCX,8),%XMM12

(165) 0x424dcd MOV	0x10(%RBP),%RDX

(165) 0x424dd1 ADD	%RDX,%RSI

(165) 0x424dd4 VMOVSD	(%RSI,%RCX,8),%XMM13

(165) 0x424dd9 MOV	-0x90(%RBP),%RSI

(165) 0x424de0 ADD	%RDX,%RSI

(165) 0x424de3 VADDSD	(%RSI,%RCX,8),%XMM13,%XMM13

(165) 0x424de8 MOV	-0x80(%RBP),%RDX

(165) 0x424dec ADD	0x50(%RBP),%RDX

(165) 0x424df0 VMULSD	(%RDX,%RCX,8),%XMM13,%XMM13

(165) 0x424df5 MOV	%R9,%RCX

(165) 0x424df8 IMUL	%RDI,%RCX

(165) 0x424dfc LEA	(%RCX,%RAX,8),%RSI

(165) 0x424e00 IMUL	%RBX,%R9

(165) 0x424e04 LEA	(%R9,%RAX,8),%R14

(165) 0x424e08 IMUL	%RBX,%R8

(165) 0x424e0c LEA	(%R8,%RAX,8),%R9

(165) 0x424e10 MOV	%R15,%RDX

(165) 0x424e13 IMUL	%RDI,%RDX

(165) 0x424e17 LEA	(%RDX,%RAX,8),%R11

(165) 0x424e1b IMUL	%RBX,%R15

(165) 0x424e1f LEA	(%R15,%RAX,8),%R8

(165) 0x424e23 IMUL	%R13,%RDI

(165) 0x424e27 IMUL	%RBX,%R13

(165) 0x424e2b MOV	-0x180(%RBP),%R15

(165) 0x424e32 IMUL	%RBX,%R15

(165) 0x424e36 IMUL	%RBX,%R12

(165) 0x424e3a MOV	-0x38(%RBP),%RAX

(165) 0x424e3e IMUL	%RBX,%RAX

(165) 0x424e42 MOV	%RAX,-0x38(%RBP)

(165) 0x424e46 MOV	-0x48(%RBP),%RCX

(165) 0x424e4a IMUL	%RBX,%RCX

(165) 0x424e4e MOV	-0x78(%RBP),%RDX

(165) 0x424e52 SUB	%R10,%RDX

(165) 0x424e55 MOV	-0xf8(%RBP),%RAX

(165) 0x424e5c ADD	%RAX,%RSI

(165) 0x424e5f MOV	%RSI,-0x48(%RBP)

(165) 0x424e63 ADD	%RAX,%R14

(165) 0x424e66 MOV	%R14,%RSI

(165) 0x424e69 ADD	-0xf0(%RBP),%R9

(165) 0x424e70 MOV	-0x100(%RBP),%RAX

(165) 0x424e77 ADD	%RAX,%R11

(165) 0x424e7a ADD	%RAX,%R8

(165) 0x424e7d ADD	-0xe8(%RBP),%R10

(165) 0x424e84 LEA	(%RDI,%R10,8),%RDI

(165) 0x424e88 MOV	0x48(%RBP),%RAX

(165) 0x424e8c ADD	%RAX,%RDI

(165) 0x424e8f LEA	(,%R10,8),%RBX

(165) 0x424e97 ADD	%R13,%RBX

(165) 0x424e9a ADD	%RAX,%RBX

(165) 0x424e9d LEA	(%R15,%R10,8),%R15

(165) 0x424ea1 ADD	0x30(%RBP),%R15

(165) 0x424ea5 LEA	(%R12,%R10,8),%R12

(165) 0x424ea9 ADD	0x28(%RBP),%R12

(165) 0x424ead MOV	-0x38(%RBP),%RAX

(165) 0x424eb1 LEA	(%RAX,%R10,8),%R13

(165) 0x424eb5 ADD	0x20(%RBP),%R13

(165) 0x424eb9 LEA	(%RCX,%R10,8),%RAX

(165) 0x424ebd ADD	0x18(%RBP),%RAX

(165) 0x424ec1 MOV	0x40(%RBP),%R14

(165) 0x424ec5 LEA	(%R14,%R10,8),%R14

(165) 0x424ec9 VMOVAPD	%XMM10,%XMM14

(165) 0x424ece XOR	%R10D,%R10D

(165) 0x424ed1 JMP	425001

0x424ed6 NOPW	%CS:(%RAX,%RAX,1)

  (166) 0x424ee0 MOV	0x78(%RBP),%RCX

  (166) 0x424ee4 VMOVSD	(%RCX),%XMM10

  (166) 0x424ee8 VMOVSD	(%R14,%R10,8),%XMM20

  (166) 0x424eef VMOVSD	(%RAX,%R10,8),%XMM21

  (166) 0x424ef6 VMOVSD	(%R13,%R10,8),%XMM22

  (166) 0x424efe VADDSD	%XMM22,%XMM22,%XMM22

  (166) 0x424f04 VDIVSD	(%R12,%R10,8),%XMM22,%XMM22

  (166) 0x424f0b VFMADD231SD	%XMM21,%XMM21,%XMM22

  (166) 0x424f11 VSQRTSD	%XMM22,%XMM22,%XMM21

  (166) 0x424f17 VCMPSD	$0x2,%XMM21,%XMM5,%K1

  (166) 0x424f1e VMOVAPD	%XMM5,%XMM22

  (166) 0x424f24 VMOVSD	%XMM21,%XMM22,%XMM22{%K1}

  (166) 0x424f2a VCMPSD	$0x2,%XMM4,%XMM20,%K1

  (166) 0x424f31 VMOVAPD	%XMM4,%XMM21

  (166) 0x424f37 VMOVSD	%XMM20,%XMM21,%XMM21{%K1}

  (166) 0x424f3d VMULSD	%XMM21,%XMM6,%XMM20

  (166) 0x424f43 VDIVSD	%XMM22,%XMM20,%XMM20

  (166) 0x424f49 VMULSD	%XMM7,%XMM18,%XMM21

  (166) 0x424f4f VANDPD	%XMM1,%XMM13,%XMM13

  (166) 0x424f53 VANDPD	%XMM1,%XMM15,%XMM22

  (166) 0x424f59 VMULSD	%XMM5,%XMM19,%XMM19

  (166) 0x424f5f VCMPSD	$0x2,%XMM22,%XMM19,%K1

  (166) 0x424f66 VMOVAPD	%XMM19,%XMM23

  (166) 0x424f6c VMOVSD	%XMM22,%XMM23,%XMM23{%K1}

  (166) 0x424f72 VCMPSD	$0x2,%XMM13,%XMM23,%K1

  (166) 0x424f79 VMOVSD	%XMM13,%XMM23,%XMM23{%K1}

  (166) 0x424f7f VDIVSD	%XMM23,%XMM21,%XMM13

  (166) 0x424f85 VMULSD	%XMM8,%XMM18,%XMM18

  (166) 0x424f8b VANDPD	%XMM1,%XMM16,%XMM16

  (166) 0x424f91 VANDPD	%XMM1,%XMM17,%XMM17

  (166) 0x424f97 VCMPSD	$0x2,%XMM17,%XMM19,%K1

  (166) 0x424f9e VMOVSD	%XMM17,%XMM19,%XMM19{%K1}

  (166) 0x424fa4 VCMPSD	$0x2,%XMM16,%XMM19,%K1

  (166) 0x424fab VMOVSD	%XMM16,%XMM19,%XMM19{%K1}

  (166) 0x424fb1 VDIVSD	%XMM19,%XMM18,%XMM16

  (166) 0x424fb7 VCMPSD	$0x2,%XMM10,%XMM16,%K1

  (166) 0x424fbe VMOVSD	%XMM16,%XMM10,%XMM10{%K1}

  (166) 0x424fc4 VCMPSD	$0x2,%XMM10,%XMM13,%K1

  (166) 0x424fcb VMOVSD	%XMM13,%XMM10,%XMM10{%K1}

  (166) 0x424fd1 VCMPSD	$0x2,%XMM10,%XMM20,%K1

  (166) 0x424fd8 VMOVSD	%XMM20,%XMM10,%XMM10{%K1}

  (166) 0x424fde VCMPSD	$0x2,%XMM10,%XMM14,%K1

  (166) 0x424fe5 VMOVSD	%XMM14,%XMM10,%XMM10{%K1}

  (166) 0x424feb INC	%R10

  (166) 0x424fee VMOVAPD	%XMM10,%XMM14

  (166) 0x424ff3 VMOVAPD	%XMM15,%XMM13

  (166) 0x424ff8 CMP	%R10,%RDX

  (166) 0x424ffb JE	4248b0

  (166) 0x425001 VMOVSD	(%R11,%R10,8),%XMM10

  (166) 0x425007 VADDSD	(%R8,%R10,8),%XMM10,%XMM10

  (166) 0x42500d VMULSD	(%R9,%R10,8),%XMM10,%XMM15

  (166) 0x425013 VMOVSD	(%R15,%R10,8),%XMM19

  (166) 0x42501a VMOVAPD	%XMM11,%XMM10

  (166) 0x42501f VMOVSD	(%RSI,%R10,8),%XMM11

  (166) 0x425025 VADDSD	%XMM10,%XMM11,%XMM10

  (166) 0x42502a VMULSD	(%RBX,%R10,8),%XMM10,%XMM16

  (166) 0x425031 VMOVAPD	%XMM12,%XMM10

  (166) 0x425036 MOV	-0x48(%RBP),%RCX

  (166) 0x42503a VMOVSD	(%RCX,%R10,8),%XMM12

  (166) 0x425040 VADDSD	%XMM10,%XMM12,%XMM10

  (166) 0x425045 VMULSD	(%RDI,%R10,8),%XMM10,%XMM17

  (166) 0x42504c VADDSD	%XMM19,%XMM19,%XMM18

  (166) 0x425052 VADDSD	%XMM16,%XMM13,%XMM10

  (166) 0x425058 VSUBSD	%XMM10,%XMM15,%XMM10

  (166) 0x42505d VADDSD	%XMM17,%XMM10,%XMM10

  (166) 0x425063 VDIVSD	%XMM18,%XMM10,%XMM10

  (166) 0x425069 VUCOMISD	%XMM10,%XMM9

  (166) 0x42506e JBE	424ee0

  (166) 0x425074 MOV	0x58(%RBP),%RCX

  (166) 0x425078 VMOVSD	(%RCX),%XMM20

  (166) 0x42507e VXORPD	%XMM0,%XMM20,%XMM20

  (166) 0x425084 VDIVSD	%XMM10,%XMM20,%XMM10

  (166) 0x42508a JMP	424ee8

0x42508f NOP

Coverage (%)	Name	Source Location	Module
►50.82+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►36.74+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►5.62+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
►4.15+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	calc_dt_kernel	calc_dt_kernel.f90:89	exec
○	calc_dt	calc_dt.f90:49	exec
○	timestep	timestep.f90:85	exec
○	hydro	hydro.f90:54	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.33+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	calc_dt_kernel.f90:89-133
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-133.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.50 to 2.75 cycles (8.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:93
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVG: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94
CMOVGE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
LEA: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes (27 double precision FP elements). The binary function is storing 240 bytes (30 double precision FP elements).

General properties

nb instructions	189
nb uops	196
loop length	874
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	0
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.50 cycles
front end	24.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	16.33	16.33	16.33	16.33	16.33	16.33	18.50	18.50	18.50	18.50	0.75	0.75	0.75	0.75	1.00	1.00
cycles	16.33	16.33	16.33	16.33	16.33	16.33	18.50	18.50	18.50	18.50	0.75	0.75	0.75	0.75	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.50
Dispatch	18.50
Overall L1	24.50

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	11%
load	6%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.50 cycles. At this rate:

3% of peak load performance is reached (8.98 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.50 to 18.50 cycles (1.32x speedup).

ASM code

In the binary file, the address of the function is: 424570

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x90(%RBP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x88(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x5c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
JS 424696 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x126>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R8,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x58(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x5c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x5383d0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404670 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R8D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
JAE 4246b4 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x144>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD 0xd60ff(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM10,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV $0x5383f0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x4c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404230 <__kmpc_for_static_fini@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x68(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x591060,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x98(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x538410,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x424560,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404830 <__kmpc_reduce@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JNE 424696 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x126>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x98(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMINSD (%RAX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $0x591060,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x538430,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4049b0 <__kmpc_end_reduce@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $0x538450,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404740 <__kmpc_barrier@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0xa0(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x20,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $-0x200000000,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R14,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAR $0x20,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x20,%R13	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAR $0x20,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOVSXD (%RSI),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV (%RCX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EBX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RCX,-0x170(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVGE %ECX,%ESI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSI,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $0x7ffffffc,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x1,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVNS %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RSI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVG %RDI,%RSI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x200000000,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %RDX,%RCX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (,%R11,8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x20,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
IMUL %RSI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RCX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,-0x128(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %R10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x118(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVNS %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %RDI,%RDX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %R13,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x50(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SHR $0x20,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
IMUL %RDX,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV $0x8,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NEG %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,-0x120(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x8(%RAX,%R14,1),%R13	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %R13,-0xe0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x8(%RSI,%R14,1),%R13	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %R13,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x8(%R12,%R14,1),%R13	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %R13,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDI,%R14,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R10,%R14,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RBX,%R14,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R15,%R14,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD 0x40(%RBP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R14,-0x190(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RSI,%RDX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %R12,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %R9,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0xd5e9f(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP 0xd2b8f(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP 0xd189f(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VBROADCASTSD 0xd1896(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD 0xd2b75(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R8D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x178(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 4248d1 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x361>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	calc_dt_kernel.f90:89-133
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.50 to 2.75 cycles (8.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:93
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVG: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94
CMOVGE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
LEA: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:94

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

General properties

nb instructions	189
nb uops	196
loop length	874
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	0
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.50 cycles
front end	24.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	16.33	16.33	16.33	16.33	16.33	16.33	18.50	18.50	18.50	18.50	0.75	0.75	0.75	0.75	1.00	1.00
cycles	16.33	16.33	16.33	16.33	16.33	16.33	18.50	18.50	18.50	18.50	0.75	0.75	0.75	0.75	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.50
Dispatch	18.50
Overall L1	24.50

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	11%
load	6%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.50 cycles. At this rate:

3% of peak load performance is reached (8.98 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 424570

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x90(%RBP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x88(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x5c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
JS 424696 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x126>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R8,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x58(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x5c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x5383d0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404670 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R8D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
JAE 4246b4 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x144>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD 0xd60ff(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM10,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV $0x5383f0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x4c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404230 <__kmpc_for_static_fini@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x68(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x591060,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x98(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x538410,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x424560,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404830 <__kmpc_reduce@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JNE 424696 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x126>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x98(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMINSD (%RAX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $0x591060,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x538430,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4049b0 <__kmpc_end_reduce@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $0x538450,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 404740 <__kmpc_barrier@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0xa0(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x20,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $-0x200000000,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R14,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAR $0x20,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x20,%R13	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAR $0x20,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOVSXD (%RSI),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV (%RCX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EBX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RCX,-0x170(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVGE %ECX,%ESI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSI,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $0x7ffffffc,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x1,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVNS %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RSI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVG %RDI,%RSI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x200000000,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %RDX,%RCX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (,%R11,8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x20,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
IMUL %RSI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RCX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,-0x128(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %R10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x118(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVNS %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %RDI,%RDX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %R13,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x50(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVG %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SHR $0x20,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
IMUL %RDX,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV $0x8,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NEG %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,-0x120(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x8(%RAX,%R14,1),%R13	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %R13,-0xe0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x8(%RSI,%R14,1),%R13	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %R13,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x8(%R12,%R14,1),%R13	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %R13,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDI,%R14,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R10,%R14,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RBX,%R14,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R15,%R14,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD 0x40(%RBP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R14,-0x190(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RSI,%RDX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %R12,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %R9,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0xd5e9f(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP 0xd2b8f(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP 0xd189f(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VBROADCASTSD 0xd1896(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD 0xd2b75(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R8D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x178(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 4248d1 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x361>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2–	3.32	1.32
▼Loop 165 - calc_dt_kernel.f90:92-129 - exec–	0.01	0.01
○Loop 167 - calc_dt_kernel.f90:92-129 - exec	3.31	1.31
○Loop 166 - calc_dt_kernel.f90:94-129 - exec	0.00	0.00

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Code clean check

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code