OV - exec - Function pack_kernel_module_mp_clover_pack_message_left

	Function: pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split104	Module: exec	Source: pack_kernel.f90:61-69	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 61 - 69

--------------------------------------------------------------------------------

61:     !$OMP PARALLEL DO PRIVATE(index)

62:     DO k=y_min-depth,y_max+y_inc+depth

63:     !$OMP SIMD

64:       DO j=1,depth

65:         index= buffer_offset + j+(k+depth-1)*depth

66:         left_snd_buffer(index)=field(x_min+x_inc-1+j,k)

67:       ENDDO

68:     ENDDO

69:   !$OMP END PARALLEL DO

0x42e940 PUSH	%RBP

0x42e941 MOV	%RSP,%RBP

0x42e944 PUSH	%R15

0x42e946 PUSH	%R14

0x42e948 PUSH	%R13

0x42e94a PUSH	%R12

0x42e94c PUSH	%RBX

0x42e94d SUB	$0x88,%RSP

0x42e954 MOV	%R9,-0x58(%RBP)

0x42e958 MOV	%R8,-0x80(%RBP)

0x42e95c MOV	0x20(%RBP),%RAX

0x42e960 MOV	%RAX,-0x78(%RBP)

0x42e964 MOV	0x18(%RBP),%RAX

0x42e968 MOV	%RAX,-0x70(%RBP)

0x42e96c MOV	0x10(%RBP),%RAX

0x42e970 MOV	%RAX,-0x68(%RBP)

0x42e974 MOV	0x30(%RBP),%EAX

0x42e977 MOVL	$0,-0x4c(%RBP)

0x42e97e TEST	%EAX,%EAX

0x42e980 JS	42e9f7

0x42e982 MOV	%RCX,%RBX

0x42e985 MOV	%RDX,%R14

0x42e988 MOV	(%RDI),%ESI

0x42e98a MOVL	$0,-0x34(%RBP)

0x42e991 MOV	%EAX,-0x30(%RBP)

0x42e994 MOVL	$0x1,-0x48(%RBP)

0x42e99b SUB	$0x8,%RSP

0x42e99f LEA	-0x48(%RBP),%RAX

0x42e9a3 LEA	-0x4c(%RBP),%RCX

0x42e9a7 LEA	-0x34(%RBP),%R8

0x42e9ab LEA	-0x30(%RBP),%R9

0x42e9af MOV	$0x5397f0,%EDI

0x42e9b4 MOV	%ESI,-0x44(%RBP)

0x42e9b7 MOV	$0x22,%EDX

0x42e9bc PUSH	$0x1

0x42e9be PUSH	$0x1

0x42e9c0 PUSH	%RAX

0x42e9c1 CALL	404670 <__kmpc_for_static_init_4@plt>

0x42e9c6 ADD	$0x20,%RSP

0x42e9ca MOV	-0x34(%RBP),%ECX

0x42e9cd MOV	-0x30(%RBP),%R13D

0x42e9d1 SUB	%ECX,%R13D

0x42e9d4 JAE	42ea09

0x42e9d6 MOV	$0x539810,%EDI

0x42e9db MOV	-0x44(%RBP),%ESI

0x42e9de ADD	$0x88,%RSP

0x42e9e5 POP	%RBX

0x42e9e6 POP	%R12

0x42e9e8 POP	%R13

0x42e9ea POP	%R14

0x42e9ec POP	%R15

0x42e9ee POP	%RBP

0x42e9ef VZEROUPPER

0x42e9f2 JMP	404230

0x42e9f7 ADD	$0x88,%RSP

0x42e9fe POP	%RBX

0x42e9ff POP	%R12

0x42ea01 POP	%R13

0x42ea03 POP	%R14

0x42ea05 POP	%R15

0x42ea07 POP	%RBP

0x42ea08 RET

0x42ea09 MOV	-0x58(%RBP),%RAX

0x42ea0d MOV	(%RAX),%R15D

0x42ea10 LEA	(%RCX,%R14,1),%EDX

0x42ea14 MOV	%RDX,-0x60(%RBP)

0x42ea18 LEA	(%RCX,%R14,1),%EDX

0x42ea1c DEC	%EDX

0x42ea1e XOR	%EDI,%EDI

0x42ea20 VMOVDQA	0xc8a28(%RIP),%XMM0

0x42ea28 VPCMPEQD	%YMM1,%YMM1,%YMM1

0x42ea2c VMOVDQA	0xc854c(%RIP),%YMM2

0x42ea34 MOV	%RBX,-0x40(%RBP)

0x42ea38 MOV	%R13D,-0x2c(%RBP)

0x42ea3c JMP	42ea4f

0x42ea3e XCHG	%AX,%AX

(294) 0x42ea40 MOV	%R14D,%R15D

(294) 0x42ea43 LEA	0x1(%RDI),%ECX

(294) 0x42ea46 INC	%EDX

(294) 0x42ea48 CMP	%R13D,%EDI

(294) 0x42ea4b MOV	%ECX,%EDI

(294) 0x42ea4d JE	42e9d6

(294) 0x42ea4f TEST	%R15D,%R15D

(294) 0x42ea52 JLE	42ea43

(294) 0x42ea54 MOV	-0x60(%RBP),%RCX

(294) 0x42ea58 ADD	%EDI,%ECX

(294) 0x42ea5a MOV	-0x80(%RBP),%RSI

(294) 0x42ea5e MOVSXD	(%RSI),%RBX

(294) 0x42ea61 MOV	-0x58(%RBP),%RSI

(294) 0x42ea65 MOV	(%RSI),%R14D

(294) 0x42ea68 MOV	-0x70(%RBP),%R8

(294) 0x42ea6c MOV	(%R8),%R9

(294) 0x42ea6f MOV	0x38(%R8),%R10

(294) 0x42ea73 MOV	-0x78(%RBP),%RSI

(294) 0x42ea77 MOV	(%RSI),%EAX

(294) 0x42ea79 MOV	0x50(%R8),%R8

(294) 0x42ea7d MOV	-0x68(%RBP),%RSI

(294) 0x42ea81 MOV	(%RSI),%R11

(294) 0x42ea84 MOV	0x38(%RSI),%RSI

(294) 0x42ea88 MOV	%R15D,%R12D

(294) 0x42ea8b MOV	%R12,%R15

(294) 0x42ea8e MOVSXD	%ECX,%R13

(294) 0x42ea91 MOV	$-0x4,%ECX

(294) 0x42ea96 AND	%RCX,%R15

(294) 0x42ea99 MOV	%RBX,-0xa8(%RBP)

(294) 0x42eaa0 MOV	%RAX,-0xa0(%RBP)

(294) 0x42eaa7 MOV	%R13,-0x98(%RBP)

(294) 0x42eaae JE	42eb80

(294) 0x42eab4 MOV	%R8,%RCX

(294) 0x42eab7 INC	%R13

(294) 0x42eaba MOV	%R8,-0x88(%RBP)

(294) 0x42eac1 IMUL	%R8,%R13

(294) 0x42eac5 VPBROADCASTQ	%R10,%YMM3

(294) 0x42eacb VPBROADCASTQ	%RSI,%YMM4

(294) 0x42ead1 LEA	(%R14,%RDX,1),%ECX

(294) 0x42ead5 MOV	%R14,-0x90(%RBP)

(294) 0x42eadc IMUL	%R14D,%ECX

(294) 0x42eae0 MOVSXD	%ECX,%R8

(294) 0x42eae3 ADD	%RBX,%R8

(294) 0x42eae6 MOV	-0x40(%RBP),%RBX

(294) 0x42eaea ADD	%EAX,%EBX

(294) 0x42eaec ADD	%R9,%R13

(294) 0x42eaef XOR	%ECX,%ECX

(294) 0x42eaf1 NOPW	%CS:(%RAX,%RAX,1)

  (296) 0x42eb00 LEA	(%RBX,%RCX,1),%R14D

  (296) 0x42eb04 VPBROADCASTD	%R14D,%XMM5

  (296) 0x42eb0a VPADDD	%XMM0,%XMM5,%XMM5

  (296) 0x42eb0e VPMOVSXDQ	%XMM5,%YMM5

  (296) 0x42eb13 VPSUBQ	%YMM1,%YMM5,%YMM5

  (296) 0x42eb17 VPMULLQ	%YMM5,%YMM3,%YMM5

  (296) 0x42eb1d KXNORW	%K0,%K0,%K1

  (296) 0x42eb21 VXORPD	%XMM6,%XMM6,%XMM6

  (296) 0x42eb25 VGATHERQPD	(%R13,%YMM5,1),%YMM6{%K1}

  (296) 0x42eb2d LEA	(%R8,%RCX,1),%R14

  (296) 0x42eb31 VPBROADCASTQ	%R14,%YMM5

  (296) 0x42eb37 VPADDQ	%YMM2,%YMM5,%YMM5

  (296) 0x42eb3b VPMULLQ	%YMM5,%YMM4,%YMM5

  (296) 0x42eb41 KXNORW	%K0,%K0,%K1

  (296) 0x42eb45 VSCATTERQPD	%YMM6,(%R11,%YMM5,1){%K1}

  (296) 0x42eb4c ADD	$0x4,%RCX

  (296) 0x42eb50 CMP	%R15,%RCX

  (296) 0x42eb53 JB	42eb00

(294) 0x42eb55 CMP	%R12,%R15

(294) 0x42eb58 MOV	-0x40(%RBP),%RBX

(294) 0x42eb5c MOV	-0x2c(%RBP),%R13D

(294) 0x42eb60 MOV	-0x90(%RBP),%R14

(294) 0x42eb67 MOV	-0x88(%RBP),%R8

(294) 0x42eb6e JE	42ea40

(294) 0x42eb74 JMP	42eb8b

0x42eb76 NOPW	%CS:(%RAX,%RAX,1)

(294) 0x42eb80 XOR	%R15D,%R15D

(294) 0x42eb83 MOV	-0x40(%RBP),%RBX

(294) 0x42eb87 MOV	-0x2c(%RBP),%R13D

(294) 0x42eb8b MOV	-0x98(%RBP),%RAX

(294) 0x42eb92 INC	%RAX

(294) 0x42eb95 IMUL	%RAX,%R8

(294) 0x42eb99 ADD	%R8,%R9

(294) 0x42eb9c SUB	%R15,%R12

(294) 0x42eb9f MOV	-0xa0(%RBP),%RAX

(294) 0x42eba6 ADD	%EBX,%EAX

(294) 0x42eba8 ADD	%R15D,%EAX

(294) 0x42ebab MOV	-0xa8(%RBP),%R8

(294) 0x42ebb2 ADD	%R15,%R8

(294) 0x42ebb5 LEA	(%R14,%RDX,1),%ECX

(294) 0x42ebb9 IMUL	%R14D,%ECX

(294) 0x42ebbd MOVSXD	%ECX,%RCX

(294) 0x42ebc0 ADD	%R8,%RCX

(294) 0x42ebc3 IMUL	%RSI,%RCX

(294) 0x42ebc7 ADD	%RCX,%R11

(294) 0x42ebca NOPW	(%RAX,%RAX,1)

  (295) 0x42ebd0 CLTQ

  (295) 0x42ebd2 LEA	0x1(%RAX),%RCX

  (295) 0x42ebd6 IMUL	%R10,%RCX

  (295) 0x42ebda VMOVQ	(%R9,%RCX,1),%XMM3

  (295) 0x42ebe0 VMOVQ	%XMM3,(%R11)

  (295) 0x42ebe5 INC	%EAX

  (295) 0x42ebe7 ADD	%RSI,%R11

  (295) 0x42ebea DEC	%R12

  (295) 0x42ebed JNE	42ebd0

(294) 0x42ebef JMP	42ea40

0x42ebf4 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►49.16+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►36.72+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►7.91+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
►1.69+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
►1.13+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	clover_pack_message_left	pack_kernel.f90:61	exec
○	clover_pack_left	clover.f90:660	exec
○	clover_exchange	clover.f90:381	exec
○	update_halo	update_halo.f90:44	exec
○	advection	advection.f90:56	exec
○	hydro	hydro.f90:64	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.13+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	clover_pack_message_left	pack_kernel.f90:61	exec
○	clover_pack_left	clover.f90:600	exec
○	clover_exchange	clover.f90:381	exec
○	update_halo	update_halo.f90:44	exec
○	timestep	timestep.f90:74	exec
○	hydro	hydro.f90:54	exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	pack_kernel.f90:61-69
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:61-69.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.25 cycles (7.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:63

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 104 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	78
nb uops	76
loop length	278
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	2
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	6.50	6.50	6.50	6.50	0.25	0.25	0.25	0.25	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	6.50	6.50	6.50	6.50	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Dispatch	6.50
Overall L1	9.50

Vectorization ratios

all	13%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	13%
load	16%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

4% of peak load performance is reached (10.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.42 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.50 to 6.50 cycles (1.46x speedup).

ASM code

In the binary file, the address of the function is: 42e940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVL $0,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JS 42e9f7 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split104+0xb7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x48(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x4c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x5397f0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404670 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x34(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x30(%RBP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 42ea09 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split104+0xc9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x539810,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 404230 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
LEA (%RCX,%R14,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%R14,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
DEC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVDQA 0xc8a28(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VPCMPEQD %YMM1,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VMOVDQA 0xc854c(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
MOV %RBX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
JMP 42ea4f <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split104+0x10f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	pack_kernel.f90:61-69
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:61-69.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.25 cycles (7.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -qopt-zmm-usage=high

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:63

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 104 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	78
nb uops	76
loop length	278
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	2
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	6.50	6.50	6.50	6.50	0.25	0.25	0.25	0.25	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	6.50	6.50	6.50	6.50	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Dispatch	6.50
Overall L1	9.50

Vectorization ratios

all	13%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	13%
load	16%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

4% of peak load performance is reached (10.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.42 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42e940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVL $0,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JS 42e9f7 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split104+0xb7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x48(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x4c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x5397f0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404670 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x34(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x30(%RBP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 42ea09 <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split104+0xc9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x539810,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 404230 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
LEA (%RCX,%R14,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%R14,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
DEC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVDQA 0xc8a28(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VPCMPEQD %YMM1,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VMOVDQA 0xc854c(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
MOV %RBX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
JMP 42ea4f <pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split104+0x10f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼pack_kernel_module_mp_clover_pack_message_left_.DIR.OMP.PARALLEL.LOOP.2.split104–	0.01	0.00
▼Loop 294 - pack_kernel.f90:62-66 - exec–	0.00	0.01
○Loop 295 - pack_kernel.f90:64-66 - exec	0.01	0.01
○Loop 296 - pack_kernel.f90:64-66 - exec	0.00	0.00

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Code clean check

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code