OV - exec - Loop 212

	Loop Id: 212	Module: exec	Source: calc_dt_kernel.f90:107-131	Coverage: 3.43%

0x231ee0 MOV	0x130(%R14),%RAX    [12]

0x231ee7 VMOVSD	(%RAX),%XMM11    [5]

0x231eeb VMOVSD	0x8(%RCX,%RDI,8),%XMM19    [3]

0x231ef3 VMOVSD	0x8(%R8,%RDI,8),%XMM18    [1]

0x231efb VMOVSD	0x8(%R10,%RDI,8),%XMM17    [4]

0x231f03 VCMPSD	$0x3,%XMM5,%XMM5,%K1

0x231f0a VANDPD	%XMM2,%XMM16,%XMM16

0x231f10 VANDPD	%XMM2,%XMM15,%XMM15

0x231f14 VANDPD	%XMM2,%XMM14,%XMM14

0x231f18 VANDPD	%XMM2,%XMM13,%XMM13

0x231f1c VCMPSD	$0x3,%XMM14,%XMM14,%K2

0x231f23 VADDSD	%XMM19,%XMM19,%XMM19

0x231f29 VDIVSD	0x8(%R15,%RDI,8),%XMM19,%XMM19    [13]

0x231f31 VMULSD	%XMM18,%XMM18,%XMM18

0x231f37 INC	%RDI

0x231f3a VADDSD	%XMM19,%XMM18,%XMM18

0x231f40 VSQRTSD	%XMM18,%XMM18,%XMM18

0x231f46 VMAXSD	%XMM5,%XMM18,%XMM19

0x231f4c VMOVSD	%XMM18,%XMM19,%XMM19{%K1}

0x231f52 VCMPSD	$0x3,%XMM4,%XMM4,%K1

0x231f59 VMINSD	%XMM4,%XMM17,%XMM18

0x231f5f VMOVSD	%XMM17,%XMM18,%XMM18{%K1}

0x231f65 VCMPSD	$0x3,%XMM16,%XMM16,%K1

0x231f6c VMULSD	%XMM6,%XMM18,%XMM17

0x231f72 VMULSD	%XMM7,%XMM12,%XMM18

0x231f78 VMULSD	%XMM8,%XMM12,%XMM12

0x231f7d VDIVSD	%XMM19,%XMM17,%XMM17

0x231f83 VMAXSD	%XMM16,%XMM15,%XMM19

0x231f89 VMAXSD	%XMM14,%XMM13,%XMM16

0x231f8f VMOVSD	%XMM15,%XMM19,%XMM19{%K1}

0x231f95 KMOVD	%EDX,%K1

0x231f99 VMOVSD	%XMM13,%XMM16,%XMM16{%K2}

0x231f9f VMAXSD	%XMM10,%XMM19,%XMM15

0x231fa5 VMAXSD	%XMM10,%XMM16,%XMM10

0x231fab VMOVSD	%XMM19,%XMM15,%XMM15{%K1}

0x231fb1 VMOVSD	%XMM16,%XMM10,%XMM10{%K1}

0x231fb7 VDIVSD	%XMM15,%XMM18,%XMM15

0x231fbd VDIVSD	%XMM10,%XMM12,%XMM10

0x231fc2 VCMPSD	$0x3,%XMM17,%XMM17,%K1

0x231fc9 VMINSD	%XMM17,%XMM20,%XMM12

0x231fcf VMOVSD	%XMM20,%XMM12,%XMM12{%K1}

0x231fd5 VCMPSD	$0x3,%XMM15,%XMM15,%K1

0x231fdc VMINSD	%XMM15,%XMM12,%XMM13

0x231fe1 VMOVSD	%XMM12,%XMM13,%XMM13{%K1}

0x231fe7 VCMPSD	$0x3,%XMM10,%XMM10,%K1

0x231fee VMINSD	%XMM10,%XMM13,%XMM12

0x231ff3 VMOVSD	%XMM13,%XMM12,%XMM12{%K1}

0x231ff9 VCMPSD	$0x3,%XMM11,%XMM11,%K1

0x232000 VMINSD	%XMM11,%XMM12,%XMM20

0x232006 VMOVSD	%XMM12,%XMM20,%XMM20{%K1}

0x23200c CMP	%RDI,0x20(%RSP)    [14]

0x232011 JE	231d70

0x232017 MOV	0x60(%RSP),%RAX    [14]

0x23201c VMOVUPD	0x8(%R12,%RDI,8),%XMM10    [10]

0x232023 VMOVSD	0x10(%R13,%RDI,8),%XMM14    [11]

0x23202a VMOVSD	0x10(%RBX,%RDI,8),%XMM13    [16]

0x232030 VMOVSD	0x8(%R11,%RDI,8),%XMM12    [7]

0x232037 VADDSD	0x8(%R13,%RDI,8),%XMM14,%XMM14    [11]

0x23203e VADDSD	0x8(%RBX,%RDI,8),%XMM13,%XMM13    [16]

0x232044 VMULSD	0x8(%RSI,%RDI,8),%XMM14,%XMM14    [8]

0x23204a VMULSD	0x8(%R9,%RDI,8),%XMM13,%XMM13    [2]

0x232051 VADDPD	0x8(%RAX,%RDI,8),%XMM10,%XMM10    [15]

0x232057 VMULPD	0x8(%RBP,%RDI,8),%XMM10,%XMM15    [9]

0x23205d VADDSD	%XMM12,%XMM12,%XMM17

0x232063 VSHUFPD	$0x1,%XMM15,%XMM15,%XMM16

0x23206a VADDSD	%XMM1,%XMM16,%XMM10

0x232070 VSUBSD	%XMM15,%XMM10,%XMM11

0x232075 VMULSD	%XMM5,%XMM12,%XMM10

0x232079 VADDSD	%XMM14,%XMM11,%XMM11

0x23207e VUCOMISD	%XMM10,%XMM10

0x232083 VSUBSD	%XMM13,%XMM11,%XMM11

0x232088 SETP	%DL

0x23208b VDIVSD	%XMM17,%XMM11,%XMM11

0x232091 VUCOMISD	%XMM11,%XMM9

0x232096 JBE	231ee0

0x23209c VDIVSD	%XMM11,%XMM3,%XMM11

0x2320a1 MOV	0x128(%R14),%RAX    [12]

0x2320a8 VMULSD	(%RAX),%XMM11,%XMM11    [6]

0x2320ac JMP	231eeb

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 107 - 131

--------------------------------------------------------------------------------

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

130:

131:       ENDDO

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.84
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks
Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source	calc_dt_kernel.f90:107-131
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	30.50
CQA cycles if no scalar integer	30.50
CQA cycles if FP arith vectorized	7.94
CQA cycles if fully vectorized	3.81
Front-end cycles	9.88
P0 cycles	0.92
P1 cycles	0.92
P2 cycles	0.92
P3 cycles	0.92
P4 cycles	0.92
P5 cycles	0.92
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	15.25
P11 cycles	15.25
P12 cycles	15.25
P13 cycles	15.25
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	30.50
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	79.00
Nb loads	18.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.89
Nb FLOP add-sub	11.00
Nb FLOP mul	9.50
Nb FLOP fma	0.00
Nb FLOP div	5.50
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.53
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	11.85
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	11.81
Vectorization ratio add_sub	10.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	14.29
Vector-efficiency ratio all	13.98
Vector-efficiency ratio load	15.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	13.98
Vector-efficiency ratio add_sub	13.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	14.29

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	4.09
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.10
Bottlenecks	P10, P11,
Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source	calc_dt_kernel.f90:107-131
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	7.94
CQA cycles if fully vectorized	4.06
Front-end cycles	10.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	15.50
P11 cycles	15.50
P12 cycles	15.50
P13 cycles	15.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	32.50
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	80.00
Nb loads	18.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.86
Nb FLOP add-sub	11.00
Nb FLOP mul	10.00
Nb FLOP fma	0.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.17
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	11.76
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	11.11
Vectorization ratio add_sub	10.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	14.29
Vector-efficiency ratio all	13.97
Vector-efficiency ratio load	15.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	13.89
Vector-efficiency ratio add_sub	13.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	14.29

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.59
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.90
Bottlenecks	P10, P11,
Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source	calc_dt_kernel.f90:107-131
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	7.94
CQA cycles if fully vectorized	3.56
Front-end cycles	9.75
P0 cycles	0.83
P1 cycles	0.83
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	15.00
P11 cycles	15.00
P12 cycles	15.00
P13 cycles	15.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	28.50
Inter-iter dependencies cycles	12
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	78.00
Nb loads	18.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.91
Nb FLOP add-sub	11.00
Nb FLOP mul	9.00
Nb FLOP fma	0.00
Nb FLOP div	5.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.89
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	7.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	11.94
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	12.50
Vectorization ratio add_sub	10.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	14.29
Vector-efficiency ratio all	13.99
Vector-efficiency ratio load	15.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	14.06
Vector-efficiency ratio add_sub	13.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	14.29

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source file and lines	calc_dt_kernel.f90:107-131
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:107-131.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 30.50 to 3.81 cycles (8.00x speedup).

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.
10% of SSE/AVX addition or subtraction instructions are used in vector version.
11% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
14% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 30.50 to 15.25 cycles (2.00x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVD: 0 occurrences
VUCOMISD: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

43 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 27 FP arithmetical operations:

11: addition or subtraction
9.50: multiply
5.50: divide
1: square root

The binary loop is loading 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	79
loop length	449
used x86 registers	16
used mmx registers	0
used xmm registers	19.50
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.18

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	9.88 cycles
front end	9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.92	0.92	0.92	0.92	0.92	0.92	4.50	4.50	4.50	4.50	15.25	15.25	15.25	15.25	1.00	1.00
cycles	0.92	0.92	0.92	0.92	0.92	0.92	4.50	4.50	4.50	4.50	15.25	15.25	15.25	15.25	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	30.50
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	9.88
Dispatch	15.25
DIV/SQRT	30.50
Data deps.	12.00
Overall L1	30.50

Vectorization ratios

all	11%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	13%
load	15%
store	NA (no store vectorizable/vectorized instructions)
mul	13%
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.50 cycles. At this rate:

2% of peak load performance is reached (5.53 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source file and lines	calc_dt_kernel.f90:107-131
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.
10% of SSE/AVX addition or subtraction instructions are used in vector version.
11% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
14% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 32.50 to 15.50 cycles (2.10x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.50 to 15.50 cycles (2.10x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:126
VUCOMISD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:112
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:123

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

44 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

11: addition or subtraction
10: multiply
6: divide
1: square root

The binary loop is loading 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	77
nb uops	80
loop length	454
used x86 registers	16
used mmx registers	0
used xmm registers	20
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.00 cycles
front end	10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	4.50	4.50	4.50	4.50	15.50	15.50	15.50	15.50	1.00	1.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	4.50	4.50	4.50	4.50	15.50	15.50	15.50	15.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	32.50
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	10.00
Dispatch	15.50
DIV/SQRT	32.50
Data deps.	12.00
Overall L1	32.50

Vectorization ratios

all	11%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	13%
load	15%
store	NA (no store vectorizable/vectorized instructions)
mul	13%
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.50 cycles. At this rate:

2% of peak load performance is reached (5.17 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 232017

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD 0x8(%RCX,%RDI,8),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R8,%RDI,8),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R10,%RDI,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VCMPSD $0x3,%XMM5,%XMM5,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM2,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM2,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM2,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM2,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCMPSD $0x3,%XMM14,%XMM14,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM19,%XMM19,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD 0x8(%R15,%RDI,8),%XMM19,%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD %XMM19,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSQRTSD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
VMAXSD %XMM5,%XMM18,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM18,%XMM19,%XMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x3,%XMM4,%XMM4,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM4,%XMM17,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM17,%XMM18,%XMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x3,%XMM16,%XMM16,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM6,%XMM18,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM7,%XMM12,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM8,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM19,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMAXSD %XMM16,%XMM15,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM14,%XMM13,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM15,%XMM19,%XMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
KMOVD %EDX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
VMOVSD %XMM13,%XMM16,%XMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMAXSD %XMM10,%XMM19,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM10,%XMM16,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM19,%XMM15,%XMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVSD %XMM16,%XMM10,%XMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VDIVSD %XMM15,%XMM18,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM10,%XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VCMPSD $0x3,%XMM17,%XMM17,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM17,%XMM20,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM20,%XMM12,%XMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x3,%XMM15,%XMM15,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM15,%XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM12,%XMM13,%XMM13{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x3,%XMM10,%XMM10,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM10,%XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM13,%XMM12,%XMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x3,%XMM11,%XMM11,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM11,%XMM12,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM12,%XMM20,%XMM20{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
CMP %RDI,0x20(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 231d70 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x150>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD 0x8(%R12,%RDI,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD 0x10(%R13,%RDI,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RBX,%RDI,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R11,%RDI,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x8(%R13,%RDI,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD 0x8(%RBX,%RDI,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD 0x8(%RSI,%RDI,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD 0x8(%R9,%RDI,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDPD 0x8(%RAX,%RDI,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD 0x8(%RBP,%RDI,8),%XMM10,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VADDSD %XMM12,%XMM12,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM15,%XMM15,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM16,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM15,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM5,%XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM14,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VUCOMISD %XMM10,%XMM10	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VSUBSD %XMM13,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
SETP %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VDIVSD %XMM17,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VUCOMISD %XMM11,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 231ee0 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x2c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VDIVSD %XMM11,%XMM3,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOV 0x128(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULSD (%RAX),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 231eeb <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x2cb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1
Source file and lines	calc_dt_kernel.f90:107-131
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.
10% of SSE/AVX addition or subtraction instructions are used in vector version.
12% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
14% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.50 to 15.00 cycles (1.90x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:126
VUCOMISD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:112
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:123

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

42 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 26 FP arithmetical operations:

11: addition or subtraction
9: multiply
5: divide
1: square root

The binary loop is loading 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	75
nb uops	78
loop length	444
used x86 registers	16
used mmx registers	0
used xmm registers	19
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.83	0.83	0.83	0.83	0.83	0.83	4.50	4.50	4.50	4.50	15.00	15.00	15.00	15.00	1.00	1.00
cycles	0.83	0.83	0.83	0.83	0.83	0.83	4.50	4.50	4.50	4.50	15.00	15.00	15.00	15.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	28.50
Longest recurrence chain latency (RecMII)	12.00

Cycles summary

Front-end	9.75
Dispatch	15.00
DIV/SQRT	28.50
Data deps.	12.00
Overall L1	28.50

Vectorization ratios

all	11%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	13%
load	15%
store	NA (no store vectorizable/vectorized instructions)
mul	14%
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

2% of peak load performance is reached (5.89 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 232017

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x130(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RCX,%RDI,8),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R8,%RDI,8),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R10,%RDI,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VCMPSD $0x3,%XMM5,%XMM5,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM2,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM2,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM2,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM2,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCMPSD $0x3,%XMM14,%XMM14,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM19,%XMM19,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD 0x8(%R15,%RDI,8),%XMM19,%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMULSD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD %XMM19,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSQRTSD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
VMAXSD %XMM5,%XMM18,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM18,%XMM19,%XMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x3,%XMM4,%XMM4,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM4,%XMM17,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM17,%XMM18,%XMM18{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x3,%XMM16,%XMM16,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM6,%XMM18,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM7,%XMM12,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM8,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM19,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VMAXSD %XMM16,%XMM15,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM14,%XMM13,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM15,%XMM19,%XMM19{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
KMOVD %EDX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
VMOVSD %XMM13,%XMM16,%XMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMAXSD %XMM10,%XMM19,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM10,%XMM16,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM19,%XMM15,%XMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVSD %XMM16,%XMM10,%XMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VDIVSD %XMM15,%XMM18,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM10,%XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VCMPSD $0x3,%XMM17,%XMM17,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM17,%XMM20,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM20,%XMM12,%XMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x3,%XMM15,%XMM15,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM15,%XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM12,%XMM13,%XMM13{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x3,%XMM10,%XMM10,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM10,%XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM13,%XMM12,%XMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x3,%XMM11,%XMM11,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM11,%XMM12,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM12,%XMM20,%XMM20{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
CMP %RDI,0x20(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 231d70 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x150>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD 0x8(%R12,%RDI,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD 0x10(%R13,%RDI,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RBX,%RDI,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R11,%RDI,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x8(%R13,%RDI,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD 0x8(%RBX,%RDI,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD 0x8(%RSI,%RDI,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD 0x8(%R9,%RDI,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDPD 0x8(%RAX,%RDI,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD 0x8(%RBP,%RDI,8),%XMM10,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VADDSD %XMM12,%XMM12,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM15,%XMM15,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM16,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM15,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM5,%XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM14,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VUCOMISD %XMM10,%XMM10	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VSUBSD %XMM13,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
SETP %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VDIVSD %XMM17,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VUCOMISD %XMM11,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 231ee0 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x2c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks