OV - exec - Loop 21

	Loop Id: 21	Module: exec	Source: build_field.f90:104-116	Coverage: 0.09%

0x21bd80 MOV	0x630(%R14),%R9    [13]

0x21bd87 MOV	0x5e8(%R14),%R8    [13]

0x21bd8e ADD	%RDX,%R9

0x21bd91 IMUL	$0x1780,%R9,%R9

0x21bd98 MOV	-0xb90(%R8,%R9,1),%R10    [3]

0x21bda0 IMUL	%RAX,%R10

0x21bda4 ADD	-0xbf8(%R8,%R9,1),%R10    [3]

0x21bdac MOV	-0xc40(%R8,%R9,1),%R8    [3]

0x21bdb4 ADD	%RDI,%R10

0x21bdb7 MOVQ	$0,-0x8(%R8,%R10,8)    [2]

0x21bdc0 MOV	0x630(%R14),%R9    [13]

0x21bdc7 MOV	0x5e8(%R14),%R8    [13]

0x21bdce ADD	%RDX,%R9

0x21bdd1 IMUL	$0x1780,%R9,%R9

0x21bdd8 MOV	-0xad0(%R8,%R9,1),%R10    [1]

0x21bde0 IMUL	%RAX,%R10

0x21bde4 ADD	-0xb38(%R8,%R9,1),%R10    [1]

0x21bdec MOV	-0xb80(%R8,%R9,1),%R8    [1]

0x21bdf4 ADD	%RDI,%R10

0x21bdf7 MOVQ	$0,-0x8(%R8,%R10,8)    [23]

0x21be00 MOV	0x630(%R14),%R9    [13]

0x21be07 MOV	0x5e8(%R14),%R8    [13]

0x21be0e ADD	%RDX,%R9

0x21be11 IMUL	$0x1780,%R9,%R9

0x21be18 MOV	-0xa10(%R8,%R9,1),%R10    [22]

0x21be20 IMUL	%RAX,%R10

0x21be24 ADD	-0xa78(%R8,%R9,1),%R10    [22]

0x21be2c MOV	-0xac0(%R8,%R9,1),%R8    [22]

0x21be34 ADD	%RDI,%R10

0x21be37 MOVQ	$0,-0x8(%R8,%R10,8)    [21]

0x21be40 MOV	0x630(%R14),%R9    [13]

0x21be47 MOV	0x5e8(%R14),%R8    [13]

0x21be4e ADD	%RDX,%R9

0x21be51 IMUL	$0x1780,%R9,%R9

0x21be58 MOV	-0x950(%R8,%R9,1),%R10    [20]

0x21be60 IMUL	%RAX,%R10

0x21be64 ADD	-0x9b8(%R8,%R9,1),%R10    [20]

0x21be6c MOV	-0xa00(%R8,%R9,1),%R8    [20]

0x21be74 ADD	%RDI,%R10

0x21be77 MOVQ	$0,-0x8(%R8,%R10,8)    [19]

0x21be80 MOV	0x630(%R14),%R9    [13]

0x21be87 MOV	0x5e8(%R14),%R8    [13]

0x21be8e ADD	%RDX,%R9

0x21be91 IMUL	$0x1780,%R9,%R9

0x21be98 MOV	-0x890(%R8,%R9,1),%R10    [18]

0x21bea0 IMUL	%RAX,%R10

0x21bea4 ADD	-0x8f8(%R8,%R9,1),%R10    [18]

0x21beac MOV	-0x940(%R8,%R9,1),%R8    [18]

0x21beb4 ADD	%RDI,%R10

0x21beb7 MOVQ	$0,-0x8(%R8,%R10,8)    [17]

0x21bec0 MOV	0x630(%R14),%R9    [13]

0x21bec7 MOV	0x5e8(%R14),%R8    [13]

0x21bece ADD	%RDX,%R9

0x21bed1 IMUL	$0x1780,%R9,%R9

0x21bed8 MOV	-0x7d0(%R8,%R9,1),%R10    [16]

0x21bee0 IMUL	%RAX,%R10

0x21bee4 ADD	-0x838(%R8,%R9,1),%R10    [16]

0x21beec MOV	-0x880(%R8,%R9,1),%R8    [16]

0x21bef4 ADD	%RDI,%R10

0x21bef7 MOVQ	$0,-0x8(%R8,%R10,8)    [15]

0x21bf00 MOV	0x630(%R14),%R9    [13]

0x21bf07 MOV	0x5e8(%R14),%R8    [13]

0x21bf0e ADD	%RDX,%R9

0x21bf11 IMUL	$0x1780,%R9,%R9

0x21bf18 MOV	-0x710(%R8,%R9,1),%R10    [14]

0x21bf20 IMUL	%RAX,%R10

0x21bf24 ADD	-0x778(%R8,%R9,1),%R10    [14]

0x21bf2c MOV	-0x7c0(%R8,%R9,1),%R8    [14]

0x21bf34 ADD	%RDI,%R10

0x21bf37 MOVQ	$0,-0x8(%R8,%R10,8)    [12]

0x21bf40 MOV	0x630(%R14),%R9    [13]

0x21bf47 MOV	0x5e8(%R14),%R8    [13]

0x21bf4e ADD	%RDX,%R9

0x21bf51 IMUL	$0x1780,%R9,%R9

0x21bf58 MOV	-0x1190(%R8,%R9,1),%R10    [11]

0x21bf60 IMUL	%RAX,%R10

0x21bf64 ADD	-0x11f8(%R8,%R9,1),%R10    [11]

0x21bf6c MOV	-0x1240(%R8,%R9,1),%R8    [11]

0x21bf74 ADD	%RDI,%R10

0x21bf77 MOVQ	$0,-0x8(%R8,%R10,8)    [10]

0x21bf80 MOV	0x630(%R14),%R9    [13]

0x21bf87 MOV	0x5e8(%R14),%R8    [13]

0x21bf8e ADD	%RDX,%R9

0x21bf91 IMUL	$0x1780,%R9,%R9

0x21bf98 MOV	-0x10d0(%R8,%R9,1),%R10    [9]

0x21bfa0 IMUL	%RAX,%R10

0x21bfa4 ADD	-0x1138(%R8,%R9,1),%R10    [9]

0x21bfac MOV	-0x1180(%R8,%R9,1),%R8    [9]

0x21bfb4 ADD	%RDI,%R10

0x21bfb7 MOVQ	$0,-0x8(%R8,%R10,8)    [8]

0x21bfc0 MOV	0x630(%R14),%R9    [13]

0x21bfc7 MOV	0x5e8(%R14),%R8    [13]

0x21bfce ADD	%RDX,%R9

0x21bfd1 IMUL	$0x1780,%R9,%R9

0x21bfd8 MOV	-0x1010(%R8,%R9,1),%R10    [7]

0x21bfe0 IMUL	%RAX,%R10

0x21bfe4 ADD	-0x1078(%R8,%R9,1),%R10    [7]

0x21bfec MOV	-0x10c0(%R8,%R9,1),%R8    [7]

0x21bff4 ADD	%RDI,%R10

0x21bff7 MOVQ	$0,-0x8(%R8,%R10,8)    [6]

0x21c000 MOV	0x630(%R14),%R9    [13]

0x21c007 MOV	0x5e8(%R14),%R8    [13]

0x21c00e ADD	%RDX,%R9

0x21c011 IMUL	$0x1780,%R9,%R9

0x21c018 MOV	-0xf50(%R8,%R9,1),%R10    [5]

0x21c020 IMUL	%RAX,%R10

0x21c024 ADD	-0xfb8(%R8,%R9,1),%R10    [5]

0x21c02c MOV	-0x1000(%R8,%R9,1),%R8    [5]

0x21c034 ADD	%RDI,%R10

0x21c037 INC	%RDI

0x21c03a MOVQ	$0,-0x8(%R8,%R10,8)    [4]

0x21c043 CMP	%RDI,%RSI

0x21c046 JNE	21bd80

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/build_field.f90: 104 - 116

--------------------------------------------------------------------------------

104:         chunk%tiles(tile)%field%work_array1(j,k)=0.0

105:         chunk%tiles(tile)%field%work_array2(j,k)=0.0

106:         chunk%tiles(tile)%field%work_array3(j,k)=0.0

107:         chunk%tiles(tile)%field%work_array4(j,k)=0.0

108:         chunk%tiles(tile)%field%work_array5(j,k)=0.0

109:         chunk%tiles(tile)%field%work_array6(j,k)=0.0

110:         chunk%tiles(tile)%field%work_array7(j,k)=0.0

111:

112:         chunk%tiles(tile)%field%xvel0(j,k)=0.0

113:         chunk%tiles(tile)%field%xvel1(j,k)=0.0

114:         chunk%tiles(tile)%field%yvel0(j,k)=0.0

115:         chunk%tiles(tile)%field%yvel1(j,k)=0.0

116:       ENDDO

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P6, P7, P8, P9,
Function	__nv_build_field__PARALLEL_F2L100_1
Source	build_field.f90:104-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.50
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	16.50
CQA cycles if fully vectorized	1.03
Front-end cycles	14.00
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	9.50
P6 cycles	16.50
P7 cycles	16.50
P8 cycles	16.50
P9 cycles	16.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	113.00
Nb uops	112.00
Nb loads	55.00
Nb stores	11.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	440.00
Bytes stored	88.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	22.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P6, P7, P8, P9,
Function	__nv_build_field__PARALLEL_F2L100_1
Source	build_field.f90:104-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.50
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	16.50
CQA cycles if fully vectorized	1.03
Front-end cycles	14.00
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	9.50
P6 cycles	16.50
P7 cycles	16.50
P8 cycles	16.50
P9 cycles	16.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	113.00
Nb uops	112.00
Nb loads	55.00
Nb stores	11.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	440.00
Bytes stored	88.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	22.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_build_field__PARALLEL_F2L100_1
Source file and lines	build_field.f90:104-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/build_field.f90:104-116.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 16.50 to 1.03 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 16.50 to 14.00 cycles (1.18x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 22 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 440 bytes. The binary loop is storing 88 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually.

General properties

nb instructions	113
nb uops	112
loop length	716
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	9.50	9.50	9.50	9.50	9.50	9.50	16.50	16.50	16.50	16.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	9.50	9.50	9.50	9.50	9.50	9.50	16.50	16.50	16.50	16.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.00
Dispatch	16.50
Data deps.	1.00
Overall L1	16.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

10% of peak load performance is reached (26.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 21bd80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xb90(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xbf8(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0xc40(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xad0(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xb38(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0xb80(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xa10(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xa78(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0xac0(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x950(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x9b8(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0xa00(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x890(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x8f8(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x940(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x7d0(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x838(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x880(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x710(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x778(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x7c0(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1190(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x11f8(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1240(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x10d0(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1138(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1180(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1010(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1078(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x10c0(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xf50(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xfb8(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1000(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 21bd80 <__nv_build_field__PARALLEL_F2L100_1_+0x800>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Function	__nv_build_field__PARALLEL_F2L100_1
Source file and lines	build_field.f90:104-116
Module	exec

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 16.50 to 14.00 cycles (1.18x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 22 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 440 bytes. The binary loop is storing 88 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually.

General properties

nb instructions	113
nb uops	112
loop length	716
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	9.50	9.50	9.50	9.50	9.50	9.50	16.50	16.50	16.50	16.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	9.50	9.50	9.50	9.50	9.50	9.50	16.50	16.50	16.50	16.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.00
Dispatch	16.50
Data deps.	1.00
Overall L1	16.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

10% of peak load performance is reached (26.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 21bd80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xb90(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xbf8(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0xc40(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xad0(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xb38(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0xb80(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xa10(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xa78(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0xac0(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x950(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x9b8(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0xa00(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x890(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x8f8(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x940(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x7d0(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x838(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x880(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x710(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x778(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x7c0(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1190(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x11f8(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1240(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x10d0(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1138(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1180(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1010(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1078(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x10c0(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R9,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0xf50(%R8,%R9,1),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0xfb8(%R8,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1000(%R8,%R9,1),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R8,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 21bd80 <__nv_build_field__PARALLEL_F2L100_1_+0x800>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code