OV - exec - Loop 19

	Loop Id: 19	Module: exec	Source: build_field.f90:123-131	Coverage: 0.06%

0x21c2b0 MOV	0x630(%R14),%R10    [16]

0x21c2b7 MOV	0x5e8(%R14),%R9    [16]

0x21c2be ADD	%RDI,%R10

0x21c2c1 IMUL	$0x1780,%R10,%R10

0x21c2c8 MOV	-0x16d0(%R9,%R10,1),%R11    [17]

0x21c2d0 IMUL	%RAX,%R11

0x21c2d4 ADD	-0x1738(%R9,%R10,1),%R11    [17]

0x21c2dc MOV	-0x1780(%R9,%R10,1),%R9    [17]

0x21c2e4 ADD	%R8,%R11

0x21c2e7 MOVQ	$0,-0x8(%R9,%R11,8)    [15]

0x21c2f0 MOV	0x630(%R14),%R10    [16]

0x21c2f7 MOV	0x5e8(%R14),%R9    [16]

0x21c2fe ADD	%RDI,%R10

0x21c301 IMUL	$0x1780,%R10,%R10

0x21c308 MOV	-0x1610(%R9,%R10,1),%R11    [14]

0x21c310 IMUL	%RAX,%R11

0x21c314 ADD	-0x1678(%R9,%R10,1),%R11    [14]

0x21c31c MOV	-0x16c0(%R9,%R10,1),%R9    [14]

0x21c324 ADD	%R8,%R11

0x21c327 MOVQ	$0,-0x8(%R9,%R11,8)    [13]

0x21c330 MOV	0x630(%R14),%R10    [16]

0x21c337 MOV	0x5e8(%R14),%R9    [16]

0x21c33e ADD	%RDI,%R10

0x21c341 IMUL	$0x1780,%R10,%R10

0x21c348 MOV	-0x1550(%R9,%R10,1),%R11    [12]

0x21c350 IMUL	%RAX,%R11

0x21c354 ADD	-0x15b8(%R9,%R10,1),%R11    [12]

0x21c35c MOV	-0x1600(%R9,%R10,1),%R9    [12]

0x21c364 ADD	%R8,%R11

0x21c367 MOVQ	$0,-0x8(%R9,%R11,8)    [11]

0x21c370 MOV	0x630(%R14),%R10    [16]

0x21c377 MOV	0x5e8(%R14),%R9    [16]

0x21c37e ADD	%RDI,%R10

0x21c381 IMUL	$0x1780,%R10,%R10

0x21c388 MOV	-0x1490(%R9,%R10,1),%R11    [10]

0x21c390 IMUL	%RAX,%R11

0x21c394 ADD	-0x14f8(%R9,%R10,1),%R11    [10]

0x21c39c MOV	-0x1540(%R9,%R10,1),%R9    [10]

0x21c3a4 ADD	%R8,%R11

0x21c3a7 MOVQ	$0,-0x8(%R9,%R11,8)    [9]

0x21c3b0 MOV	0x630(%R14),%R10    [16]

0x21c3b7 MOV	0x5e8(%R14),%R9    [16]

0x21c3be ADD	%RDI,%R10

0x21c3c1 IMUL	$0x1780,%R10,%R10

0x21c3c8 MOV	-0x13d0(%R9,%R10,1),%R11    [8]

0x21c3d0 IMUL	%RAX,%R11

0x21c3d4 ADD	-0x1438(%R9,%R10,1),%R11    [8]

0x21c3dc MOV	-0x1480(%R9,%R10,1),%R9    [8]

0x21c3e4 ADD	%R8,%R11

0x21c3e7 MOVQ	$0,-0x8(%R9,%R11,8)    [7]

0x21c3f0 MOV	0x630(%R14),%R10    [16]

0x21c3f7 MOV	0x5e8(%R14),%R9    [16]

0x21c3fe ADD	%RDI,%R10

0x21c401 IMUL	$0x1780,%R10,%R10

0x21c408 MOV	-0x1310(%R9,%R10,1),%R11    [6]

0x21c410 IMUL	%RAX,%R11

0x21c414 ADD	-0x1378(%R9,%R10,1),%R11    [6]

0x21c41c MOV	-0x13c0(%R9,%R10,1),%R9    [6]

0x21c424 ADD	%R8,%R11

0x21c427 MOVQ	$0,-0x8(%R9,%R11,8)    [5]

0x21c430 MOV	0x630(%R14),%R10    [16]

0x21c437 MOV	0x5e8(%R14),%R9    [16]

0x21c43e ADD	%RDI,%R10

0x21c441 IMUL	$0x1780,%R10,%R10

0x21c448 MOV	-0x1250(%R9,%R10,1),%R11    [4]

0x21c450 IMUL	%RAX,%R11

0x21c454 ADD	-0x12b8(%R9,%R10,1),%R11    [4]

0x21c45c MOV	-0x1300(%R9,%R10,1),%R9    [4]

0x21c464 ADD	%R8,%R11

0x21c467 MOVQ	$0,-0x8(%R9,%R11,8)    [3]

0x21c470 MOV	0x630(%R14),%R10    [16]

0x21c477 MOV	0x5e8(%R14),%R9    [16]

0x21c47e ADD	%RDI,%R10

0x21c481 IMUL	$0x1780,%R10,%R10

0x21c488 MOV	-0x1d0(%R9,%R10,1),%R11    [2]

0x21c490 IMUL	%RAX,%R11

0x21c494 ADD	-0x238(%R9,%R10,1),%R11    [2]

0x21c49c MOV	-0x280(%R9,%R10,1),%R9    [2]

0x21c4a4 LEA	0x1(%RSI,%R8,1),%R10

0x21c4a9 ADD	%R8,%R11

0x21c4ac INC	%R8

0x21c4af MOVQ	$0,-0x8(%R9,%R11,8)    [1]

0x21c4b8 CMP	$0x1,%R10

0x21c4bc JNE	21c2b0

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/build_field.f90: 123 - 131

--------------------------------------------------------------------------------

123:         chunk%tiles(tile)%field%density0(j,k)=0.0

124:         chunk%tiles(tile)%field%density1(j,k)=0.0

125:         chunk%tiles(tile)%field%energy0(j,k)=0.0

126:         chunk%tiles(tile)%field%energy1(j,k)=0.0

127:         chunk%tiles(tile)%field%pressure(j,k)=0.0

128:         chunk%tiles(tile)%field%viscosity(j,k)=0.0

129:         chunk%tiles(tile)%field%soundspeed(j,k)=0.0

130:         chunk%tiles(tile)%field%volume(j,k)=0.0

131:       ENDDO

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P6, P7, P8, P9,
Function	__nv_build_field__PARALLEL_F2L100_1
Source	build_field.f90:123-131
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	12.25
CQA cycles if FP arith vectorized	12.25
CQA cycles if fully vectorized	0.77
Front-end cycles	10.50
P0 cycles	7.17
P1 cycles	7.17
P2 cycles	7.17
P3 cycles	7.17
P4 cycles	7.17
P5 cycles	7.17
P6 cycles	12.25
P7 cycles	12.25
P8 cycles	12.25
P9 cycles	12.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	84.00
Nb uops	84.00
Nb loads	40.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.35
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P6, P7, P8, P9,
Function	__nv_build_field__PARALLEL_F2L100_1
Source	build_field.f90:123-131
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	12.25
CQA cycles if FP arith vectorized	12.25
CQA cycles if fully vectorized	0.77
Front-end cycles	10.50
P0 cycles	7.17
P1 cycles	7.17
P2 cycles	7.17
P3 cycles	7.17
P4 cycles	7.17
P5 cycles	7.17
P6 cycles	12.25
P7 cycles	12.25
P8 cycles	12.25
P9 cycles	12.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	84.00
Nb uops	84.00
Nb loads	40.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.35
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_build_field__PARALLEL_F2L100_1
Source file and lines	build_field.f90:123-131
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/build_field.f90:123-131.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 12.25 to 0.77 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 12.25 to 10.50 cycles (1.17x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/build_field.f90:130

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually.

General properties

nb instructions	84
nb uops	84
loop length	530
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.17	7.17	7.17	7.17	7.17	7.17	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.17	7.17	7.17	7.17	7.17	7.17	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.50
Dispatch	12.25
Data deps.	1.00
Overall L1	12.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

10% of peak load performance is reached (26.12 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 21c2b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x16d0(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1738(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1780(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1610(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1678(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x16c0(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1550(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x15b8(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1600(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1490(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x14f8(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1540(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x13d0(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1438(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1480(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1310(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1378(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x13c0(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1250(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x12b8(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1300(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1d0(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x238(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x280(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RSI,%R8,1),%R10	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP $0x1,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 21c2b0 <__nv_build_field__PARALLEL_F2L100_1_+0xd30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Function	__nv_build_field__PARALLEL_F2L100_1
Source file and lines	build_field.f90:123-131
Module	exec

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 12.25 to 10.50 cycles (1.17x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/build_field.f90:130

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually.

General properties

nb instructions	84
nb uops	84
loop length	530
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.17	7.17	7.17	7.17	7.17	7.17	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.17	7.17	7.17	7.17	7.17	7.17	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.50
Dispatch	12.25
Data deps.	1.00
Overall L1	12.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

10% of peak load performance is reached (26.12 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 21c2b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x16d0(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1738(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1780(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1610(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1678(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x16c0(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1550(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x15b8(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1600(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1490(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x14f8(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1540(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x13d0(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1438(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1480(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1310(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x1378(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x13c0(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1250(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x12b8(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x1300(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV 0x630(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x5e8(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL $0x1780,%R10,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV -0x1d0(%R9,%R10,1),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %RAX,%R11	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD -0x238(%R9,%R10,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV -0x280(%R9,%R10,1),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RSI,%R8,1),%R10	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x8(%R9,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP $0x1,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 21c2b0 <__nv_build_field__PARALLEL_F2L100_1_+0xd30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

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Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code