| Loop Id: 134 | Module: exec | Source: advec_mom_kernel.f90:152-177 | Coverage: 4.30% |
|---|
| Loop Id: 134 | Module: exec | Source: advec_mom_kernel.f90:152-177 | Coverage: 4.30% |
|---|
0x22d8f0 VSUBSD %XMM8,%XMM2,%XMM8 |
0x22d8f5 INC %RCX |
0x22d8f8 VMULSD %XMM12,%XMM8,%XMM8 |
0x22d8fd VADDSD %XMM8,%XMM9,%XMM8 |
0x22d902 VMULSD %XMM7,%XMM8,%XMM7 |
0x22d906 VMOVSD %XMM7,(%RBP,%RDI,8) [9] |
0x22d90c INC %RDI |
0x22d90f CMP %RDI,%RDX |
0x22d912 JE 22d8a0 |
0x22d914 VMOVSD (%R15,%RDI,8),%XMM7 [4] |
0x22d91a LEA (%R8,%RCX,1),%RBX |
0x22d91e VUCOMISD %XMM7,%XMM0 |
0x22d922 JA 22d940 |
0x22d924 MOV (%RSP),%R9 [2] |
0x22d928 LEA -0x1(%RCX),%EAX |
0x22d92b LEA (%R12,%RDI,1),%R13 |
0x22d92f ADD %EDI,%R9D |
0x22d932 JMP 22d94f |
0x22d940 MOV %RBX,%R13 |
0x22d943 LEA 0x1(%RCX),%R9D |
0x22d947 LEA (%R12,%RDI,1),%RBX |
0x22d94b LEA 0x1(%RSI,%RDI,1),%EAX |
0x22d94f VANDPD %XMM1,%XMM7,%XMM8 |
0x22d953 VDIVSD (%R10,%RBX,8),%XMM8,%XMM8 [1] |
0x22d959 CLTQ |
0x22d95b VMOVSD (%R11,%RBX,8),%XMM9 [3] |
0x22d961 VMOVSD (%R11,%R13,8),%XMM10 [3] |
0x22d967 VXORPD %XMM12,%XMM12,%XMM12 |
0x22d96c ADD %R8,%RAX |
0x22d96f VSUBSD (%R11,%RAX,8),%XMM9,%XMM11 [3] |
0x22d975 VSUBSD %XMM9,%XMM10,%XMM10 |
0x22d97a VMULSD %XMM10,%XMM11,%XMM13 |
0x22d97f VUCOMISD %XMM12,%XMM13 |
0x22d984 JBE 22d8f0 |
0x22d98a MOV 0x118(%R14),%RBX [6] |
0x22d991 MOV 0x110(%R14),%RAX [6] |
0x22d998 VADDSD %XMM2,%XMM8,%XMM12 |
0x22d99c MOVSXD %R9D,%R9 |
0x22d99f VANDPD %XMM3,%XMM11,%XMM11 |
0x22d9a3 VSUBSD %XMM8,%XMM4,%XMM15 |
0x22d9a8 VANDPD %XMM3,%XMM10,%XMM14 |
0x22d9ac VCMPSD $0x3,%XMM11,%XMM11,%K1 |
0x22d9b3 VMULSD %XMM11,%XMM12,%XMM12 |
0x22d9b8 VMULSD %XMM14,%XMM15,%XMM15 |
0x22d9bd MOV (%RBX),%RBX [5] |
0x22d9c0 LEA (,%RBX,8),%R13 |
0x22d9c8 SUB %RBX,%R9 |
0x22d9cb VDIVSD (%RAX,%R9,8),%XMM12,%XMM12 [8] |
0x22d9d1 SUB %R13,%RAX |
0x22d9d4 ADD 0x8(%RSP),%RAX [2] |
0x22d9d9 VMOVSD (%RAX,%RDI,8),%XMM13 [7] |
0x22d9de VDIVSD %XMM13,%XMM15,%XMM15 |
0x22d9e3 VADDSD %XMM12,%XMM15,%XMM12 |
0x22d9e8 VMULSD %XMM12,%XMM13,%XMM12 |
0x22d9ed VDIVSD %XMM5,%XMM12,%XMM12 |
0x22d9f1 VMINSD %XMM11,%XMM12,%XMM13 |
0x22d9f6 VMOVSD %XMM12,%XMM13,%XMM13{%K1} |
0x22d9fc VCMPSD $0x3,%XMM14,%XMM14,%K1 |
0x22da03 VMINSD %XMM14,%XMM13,%XMM11 |
0x22da08 VMOVSD %XMM13,%XMM11,%XMM11{%K1} |
0x22da0e VCMPSD $0x6,%XMM0,%XMM10,%K1 |
0x22da15 VXORPD %XMM6,%XMM11,%XMM12 |
0x22da19 VMOVSD %XMM11,%XMM12,%XMM12{%K1} |
0x22da1f JMP 22d8f0 |
/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 152 - 177 |
-------------------------------------------------------------------------------- |
152: IF(node_flux(j,k).LT.0.0)THEN |
153: upwind=j+2 |
154: donor=j+1 |
155: downwind=j |
156: dif=donor |
157: ELSE |
158: upwind=j-1 |
159: donor=j |
160: downwind=j+1 |
161: dif=upwind |
162: ENDIF |
163: sigma=ABS(node_flux(j,k))/(node_mass_pre(donor,k)) |
164: width=celldx(j) |
165: vdiffuw=vel1(donor,k)-vel1(upwind,k) |
166: vdiffdw=vel1(downwind,k)-vel1(donor,k) |
167: limiter=0.0 |
168: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
169: auw=ABS(vdiffuw) |
170: adw=ABS(vdiffdw) |
171: wind=1.0_8 |
172: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
173: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldx(dif))/6.0_8,auw,adw) |
174: ENDIF |
175: advec_vel_s=vel1(donor,k)+(1.0-sigma)*limiter |
176: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
177: ENDDO |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 4.37 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.72 |
| Bottlenecks | |
| Function | __nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1 |
| Source | advec_mom_kernel.f90:152-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 10.00 |
| CQA cycles if no scalar integer | 10.00 |
| CQA cycles if FP arith vectorized | 2.29 |
| CQA cycles if fully vectorized | 1.25 |
| Front-end cycles | 5.75 |
| P0 cycles | 2.42 |
| P1 cycles | 2.42 |
| P2 cycles | 2.42 |
| P3 cycles | 2.42 |
| P4 cycles | 2.42 |
| P5 cycles | 2.42 |
| P6 cycles | 2.50 |
| P7 cycles | 2.50 |
| P8 cycles | 2.50 |
| P9 cycles | 2.50 |
| P10 cycles | 5.13 |
| P11 cycles | 5.13 |
| P12 cycles | 5.38 |
| P13 cycles | 5.38 |
| P14 cycles | 1.50 |
| P15 cycles | 1.50 |
| DIV/SQRT cycles | 10.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 44.50 |
| Nb uops | 46.00 |
| Nb loads | 8.50 |
| Nb stores | 1.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 1.25 |
| Nb FLOP add-sub | 5.50 |
| Nb FLOP mul | 4.50 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 2.50 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 9.63 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 68.00 |
| Bytes stored | 8.00 |
| Stride 0 | 1.25 |
| Stride 1 | 3.50 |
| Stride n | 0.00 |
| Stride unknown | 1.50 |
| Stride indirect | 0.50 |
| Vectorization ratio all | 11.69 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 31.37 |
| Vector-efficiency ratio all | 13.88 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.19 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 16.42 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 5.45 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.06 |
| Bottlenecks | P10, P11, |
| Function | __nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1 |
| Source | advec_mom_kernel.f90:152-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 2.94 |
| CQA cycles if fully vectorized | 2.00 |
| Front-end cycles | 7.63 |
| P0 cycles | 3.00 |
| P1 cycles | 3.00 |
| P2 cycles | 3.00 |
| P3 cycles | 3.00 |
| P4 cycles | 3.00 |
| P5 cycles | 3.00 |
| P6 cycles | 3.25 |
| P7 cycles | 3.25 |
| P8 cycles | 3.25 |
| P9 cycles | 3.25 |
| P10 cycles | 7.75 |
| P11 cycles | 7.75 |
| P12 cycles | 7.75 |
| P13 cycles | 7.75 |
| P14 cycles | 1.50 |
| P15 cycles | 1.50 |
| DIV/SQRT cycles | 16.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 60.00 |
| Nb uops | 61.00 |
| Nb loads | 12.00 |
| Nb stores | 1.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 1.06 |
| Nb FLOP add-sub | 7.00 |
| Nb FLOP mul | 6.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 6.50 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 96.00 |
| Bytes stored | 8.00 |
| Stride 0 | 2.00 |
| Stride 1 | 5.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 1.00 |
| Vectorization ratio all | 12.82 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 29.41 |
| Vector-efficiency ratio all | 14.10 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 16.18 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.29 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.03 |
| Bottlenecks | P10, P11, |
| Function | __nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1 |
| Source | advec_mom_kernel.f90:152-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 4.00 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 1.75 |
| CQA cycles if fully vectorized | 0.50 |
| Front-end cycles | 3.88 |
| P0 cycles | 2.00 |
| P1 cycles | 2.00 |
| P2 cycles | 2.00 |
| P3 cycles | 2.00 |
| P4 cycles | 2.00 |
| P5 cycles | 2.00 |
| P6 cycles | 1.75 |
| P7 cycles | 1.75 |
| P8 cycles | 1.75 |
| P9 cycles | 1.75 |
| P10 cycles | 2.50 |
| P11 cycles | 2.50 |
| P12 cycles | 3.00 |
| P13 cycles | 3.00 |
| P14 cycles | 1.50 |
| P15 cycles | 1.50 |
| DIV/SQRT cycles | 4.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 30.00 |
| Nb uops | 31.00 |
| Nb loads | 6.00 |
| Nb stores | 1.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 2.00 |
| Nb FLOP add-sub | 4.00 |
| Nb FLOP mul | 3.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 14.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 48.00 |
| Bytes stored | 8.00 |
| Stride 0 | 1.00 |
| Stride 1 | 4.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 10.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 33.33 |
| Vector-efficiency ratio all | 13.44 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 11.25 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 16.67 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 5.45 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.06 |
| Bottlenecks | P10, P11, |
| Function | __nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1 |
| Source | advec_mom_kernel.f90:152-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 2.94 |
| CQA cycles if fully vectorized | 2.00 |
| Front-end cycles | 7.63 |
| P0 cycles | 2.83 |
| P1 cycles | 2.83 |
| P2 cycles | 2.83 |
| P3 cycles | 2.83 |
| P4 cycles | 2.83 |
| P5 cycles | 2.83 |
| P6 cycles | 3.25 |
| P7 cycles | 3.25 |
| P8 cycles | 3.25 |
| P9 cycles | 3.25 |
| P10 cycles | 7.75 |
| P11 cycles | 7.75 |
| P12 cycles | 7.75 |
| P13 cycles | 7.75 |
| P14 cycles | 1.50 |
| P15 cycles | 1.50 |
| DIV/SQRT cycles | 16.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 59.00 |
| Nb uops | 61.00 |
| Nb loads | 11.00 |
| Nb stores | 1.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 1.06 |
| Nb FLOP add-sub | 7.00 |
| Nb FLOP mul | 6.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 6.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 88.00 |
| Bytes stored | 8.00 |
| Stride 0 | 2.00 |
| Stride 1 | 3.00 |
| Stride n | 0.00 |
| Stride unknown | 3.00 |
| Stride indirect | 1.00 |
| Vectorization ratio all | 12.82 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 29.41 |
| Vector-efficiency ratio all | 14.10 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 16.18 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.60 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.03 |
| Bottlenecks | P10, P11, |
| Function | __nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1 |
| Source | advec_mom_kernel.f90:152-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 4.00 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 1.54 |
| CQA cycles if fully vectorized | 0.50 |
| Front-end cycles | 3.88 |
| P0 cycles | 1.83 |
| P1 cycles | 1.83 |
| P2 cycles | 1.83 |
| P3 cycles | 1.83 |
| P4 cycles | 1.83 |
| P5 cycles | 1.83 |
| P6 cycles | 1.75 |
| P7 cycles | 1.75 |
| P8 cycles | 1.75 |
| P9 cycles | 1.75 |
| P10 cycles | 2.50 |
| P11 cycles | 2.50 |
| P12 cycles | 3.00 |
| P13 cycles | 3.00 |
| P14 cycles | 1.50 |
| P15 cycles | 1.50 |
| DIV/SQRT cycles | 4.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 29.00 |
| Nb uops | 31.00 |
| Nb loads | 5.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.00 |
| Nb FLOP add-sub | 4.00 |
| Nb FLOP mul | 3.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 40.00 |
| Bytes stored | 8.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 11.11 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 33.33 |
| Vector-efficiency ratio all | 13.89 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 16.67 |
| Path / |
| Function | __nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1 |
| Source file and lines | advec_mom_kernel.f90:152-177 |
| Module | exec |
 |
| nb instructions | 44.50 |
| nb uops | 46 |
| loop length | 203.50 |
| used x86 registers | 14.75 |
| used mmx registers | 0 |
| used xmm registers | 13 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 1 |
| ADD-SUB / MUL ratio | 1.25 |
| micro-operation queue | 5.75 cycles |
| front end | 5.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.42 | 2.42 | 2.42 | 2.42 | 2.42 | 2.42 | 2.50 | 2.50 | 2.50 | 2.50 | 5.13 | 5.13 | 5.38 | 5.38 | 1.50 | 1.50 |
| cycles | 2.42 | 2.42 | 2.42 | 2.42 | 2.42 | 2.42 | 2.50 | 2.50 | 2.50 | 2.50 | 5.13 | 5.13 | 5.38 | 5.38 | 1.50 | 1.50 |
| Cycles executing div or sqrt instructions | 10.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 5.75 |
| Dispatch | 5.38 |
| DIV/SQRT | 10.00 |
| Data deps. | 0.00 |
| Overall L1 | 10.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 13% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 41% |
| all | 11% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 31% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 6% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 17% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 16% |
| Function | __nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1 |
| Source file and lines | advec_mom_kernel.f90:152-177 |
| Module | exec |
|
| nb instructions | 60 |
| nb uops | 61 |
| loop length | 281 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 16 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| ADD-SUB / MUL ratio | 1.17 |
| micro-operation queue | 7.63 cycles |
| front end | 7.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 3.25 | 3.25 | 3.25 | 3.25 | 7.75 | 7.75 | 7.75 | 7.75 | 1.50 | 1.50 |
| cycles | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 3.25 | 3.25 | 3.25 | 3.25 | 7.75 | 7.75 | 7.75 | 7.75 | 1.50 | 1.50 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 7.63 |
| Dispatch | 7.75 |
| DIV/SQRT | 16.00 |
| Data deps. | 0.00 |
| Overall L1 | 16.00 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 13% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 33% |
| all | 12% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 29% |
| all | 12% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 16% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 16% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VSUBSD %XMM8,%XMM2,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| INC %RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMULSD %XMM12,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VADDSD %XMM8,%XMM9,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD %XMM7,%XMM8,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD %XMM7,(%RBP,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| INC %RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %RDI,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| JE 22d8a0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2200> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| VMOVSD (%R15,%RDI,8),%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R8,%RCX,1),%RBX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| VUCOMISD %XMM7,%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 0.50 | scal (12.5%) |
| JA 22d940 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x22a0> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| MOV (%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| LEA -0x1(%RCX),%EAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LEA (%R12,%RDI,1),%R13 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD %EDI,%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JMP 22d94f <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x22af> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
| VANDPD %XMM1,%XMM7,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | vect (25.0%) |
| VDIVSD (%R10,%RBX,8),%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| CLTQ | scal (12.5%) | |||||||||||||||||||
| VMOVSD (%R11,%RBX,8),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R11,%R13,8),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VXORPD %XMM12,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| ADD %R8,%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VSUBSD (%R11,%RAX,8),%XMM9,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VSUBSD %XMM9,%XMM10,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD %XMM10,%XMM11,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VUCOMISD %XMM12,%XMM13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 0.50 | scal (12.5%) |
| JBE 22d8f0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2250> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| MOV 0x118(%R14),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| MOV 0x110(%R14),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VADDSD %XMM2,%XMM8,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| MOVSXD %R9D,%R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VANDPD %XMM3,%XMM11,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | vect (25.0%) |
| VSUBSD %XMM8,%XMM4,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VANDPD %XMM3,%XMM10,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | vect (25.0%) |
| VCMPSD $0x3,%XMM11,%XMM11,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMULSD %XMM11,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMULSD %XMM14,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| MOV (%RBX),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| LEA (,%RBX,8),%R13 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB %RBX,%R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VDIVSD (%RAX,%R9,8),%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| SUB %R13,%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD 0x8(%RSP),%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| VMOVSD (%RAX,%RDI,8),%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VDIVSD %XMM13,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VADDSD %XMM12,%XMM15,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD %XMM12,%XMM13,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VDIVSD %XMM5,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VMINSD %XMM11,%XMM12,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMOVSD %XMM12,%XMM13,%XMM13{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| VCMPSD $0x3,%XMM14,%XMM14,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMINSD %XMM14,%XMM13,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMOVSD %XMM13,%XMM11,%XMM11{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| VCMPSD $0x6,%XMM0,%XMM10,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VXORPD %XMM6,%XMM11,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | vect (25.0%) |
| VMOVSD %XMM11,%XMM12,%XMM12{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| JMP 22d8f0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2250> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
| Function | __nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1 |
| Source file and lines | advec_mom_kernel.f90:152-177 |
| Module | exec |
|
| nb instructions | 30 |
| nb uops | 31 |
| loop length | 127 |
| used x86 registers | 14 |
| used mmx registers | 0 |
| used xmm registers | 10 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 1 |
| ADD-SUB / MUL ratio | 1.33 |
| micro-operation queue | 3.88 cycles |
| front end | 3.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 2.00 | 2.00 | 2.00 | 2.00 | 2.00 | 1.75 | 1.75 | 1.75 | 1.75 | 2.50 | 2.50 | 3.00 | 3.00 | 1.50 | 1.50 |
| cycles | 2.00 | 2.00 | 2.00 | 2.00 | 2.00 | 2.00 | 1.75 | 1.75 | 1.75 | 1.75 | 2.50 | 2.50 | 3.00 | 3.00 | 1.50 | 1.50 |
| Cycles executing div or sqrt instructions | 4.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 3.88 |
| Dispatch | 3.00 |
| DIV/SQRT | 4.00 |
| Data deps. | 0.00 |
| Overall L1 | 4.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 50% |
| all | 10% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 33% |
| all | 10% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 6% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 18% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 11% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 16% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VSUBSD %XMM8,%XMM2,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| INC %RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMULSD %XMM12,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VADDSD %XMM8,%XMM9,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD %XMM7,%XMM8,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD %XMM7,(%RBP,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| INC %RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %RDI,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| JE 22d8a0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2200> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| VMOVSD (%R15,%RDI,8),%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R8,%RCX,1),%RBX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| VUCOMISD %XMM7,%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 0.50 | scal (12.5%) |
| JA 22d940 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x22a0> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| MOV (%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (12.5%) |
| LEA -0x1(%RCX),%EAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LEA (%R12,%RDI,1),%R13 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD %EDI,%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| JMP 22d94f <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x22af> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
| VANDPD %XMM1,%XMM7,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | vect (25.0%) |
| VDIVSD (%R10,%RBX,8),%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| CLTQ | scal (12.5%) | |||||||||||||||||||
| VMOVSD (%R11,%RBX,8),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R11,%R13,8),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VXORPD %XMM12,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| ADD %R8,%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VSUBSD (%R11,%RAX,8),%XMM9,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VSUBSD %XMM9,%XMM10,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD %XMM10,%XMM11,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VUCOMISD %XMM12,%XMM13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 0.50 | scal (12.5%) |
| JBE 22d8f0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2250> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| Function | __nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1 |
| Source file and lines | advec_mom_kernel.f90:152-177 |
| Module | exec |
|
| nb instructions | 59 |
| nb uops | 61 |
| loop length | 280 |
| used x86 registers | 16 |
| used mmx registers | 0 |
| used xmm registers | 16 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 1 |
| ADD-SUB / MUL ratio | 1.17 |
| micro-operation queue | 7.63 cycles |
| front end | 7.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.83 | 2.83 | 2.83 | 2.83 | 2.83 | 2.83 | 3.25 | 3.25 | 3.25 | 3.25 | 7.75 | 7.75 | 7.75 | 7.75 | 1.50 | 1.50 |
| cycles | 2.83 | 2.83 | 2.83 | 2.83 | 2.83 | 2.83 | 3.25 | 3.25 | 3.25 | 3.25 | 7.75 | 7.75 | 7.75 | 7.75 | 1.50 | 1.50 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 7.63 |
| Dispatch | 7.75 |
| DIV/SQRT | 16.00 |
| Data deps. | 0.00 |
| Overall L1 | 16.00 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 13% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 33% |
| all | 12% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 29% |
| all | 12% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 16% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 16% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VSUBSD %XMM8,%XMM2,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| INC %RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMULSD %XMM12,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VADDSD %XMM8,%XMM9,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD %XMM7,%XMM8,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD %XMM7,(%RBP,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| INC %RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %RDI,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| JE 22d8a0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2200> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| VMOVSD (%R15,%RDI,8),%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R8,%RCX,1),%RBX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| VUCOMISD %XMM7,%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 0.50 | scal (12.5%) |
| JA 22d940 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x22a0> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| MOV %RBX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| LEA 0x1(%RCX),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LEA (%R12,%RDI,1),%RBX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LEA 0x1(%RSI,%RDI,1),%EAX | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VANDPD %XMM1,%XMM7,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | vect (25.0%) |
| VDIVSD (%R10,%RBX,8),%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| CLTQ | scal (12.5%) | |||||||||||||||||||
| VMOVSD (%R11,%RBX,8),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R11,%R13,8),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VXORPD %XMM12,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| ADD %R8,%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VSUBSD (%R11,%RAX,8),%XMM9,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VSUBSD %XMM9,%XMM10,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD %XMM10,%XMM11,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VUCOMISD %XMM12,%XMM13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 0.50 | scal (12.5%) |
| JBE 22d8f0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2250> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| MOV 0x118(%R14),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| MOV 0x110(%R14),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VADDSD %XMM2,%XMM8,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| MOVSXD %R9D,%R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VANDPD %XMM3,%XMM11,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | vect (25.0%) |
| VSUBSD %XMM8,%XMM4,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VANDPD %XMM3,%XMM10,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | vect (25.0%) |
| VCMPSD $0x3,%XMM11,%XMM11,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMULSD %XMM11,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMULSD %XMM14,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| MOV (%RBX),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| LEA (,%RBX,8),%R13 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB %RBX,%R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VDIVSD (%RAX,%R9,8),%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| SUB %R13,%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD 0x8(%RSP),%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| VMOVSD (%RAX,%RDI,8),%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VDIVSD %XMM13,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VADDSD %XMM12,%XMM15,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD %XMM12,%XMM13,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VDIVSD %XMM5,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| VMINSD %XMM11,%XMM12,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMOVSD %XMM12,%XMM13,%XMM13{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| VCMPSD $0x3,%XMM14,%XMM14,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMINSD %XMM14,%XMM13,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMOVSD %XMM13,%XMM11,%XMM11{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| VCMPSD $0x6,%XMM0,%XMM10,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VXORPD %XMM6,%XMM11,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | vect (25.0%) |
| VMOVSD %XMM11,%XMM12,%XMM12{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| JMP 22d8f0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2250> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
| Function | __nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1 |
| Source file and lines | advec_mom_kernel.f90:152-177 |
| Module | exec |
|
| nb instructions | 29 |
| nb uops | 31 |
| loop length | 126 |
| used x86 registers | 14 |
| used mmx registers | 0 |
| used xmm registers | 10 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.33 |
| micro-operation queue | 3.88 cycles |
| front end | 3.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.83 | 1.83 | 1.83 | 1.83 | 1.83 | 1.83 | 1.75 | 1.75 | 1.75 | 1.75 | 2.50 | 2.50 | 3.00 | 3.00 | 1.50 | 1.50 |
| cycles | 1.83 | 1.83 | 1.83 | 1.83 | 1.83 | 1.83 | 1.75 | 1.75 | 1.75 | 1.75 | 2.50 | 2.50 | 3.00 | 3.00 | 1.50 | 1.50 |
| Cycles executing div or sqrt instructions | 4.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 3.88 |
| Dispatch | 3.00 |
| DIV/SQRT | 4.00 |
| Data deps. | 0.00 |
| Overall L1 | 4.00 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 50% |
| all | 11% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 33% |
| all | 12% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 18% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 16% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VSUBSD %XMM8,%XMM2,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| INC %RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMULSD %XMM12,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VADDSD %XMM8,%XMM9,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD %XMM7,%XMM8,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VMOVSD %XMM7,(%RBP,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (12.5%) |
| INC %RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %RDI,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| JE 22d8a0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2200> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| VMOVSD (%R15,%RDI,8),%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| LEA (%R8,%RCX,1),%RBX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| VUCOMISD %XMM7,%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 0.50 | scal (12.5%) |
| JA 22d940 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x22a0> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| MOV %RBX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| LEA 0x1(%RCX),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LEA (%R12,%RDI,1),%RBX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LEA 0x1(%RSI,%RDI,1),%EAX | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VANDPD %XMM1,%XMM7,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | vect (25.0%) |
| VDIVSD (%R10,%RBX,8),%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 4 | scal (12.5%) |
| CLTQ | scal (12.5%) | |||||||||||||||||||
| VMOVSD (%R11,%RBX,8),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VMOVSD (%R11,%R13,8),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VXORPD %XMM12,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| ADD %R8,%RAX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VSUBSD (%R11,%RAX,8),%XMM9,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VSUBSD %XMM9,%XMM10,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | scal (12.5%) |
| VMULSD %XMM10,%XMM11,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VUCOMISD %XMM12,%XMM13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 0.50 | scal (12.5%) |
| JBE 22d8f0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__PARALLEL_F2L79_1_+0x2250> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |