OV - exec - Loop 1141

	Loop Id: 1141	Module: exec	Source: viscosity_kernel.f90:56-92	Coverage: 2.20%

0x26b930 MOV	0xc8(%R14),%RDI    [8]

0x26b937 VXORPD	%XMM7,%XMM7,%XMM7

0x26b93b ADD	%R15,%RDI

0x26b93e VMOVSD	%XMM7,(%RDI,%RBP,8)    [9]

0x26b943 INC	%RBP

0x26b946 CMP	%RBP,%RDX

0x26b949 JE	26b8d0

0x26b94b VMOVUPD	(%R9,%RBP,8),%XMM7    [3]

0x26b951 VMOVSD	-0x10(%RAX,%RBP,8),%XMM13    [10]

0x26b957 VMOVSD	(%RAX,%RBP,8),%XMM14    [10]

0x26b95c VMOVUPD	(%RSI,%RBP,8),%XMM8    [5]

0x26b961 VMOVLPD	(%R10,%RBP,8),%XMM7,%XMM9    [4]

0x26b967 VMOVDDUP	(%RSI,%RBP,8),%XMM7    [5]

0x26b96c VMOVLPD	-0x8(%R10,%RBP,8),%XMM8,%XMM10    [4]

0x26b973 VMOVHPD	(%R13,%RBP,8),%XMM14,%XMM14    [7]

0x26b97a VMOVHPD	(%RBX,%RBP,8),%XMM13,%XMM13    [11]

0x26b97f VMOVLPD	-0x8(%R8,%RBP,8),%XMM7,%XMM11    [1]

0x26b986 VMOVDDUP	(%R9,%RBP,8),%XMM7    [3]

0x26b98c VMOVLPD	(%R8,%RBP,8),%XMM7,%XMM12    [1]

0x26b992 VMOVUPD	(%R12,%RBP,8),%XMM7    [6]

0x26b998 VADDPD	0x8(%R12,%RBP,8){1to2},%XMM7,%XMM8    [6]

0x26b9a0 VSUBPD	%XMM13,%XMM14,%XMM13

0x26b9a5 VADDPD	%XMM11,%XMM10,%XMM14

0x26b9aa VUNPCKLPD	%XMM6,%XMM8,%XMM8

0x26b9ae VDIVPD	%XMM8,%XMM13,%XMM8

0x26b9b3 VADDPD	%XMM12,%XMM9,%XMM13

0x26b9b8 VSUBPD	%XMM14,%XMM13,%XMM13

0x26b9bd VSHUFPD	$0x1,%XMM13,%XMM13,%XMM14

0x26b9c3 VMULSD	%XMM7,%XMM13,%XMM15

0x26b9c7 VMULSD	%XMM5,%XMM14,%XMM14

0x26b9cb VADDSD	%XMM15,%XMM14,%XMM16

0x26b9d1 VMULPD	%XMM8,%XMM8,%XMM15

0x26b9d6 VUCOMISD	%XMM2,%XMM16

0x26b9dc VSHUFPD	$0x1,%XMM15,%XMM15,%XMM14

0x26b9e2 VADDSD	%XMM14,%XMM15,%XMM14

0x26b9e7 VMAXSD	%XMM1,%XMM14,%XMM14

0x26b9eb JAE	26b930

0x26b9f1 VADDPD	%XMM10,%XMM9,%XMM9

0x26b9f6 VUNPCKLPD	%XMM7,%XMM5,%XMM10

0x26b9fa VSUBPD	%XMM11,%XMM9,%XMM9

0x26b9ff VMULPD	%XMM0,%XMM13,%XMM11

0x26ba03 VSUBPD	%XMM12,%XMM9,%XMM9

0x26ba08 VUNPCKLPD	%XMM5,%XMM7,%XMM12

0x26ba0c VDIVPD	%XMM12,%XMM11,%XMM11

0x26ba11 VMULPD	%XMM0,%XMM9,%XMM9

0x26ba15 VDIVPD	%XMM10,%XMM9,%XMM9

0x26ba1a VMULPD	%XMM15,%XMM11,%XMM11

0x26ba1f VSHUFPD	$0x1,%XMM11,%XMM11,%XMM12

0x26ba25 VADDSD	%XMM12,%XMM11,%XMM11

0x26ba2a VSHUFPD	$0x1,%XMM9,%XMM9,%XMM10

0x26ba30 VADDSD	%XMM10,%XMM9,%XMM9

0x26ba35 VSHUFPD	$0x1,%XMM8,%XMM8,%XMM10

0x26ba3b VMULSD	%XMM8,%XMM9,%XMM9

0x26ba40 VMULSD	%XMM10,%XMM9,%XMM9

0x26ba45 VADDSD	%XMM11,%XMM9,%XMM9

0x26ba4a VDIVSD	%XMM14,%XMM9,%XMM9

0x26ba4f VUCOMISD	%XMM2,%XMM9

0x26ba53 JA	26b930

0x26ba59 VANDPD	%XMM3,%XMM8,%XMM11

0x26ba5d VCMPSD	$0x5,%XMM2,%XMM8,%K1

0x26ba64 VANDPD	%XMM3,%XMM10,%XMM8

0x26ba68 MOV	0xd0(%R14),%R11    [8]

0x26ba6f MOV	0xc8(%R14),%RDI    [8]

0x26ba76 VMAXSD	%XMM1,%XMM11,%XMM11

0x26ba7a VMAXSD	%XMM1,%XMM8,%XMM8

0x26ba7e VXORPD	%XMM4,%XMM11,%XMM12

0x26ba82 VXORPD	%XMM4,%XMM8,%XMM10

0x26ba86 VMOVSD	%XMM11,%XMM12,%XMM12{%K1}

0x26ba8c VCMPSD	$0x5,%XMM2,%XMM12,%K1

0x26ba93 ADD	%R15,%R11

0x26ba96 VMOVSD	%XMM8,%XMM10,%XMM10{%K1}

0x26ba9c VMULSD	%XMM12,%XMM12,%XMM8

0x26baa1 VMULSD	%XMM10,%XMM10,%XMM11

0x26baa6 VADDSD	%XMM11,%XMM8,%XMM8

0x26baab VSQRTSD	%XMM8,%XMM8,%XMM8

0x26bab0 VMULSD	%XMM7,%XMM8,%XMM7

0x26bab4 VMULSD	%XMM5,%XMM8,%XMM8

0x26bab8 VDIVSD	%XMM12,%XMM7,%XMM7

0x26babd VDIVSD	%XMM10,%XMM8,%XMM8

0x26bac2 VANDPD	%XMM3,%XMM8,%XMM8

0x26bac6 VANDPD	%XMM3,%XMM7,%XMM7

0x26baca VMINSD	%XMM8,%XMM7,%XMM10

0x26bacf VCMPSD	$0x3,%XMM8,%XMM8,%K1

0x26bad6 VMOVSD	(%R11,%RBP,8),%XMM8    [2]

0x26badc VMOVSD	%XMM7,%XMM10,%XMM10{%K1}

0x26bae2 VMULSD	%XMM10,%XMM10,%XMM7

0x26bae7 VADDSD	%XMM8,%XMM8,%XMM8

0x26baec VMULSD	%XMM7,%XMM8,%XMM7

0x26baf0 VMULSD	%XMM7,%XMM9,%XMM7

0x26baf4 VMULSD	%XMM7,%XMM9,%XMM7

0x26baf8 JMP	26b93b

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 56 - 92

--------------------------------------------------------------------------------

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

90:         ENDIF

91:

92:       ENDDO

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.01
CQA speedup if fully vectorized	5.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.61
Bottlenecks
Function	__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1
Source	viscosity_kernel.f90:56-92
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.17
CQA cycles if no scalar integer	18.17
CQA cycles if FP arith vectorized	6.04
CQA cycles if fully vectorized	3.36
Front-end cycles	7.88
P0 cycles	1.06
P1 cycles	1.06
P2 cycles	1.06
P3 cycles	1.06
P4 cycles	1.06
P5 cycles	1.06
P6 cycles	4.17
P7 cycles	4.17
P8 cycles	4.17
P9 cycles	4.17
P10 cycles	11.67
P11 cycles	11.67
P12 cycles	11.67
P13 cycles	11.67
P14 cycles	1.33
P15 cycles	1.33
DIV/SQRT cycles	17.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.33
Nb uops	63.00
Nb loads	15.67
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.04
Nb FLOP add-sub	18.67
Nb FLOP mul	12.00
Nb FLOP fma	0.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.33
Nb FLOP rsqrt	0.00
Bytes/cycle	13.33
Bytes prefetched	0.00
Bytes loaded	149.33
Bytes stored	8.00
Stride 0	1.00
Stride 1	3.33
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	41.75
Vectorization ratio load	27.94
Vectorization ratio store	0.00
Vectorization ratio mul	36.11
Vectorization ratio add_sub	62.10
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	72.62
Vectorization ratio other	46.91
Vector-efficiency ratio all	17.72
Vector-efficiency ratio load	15.99
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	17.01
Vector-efficiency ratio add_sub	20.26
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	21.58
Vector-efficiency ratio other	18.36

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.55
CQA speedup if fully vectorized	5.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P10, P11, P12, P13,
Function	__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1
Source	viscosity_kernel.f90:56-92
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	3.88
CQA cycles if fully vectorized	1.03
Front-end cycles	4.75
P0 cycles	0.83
P1 cycles	0.83
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	38.00
Nb loads	15.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	12.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.33
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	8.00
Stride 0	1.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	41.94
Vectorization ratio load	28.57
Vectorization ratio store	0.00
Vectorization ratio mul	33.33
Vectorization ratio add_sub	71.43
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	17.74
Vector-efficiency ratio load	16.07
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	16.67
Vector-efficiency ratio add_sub	21.43
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.97
CQA speedup if fully vectorized	5.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.81
Bottlenecks	P10, P11,
Function	__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1
Source	viscosity_kernel.f90:56-92
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	8.19
CQA cycles if fully vectorized	5.56
Front-end cycles	11.38
P0 cycles	1.33
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	18.00
P11 cycles	18.00
P12 cycles	18.00
P13 cycles	18.00
P14 cycles	1.50
P15 cycles	1.50
DIV/SQRT cycles	32.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	91.00
Nb loads	17.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.63
Nb FLOP add-sub	23.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	9.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.17
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	8.00
Stride 0	1.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	36.25
Vectorization ratio load	26.67
Vectorization ratio store	0.00
Vectorization ratio mul	25.00
Vectorization ratio add_sub	53.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	42.86
Vectorization ratio other	40.74
Vector-efficiency ratio all	17.03
Vector-efficiency ratio load	15.83
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	15.63
Vector-efficiency ratio add_sub	19.17
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	17.86
Vector-efficiency ratio other	17.59

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.64
CQA speedup if fully vectorized	4.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P10, P11,
Function	__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1
Source	viscosity_kernel.f90:56-92
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	6.06
CQA cycles if fully vectorized	3.50
Front-end cycles	7.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	11.00
P13 cycles	11.00
P14 cycles	1.50
P15 cycles	1.50
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	60.00
Nb loads	15.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	21.00
Nb FLOP mul	12.00
Nb FLOP fma	0.00
Nb FLOP div	7.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.50
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	8.00
Stride 0	1.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	47.06
Vectorization ratio load	28.57
Vectorization ratio store	0.00
Vectorization ratio mul	50.00
Vectorization ratio add_sub	61.54
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	75.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	18.38
Vector-efficiency ratio load	16.07
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	18.75
Vector-efficiency ratio add_sub	20.19
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	21.88
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1
Source file and lines	viscosity_kernel.f90:56-92
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56-92.

The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 18.17 to 3.36 cycles (5.40x speedup).

Details

41% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

27% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
62% of SSE/AVX addition or subtraction instructions are used in vector version.
36% of SSE/AVX multiply instructions are used in vector version.
72% of SSE/AVX divide and square root instructions are used in vector version.
46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.17 to 11.67 cycles (1.56x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 0 occurrences

Type of elements and instruction set

17 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 37 FP arithmetical operations:

18.67: addition or subtraction
12: multiply
6: divide
0.33: square root

The binary loop is loading 149 bytes (18 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.

General properties

nb instructions	61.33
nb uops	63
loop length	313.33
used x86 registers	13.33
used mmx registers	0
used xmm registers	15.33
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.63

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.06	1.06	1.06	1.06	1.06	1.06	4.17	4.17	4.17	4.17	11.67	11.67	11.67	11.67	1.33	1.33
cycles	1.06	1.06	1.06	1.06	1.06	1.06	4.17	4.17	4.17	4.17	11.67	11.67	11.67	11.67	1.33	1.33

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	17.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	7.88
Dispatch	11.67
DIV/SQRT	17.50
Data deps.	0.00
Overall L1	18.17

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	41%
load	27%
store	0%
mul	36%
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	72%
other	47%

INT+FP

all	41%
load	27%
store	0%
mul	36%
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	72%
other	46%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	15%
store	12%
mul	17%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	21%
other	18%

INT+FP

all	17%
load	15%
store	12%
mul	17%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	21%
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.17 cycles. At this rate:

4% of peak load performance is reached (12.64 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.69 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1
Source file and lines	viscosity_kernel.f90:56-92
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

41% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
71% of SSE/AVX addition or subtraction instructions are used in vector version.
33% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.75 cycles (1.26x speedup).

Workaround

Reduce the number of FP add instructions
Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:74

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

12: addition or subtraction
4: multiply
2: divide

The binary loop is loading 144 bytes (18 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually.

General properties

nb instructions	37
nb uops	38
loop length	193
used x86 registers	13
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	2.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.83	0.83	0.83	0.83	0.83	0.83	4.00	4.00	4.00	4.00	6.00	6.00	6.00	6.00	1.00	1.00
cycles	0.83	0.83	0.83	0.83	0.83	0.83	4.00	4.00	4.00	4.00	6.00	6.00	6.00	6.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.75
Dispatch	6.00
DIV/SQRT	4.00
Data deps.	0.00
Overall L1	6.00

Vectorization ratios

all	41%
load	28%
store	0%
mul	33%
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	50%

Vector efficiency ratios

all	17%
load	16%
store	12%
mul	16%
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

9% of peak load performance is reached (24.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 26b94b

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0xc8(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,(%RDI,%RBP,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBP,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 26b8d0 <__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1_+0x1d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R9,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x10(%RAX,%RBP,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX,%RBP,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVUPD (%RSI,%RBP,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVLPD (%R10,%RBP,8),%XMM7,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP (%RSI,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVLPD -0x8(%R10,%RBP,8),%XMM8,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R13,%RBP,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RBX,%RBP,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVLPD -0x8(%R8,%RBP,8),%XMM7,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP (%R9,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVLPD (%R8,%RBP,8),%XMM7,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVUPD (%R12,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x8(%R12,%RBP,8){1to2},%XMM7,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM13,%XMM14,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD %XMM11,%XMM10,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKLPD %XMM6,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VDIVPD %XMM8,%XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (25.0%)
VADDPD %XMM12,%XMM9,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM14,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM13,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULSD %XMM7,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM5,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM14,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULPD %XMM8,%XMM8,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VUCOMISD %XMM2,%XMM16	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM15,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM14,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM1,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
JAE 26b930 <__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1_+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1
Source file and lines	viscosity_kernel.f90:56-92
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

26% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
53% of SSE/AVX addition or subtraction instructions are used in vector version.
25% of SSE/AVX multiply instructions are used in vector version.
42% of SSE/AVX divide and square root instructions are used in vector version.
40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 32.50 to 18.00 cycles (1.81x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.50 to 18.00 cycles (1.81x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:74

Type of elements and instruction set

32 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 15 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 53 FP arithmetical operations:

23: addition or subtraction
20: multiply
9: divide
1: square root

The binary loop is loading 160 bytes (20 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	89
nb uops	91
loop length	450
used x86 registers	14
used mmx registers	0
used xmm registers	17
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.94

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.38 cycles
front end	11.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.33	1.33	1.33	4.50	4.50	4.50	4.50	18.00	18.00	18.00	18.00	1.50	1.50
cycles	1.33	1.33	1.33	1.33	1.33	1.33	4.50	4.50	4.50	4.50	18.00	18.00	18.00	18.00	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	32.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	11.38
Dispatch	18.00
DIV/SQRT	32.50
Data deps.	0.00
Overall L1	32.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	36%
load	26%
store	0%
mul	25%
add-sub	53%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	42%
other	42%

INT+FP

all	36%
load	26%
store	0%
mul	25%
add-sub	53%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	42%
other	40%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	15%
store	12%
mul	15%
add-sub	19%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	17%
other	17%

INT+FP

all	17%
load	15%
store	12%
mul	15%
add-sub	19%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	17%
other	17%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.50 cycles. At this rate:

1% of peak load performance is reached (4.92 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 26b94b

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,(%RDI,%RBP,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBP,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 26b8d0 <__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1_+0x1d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R9,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x10(%RAX,%RBP,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX,%RBP,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVUPD (%RSI,%RBP,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVLPD (%R10,%RBP,8),%XMM7,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP (%RSI,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVLPD -0x8(%R10,%RBP,8),%XMM8,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R13,%RBP,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RBX,%RBP,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVLPD -0x8(%R8,%RBP,8),%XMM7,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP (%R9,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVLPD (%R8,%RBP,8),%XMM7,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVUPD (%R12,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x8(%R12,%RBP,8){1to2},%XMM7,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM13,%XMM14,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD %XMM11,%XMM10,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKLPD %XMM6,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VDIVPD %XMM8,%XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (25.0%)
VADDPD %XMM12,%XMM9,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM14,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM13,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULSD %XMM7,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM5,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM14,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULPD %XMM8,%XMM8,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VUCOMISD %XMM2,%XMM16	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM15,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM14,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM1,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
JAE 26b930 <__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1_+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VADDPD %XMM10,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKLPD %XMM7,%XMM5,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VSUBPD %XMM11,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD %XMM0,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM12,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKLPD %XMM5,%XMM7,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VDIVPD %XMM12,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (25.0%)
VMULPD %XMM0,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VDIVPD %XMM10,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (25.0%)
VMULPD %XMM15,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM11,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM12,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM10,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM8,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULSD %XMM8,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM10,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM11,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM14,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VUCOMISD %XMM2,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JA 26b930 <__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1_+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VANDPD %XMM3,%XMM8,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCMPSD $0x5,%XMM2,%XMM8,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VANDPD %XMM3,%XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV 0xd0(%R14),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc8(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMAXSD %XMM1,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM1,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VXORPD %XMM4,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VXORPD %XMM4,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVSD %XMM11,%XMM12,%XMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VCMPSD $0x5,%XMM2,%XMM12,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
ADD %R15,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM8,%XMM10,%XMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD %XMM12,%XMM12,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM10,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM11,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSQRTSD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
VMULSD %XMM7,%XMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM5,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VDIVSD %XMM12,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VDIVSD %XMM10,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VANDPD %XMM3,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VANDPD %XMM3,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMINSD %XMM8,%XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VCMPSD $0x3,%XMM8,%XMM8,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%R11,%RBP,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,%XMM10,%XMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD %XMM10,%XMM10,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM7,%XMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM7,%XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM7,%XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 26b93b <__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1_+0x23b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1
Source file and lines	viscosity_kernel.f90:56-92
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 3.50 cycles (4.57x speedup).

Details

47% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
61% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
75% of SSE/AVX divide and square root instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 11.00 cycles (1.45x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:74
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:74

Type of elements and instruction set

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 15 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

21: addition or subtraction
12: multiply
7: divide

The binary loop is loading 144 bytes (18 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	58
nb uops	60
loop length	297
used x86 registers	13
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.63

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	4.00	4.00	4.00	4.00	11.00	11.00	11.00	11.00	1.50	1.50
cycles	1.00	1.00	1.00	1.00	1.00	1.00	4.00	4.00	4.00	4.00	11.00	11.00	11.00	11.00	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	7.50
Dispatch	11.00
DIV/SQRT	16.00
Data deps.	0.00
Overall L1	16.00

Vectorization ratios

all	47%
load	28%
store	0%
mul	50%
add-sub	61%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	75%
other	50%

Vector efficiency ratios

all	18%
load	16%
store	12%
mul	18%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	21%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

3% of peak load performance is reached (9.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 26b94b

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0xc8(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,(%RDI,%RBP,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBP,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 26b8d0 <__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1_+0x1d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R9,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x10(%RAX,%RBP,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX,%RBP,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVUPD (%RSI,%RBP,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVLPD (%R10,%RBP,8),%XMM7,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP (%RSI,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVLPD -0x8(%R10,%RBP,8),%XMM8,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R13,%RBP,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RBX,%RBP,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVLPD -0x8(%R8,%RBP,8),%XMM7,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP (%R9,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVLPD (%R8,%RBP,8),%XMM7,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVUPD (%R12,%RBP,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x8(%R12,%RBP,8){1to2},%XMM7,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM13,%XMM14,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD %XMM11,%XMM10,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKLPD %XMM6,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VDIVPD %XMM8,%XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (25.0%)
VADDPD %XMM12,%XMM9,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM14,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM13,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULSD %XMM7,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM5,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM15,%XMM14,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULPD %XMM8,%XMM8,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VUCOMISD %XMM2,%XMM16	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM15,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM14,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMAXSD %XMM1,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
JAE 26b930 <__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1_+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VADDPD %XMM10,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKLPD %XMM7,%XMM5,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VSUBPD %XMM11,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD %XMM0,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM12,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKLPD %XMM5,%XMM7,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VDIVPD %XMM12,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (25.0%)
VMULPD %XMM0,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VDIVPD %XMM10,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (25.0%)
VMULPD %XMM15,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM11,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM12,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM10,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM8,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULSD %XMM8,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM10,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM11,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VDIVSD %XMM14,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VUCOMISD %XMM2,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JA 26b930 <__nv_viscosity_kernel_module_viscosity_kernel__PARALLEL_F2L50_1_+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

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Expensive FP math instructions/calls

Masked instructions

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FMA

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Complex instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

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Execution units bottlenecks

Workaround

FMA

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Complex instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

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Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

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FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details