OV - exec - Function __nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155

	Function: __nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3	Module: exec	Source: pack_kernel.f90:155-162	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 155 - 162

--------------------------------------------------------------------------------

155:     !$OMP PARALLEL DO PRIVATE(index)

156:     DO k=y_min-depth,y_max+y_inc+depth

157:     !$OMP SIMD

158:       DO j=1,depth

159:         index= buffer_offset + j+(k+depth-1)*depth

160:         right_snd_buffer(index)=field(x_max+1-j,k)

161:       ENDDO

162:     ENDDO

0x23b290 PUSH	%RBP

0x23b291 PUSH	%R15

0x23b293 PUSH	%R14

0x23b295 PUSH	%R13

0x23b297 PUSH	%R12

0x23b299 PUSH	%RBX

0x23b29a SUB	$0x68,%RSP

0x23b29e MOV	%RDX,%R14

0x23b2a1 MOV	(%RDX),%RAX

0x23b2a4 MOV	0x8(%RDX),%RBX

0x23b2a8 MOV	0x10(%RDX),%RDX

0x23b2ac MOVL	$0,0x24(%RSP)

0x23b2b4 MOV	(%RDI),%ESI

0x23b2b6 MOV	0x18(%R14),%RDI

0x23b2ba MOV	(%RBX),%ECX

0x23b2bc MOV	(%RDX),%EBP

0x23b2be MOV	(%RAX),%EAX

0x23b2c0 ADD	%ECX,%EBP

0x23b2c2 ADD	(%RDI),%EBP

0x23b2c4 SUB	%ECX,%EAX

0x23b2c6 MOVL	$0x1,0x20(%RSP)

0x23b2ce MOV	%EAX,0x4(%RSP)

0x23b2d2 MOV	%EBP,(%RSP)

0x23b2d5 SUB	$0x8,%RSP

0x23b2d9 LEA	0x28(%RSP),%RAX

0x23b2de LEA	0x2c(%RSP),%RCX

0x23b2e3 LEA	0xc(%RSP),%R8

0x23b2e8 LEA	0x8(%RSP),%R9

0x23b2ed XOR	%EDI,%EDI

0x23b2ef MOV	%ESI,0x18(%RSP)

0x23b2f3 MOV	$0x22,%EDX

0x23b2f8 PUSH	$0x1

0x23b2fa PUSH	$0x1

0x23b2fc PUSH	%RAX

0x23b2fd CALL	283090 <@plt_start@+0xa0>

0x23b302 ADD	$0x20,%RSP

0x23b306 MOVSXD	0x4(%RSP),%RAX

0x23b30b CMP	%EBP,%EAX

0x23b30d JG	23b59d

0x23b313 MOVSXD	(%RSP),%RCX

0x23b317 MOV	%RCX,0x60(%RSP)

0x23b31c CMP	%EAX,%ECX

0x23b31e JL	23b59d

0x23b324 MOV	(%RBX),%EDX

0x23b326 TEST	%EDX,%EDX

0x23b328 JLE	23b59d

0x23b32e MOV	0x80(%R14),%R9

0x23b335 MOV	0x20(%R14),%RCX

0x23b339 VMOVAPD	-0x2d703(%RIP),%ZMM0

0x23b343 MOV	0x28(%R14),%RSI

0x23b347 MOV	0x50(%R14),%R8

0x23b34b LEA	0x1(%RDX),%R15

0x23b34f XOR	%R12D,%R12D

0x23b352 MOV	%R15,0x48(%RSP)

0x23b357 MOV	(%R9),%R9

0x23b35a MOV	(%RCX),%EDI

0x23b35c MOV	0xa0(%R14),%RCX

0x23b363 MOV	%R9,0x58(%RSP)

0x23b368 MOV	0x98(%R14),%R9

0x23b36f MOV	(%RCX),%ECX

0x23b371 MOV	(%R9),%R10

0x23b374 MOV	0x48(%R14),%R9

0x23b378 LEA	-0x1(%RDX),%R14

0x23b37c MOV	%R14,0x50(%RSP)

0x23b381 MOV	(%R9),%R11

0x23b384 LEA	-0x1(%RDX,%RAX,1),%R9D

0x23b389 IMUL	%EDX,%R9D

0x23b38d LEA	(%RDI,%R9,1),%EBP

0x23b391 LEA	0x1(%RDI,%R9,1),%EDI

0x23b396 MOV	%ECX,%R9D

0x23b399 SUB	%R14D,%R9D

0x23b39c MOV	%R9D,0x14(%RSP)

0x23b3a1 MOV	%EDX,%R9D

0x23b3a4 AND	$-0x20,%R9D

0x23b3a8 MOV	%R9,0x8(%RSP)

0x23b3ad INC	%R9

0x23b3b0 MOV	%EDI,%R15D

0x23b3b3 MOV	%EDI,0x18(%RSP)

0x23b3b7 MOV	%R9,0x28(%RSP)

0x23b3bc MOV	%EDX,%R9D

0x23b3bf AND	$-0x4,%R9D

0x23b3c3 LEA	0x1(%R9),%RBX

0x23b3c7 MOV	%R9,0x40(%RSP)

0x23b3cc NEG	%R9

0x23b3cf MOV	%RBX,0x38(%RSP)

0x23b3d4 LEA	0x1(%RCX),%EBX

0x23b3d7 MOV	%R9,0x30(%RSP)

0x23b3dc MOV	%EBX,0x1c(%RSP)

0x23b3e0 JMP	23b40f

0x23b3e2 NOPW	%CS:(%RAX,%RAX,1)

(371) 0x23b3f0 MOV	0x50(%RSP),%R14

(371) 0x23b3f5 LEA	0x1(%RAX),%RDI

(371) 0x23b3f9 INC	%R12D

(371) 0x23b3fc ADD	%EDX,%R15D

(371) 0x23b3ff ADD	%EDX,%EBP

(371) 0x23b401 CMP	0x60(%RSP),%RAX

(371) 0x23b406 MOV	%RDI,%RAX

(371) 0x23b409 JE	23b59d

(371) 0x23b40f MOV	0x58(%RSP),%R9

(371) 0x23b414 MOV	$0x1,%EBX

(371) 0x23b419 IMUL	%RAX,%R9

(371) 0x23b41d CMP	$0x4,%EDX

(371) 0x23b420 JB	23b560

(371) 0x23b426 MOV	%R14,%RDI

(371) 0x23b429 SHR	$0x20,%RDI

(371) 0x23b42d JNE	23b560

(371) 0x23b433 MOV	%EDX,%EDI

(371) 0x23b435 IMUL	%R12D,%EDI

(371) 0x23b439 ADD	0x18(%RSP),%EDI

(371) 0x23b43d LEA	(%RDI,%R14,1),%R13D

(371) 0x23b441 CMP	%R13D,%EDI

(371) 0x23b444 JG	23b560

(371) 0x23b44a CMP	%ECX,0x14(%RSP)

(371) 0x23b44e JG	23b560

(371) 0x23b454 CMP	$0x20,%EDX

(371) 0x23b457 JAE	23b461

(371) 0x23b459 XOR	%R13D,%R13D

(371) 0x23b45c JMP	23b4f4

(371) 0x23b461 MOV	0x8(%RSP),%RDI

(371) 0x23b466 MOV	%ECX,%EBX

(371) 0x23b468 MOV	%R15D,%R13D

(371) 0x23b46b NOPL	(%RAX,%RAX,1)

  (372) 0x23b470 MOVSXD	%EBX,%RBX

  (372) 0x23b473 MOVSXD	%R13D,%R13

  (372) 0x23b476 LEA	(%R9,%RBX,1),%R14

  (372) 0x23b47a ADD	$-0x20,%EBX

  (372) 0x23b47d ADD	%R10,%R14

  (372) 0x23b480 VPERMPD	-0x40(%R8,%R14,8),%ZMM0,%ZMM1

  (372) 0x23b488 VPERMPD	-0x80(%R8,%R14,8),%ZMM0,%ZMM2

  (372) 0x23b490 VPERMPD	-0xc0(%R8,%R14,8),%ZMM0,%ZMM3

  (372) 0x23b498 VPERMPD	-0x100(%R8,%R14,8),%ZMM0,%ZMM4

  (372) 0x23b4a0 LEA	(%R11,%R13,1),%R14

  (372) 0x23b4a4 ADD	$0x20,%R13D

  (372) 0x23b4a8 ADD	$-0x20,%RDI

  (372) 0x23b4ac VMOVUPD	%ZMM1,-0x8(%RSI,%R14,8)

  (372) 0x23b4b7 VMOVUPD	%ZMM2,0x38(%RSI,%R14,8)

  (372) 0x23b4c2 VMOVUPD	%ZMM3,0x78(%RSI,%R14,8)

  (372) 0x23b4cd VMOVUPD	%ZMM4,0xb8(%RSI,%R14,8)

  (372) 0x23b4d8 JNE	23b470

(371) 0x23b4da CMP	%RDX,0x8(%RSP)

(371) 0x23b4df JE	23b3f0

(371) 0x23b4e5 MOV	0x8(%RSP),%R13

(371) 0x23b4ea MOV	0x28(%RSP),%RBX

(371) 0x23b4ef TEST	$0x1c,%DL

(371) 0x23b4f2 JE	23b560

(371) 0x23b4f4 MOV	%ECX,%EDI

(371) 0x23b4f6 LEA	(%R15,%R13,1),%EBX

(371) 0x23b4fa SUB	%R13D,%EDI

(371) 0x23b4fd ADD	0x30(%RSP),%R13

(371) 0x23b502 NOPW	%CS:(%RAX,%RAX,1)

  (373) 0x23b510 MOVSXD	%EDI,%RDI

  (373) 0x23b513 MOVSXD	%EBX,%RBX

  (373) 0x23b516 LEA	(%R9,%RDI,1),%R14

  (373) 0x23b51a ADD	$-0x4,%EDI

  (373) 0x23b51d ADD	%R10,%R14

  (373) 0x23b520 VPERMILPD	$0x1,-0x20(%R8,%R14,8),%XMM1

  (373) 0x23b528 VPERMILPD	$0x1,-0x10(%R8,%R14,8),%XMM2

  (373) 0x23b530 LEA	(%R11,%RBX,1),%R14

  (373) 0x23b534 ADD	$0x4,%EBX

  (373) 0x23b537 ADD	$0x4,%R13

  (373) 0x23b53b VMOVUPD	%XMM1,0x8(%RSI,%R14,8)

  (373) 0x23b542 VMOVUPD	%XMM2,-0x8(%RSI,%R14,8)

  (373) 0x23b549 JNE	23b510

(371) 0x23b54b MOV	0x38(%RSP),%RBX

(371) 0x23b550 CMP	%RDX,0x40(%RSP)

(371) 0x23b555 JE	23b3f0

(371) 0x23b55b NOPL	(%RAX,%RAX,1)

(371) 0x23b560 MOV	0x48(%RSP),%R13

(371) 0x23b565 MOV	0x1c(%RSP),%EDI

(371) 0x23b569 SUB	%EBX,%EDI

(371) 0x23b56b SUB	%RBX,%R13

(371) 0x23b56e ADD	%EBP,%EBX

  (370) 0x23b570 MOVSXD	%EDI,%RDI

  (370) 0x23b573 MOVSXD	%EBX,%RBX

  (370) 0x23b576 LEA	(%R9,%RDI,1),%R14

  (370) 0x23b57a DEC	%EDI

  (370) 0x23b57c ADD	%R10,%R14

  (370) 0x23b57f VMOVSD	-0x8(%R8,%R14,8),%XMM1

  (370) 0x23b586 LEA	(%R11,%RBX,1),%R14

  (370) 0x23b58a INC	%EBX

  (370) 0x23b58c DEC	%R13

  (370) 0x23b58f VMOVSD	%XMM1,-0x8(%RSI,%R14,8)

  (370) 0x23b596 JNE	23b570

(371) 0x23b598 JMP	23b3f0

0x23b59d MOV	0x10(%RSP),%ESI

0x23b5a1 XOR	%EDI,%EDI

0x23b5a3 VZEROUPPER

0x23b5a6 CALL	2830a0 <@plt_start@+0xb0>

0x23b5ab ADD	$0x68,%RSP

0x23b5af POP	%RBX

0x23b5b0 POP	%R12

0x23b5b2 POP	%R13

0x23b5b4 POP	%R14

0x23b5b6 POP	%R15

0x23b5b8 POP	%RBP

0x23b5b9 RET

0x23b5ba NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	pack_kernel.f90:155-162
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:155-162.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.13 to 1.50 cycles (8.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.13 to 9.67 cycles (1.36x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:156
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:162

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:161
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:161

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	103
nb uops	105
loop length	387
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	1
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.13 cycles
front end	13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.17	6.17	6.17	6.17	6.17	6.17	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.17	6.17	6.17	6.17	6.17	6.17	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.13
Dispatch	11.75
Overall L1	13.13

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	19%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.13 cycles. At this rate:

6% of peak load performance is reached (16.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.13 to 11.75 cycles (1.12x speedup).

ASM code

In the binary file, the address of the function is: 23b290

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVL $0,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%RAX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %ECX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD (%RDI),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
SUB %ECX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVL $0x1,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EAX,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EBP,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x28(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x2c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xc(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x8(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 283090 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD 0x4(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
CMP %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JG 23b59d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOVSXD (%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %RCX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JL 23b59d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EDX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 23b59d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x80(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVAPD -0x2d703(%RIP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV 0x28(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x50(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA 0x1(%RDX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %R15,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0xa0(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x98(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x48(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R14,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R9),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA -0x1(%RDX,%RAX,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
IMUL %EDX,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDI,%R9,1),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x1(%RDI,%R9,1),%EDI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R14D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %EDI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R9,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%R9),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
NEG %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0x1(%RCX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EBX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
JMP 23b40f <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x17f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x10(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2830a0 <@plt_start@+0xb0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	pack_kernel.f90:155-162
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.13 to 1.50 cycles (8.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:156
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:162

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:161
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:161

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	103
nb uops	105
loop length	387
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	1
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.13 cycles
front end	13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.17	6.17	6.17	6.17	6.17	6.17	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.17	6.17	6.17	6.17	6.17	6.17	11.75	11.75	11.75	11.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.13
Dispatch	11.75
Overall L1	13.13

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	19%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.13 cycles. At this rate:

6% of peak load performance is reached (16.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 23b290

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVL $0,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%RAX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %ECX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD (%RDI),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
SUB %ECX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVL $0x1,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EAX,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EBP,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x28(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x2c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xc(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x8(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 283090 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD 0x4(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
CMP %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JG 23b59d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOVSXD (%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %RCX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JL 23b59d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EDX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 23b59d <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x30d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x80(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVAPD -0x2d703(%RIP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV 0x28(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x50(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA 0x1(%RDX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %R15,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0xa0(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x98(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x48(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R14,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R9),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA -0x1(%RDX,%RAX,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
IMUL %EDX,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDI,%R9,1),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x1(%RDI,%R9,1),%EDI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R14D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %EDI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R9,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%R9),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
NEG %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RBX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0x1(%RCX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EBX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
JMP 23b40f <__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3_+0x17f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x10(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2830a0 <@plt_start@+0xb0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼__nv_pack_kernel_module_clover_pack_message_right__PARALLEL_F2L155_3–	0.01	0.00
▼Loop 371 - pack_kernel.f90:160-162 - exec–	0.00	0.00
○Loop 370 - pack_kernel.f90:160-161 - exec	0.01	0.01
○Loop 373 - pack_kernel.f90:160-160 - exec	0.00	0.00
○Loop 372 - pack_kernel.f90:160-160 - exec	0.00	0.00

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