OV - exec - Function __nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89

	Function: __nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1	Module: exec	Source: calc_dt_kernel.f90:89-135 [...]	Coverage (incl. loops): 3.43% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 135

--------------------------------------------------------------------------------

89:     !$OMP PARALLEL

90:

91:     !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val)

92:     DO k=y_min,y_max

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

[...]

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

130:

131:       ENDDO

132:     ENDDO

133:     !$OMP END DO

134:

135:     !$OMP END PARALLEL

0x231c20 PUSH	%RBP

0x231c21 PUSH	%R15

0x231c23 PUSH	%R14

0x231c25 PUSH	%R13

0x231c27 PUSH	%R12

0x231c29 PUSH	%RBX

0x231c2a SUB	$0x68,%RSP

0x231c2e MOV	0x8(%RDX),%RAX

0x231c32 MOV	0x10(%RDX),%RCX

0x231c36 MOVL	$0,0x14(%RSP)

0x231c3e MOV	(%RDI),%ESI

0x231c40 MOV	%RDX,%R14

0x231c43 MOV	(%RAX),%EAX

0x231c45 MOV	(%RCX),%EBX

0x231c47 MOVL	$0x1,0x10(%RSP)

0x231c4f MOV	%EAX,0x8(%RSP)

0x231c53 MOV	%EBX,0x4(%RSP)

0x231c57 SUB	$0x8,%RSP

0x231c5b LEA	0x18(%RSP),%RAX

0x231c60 LEA	0x1c(%RSP),%RCX

0x231c65 LEA	0x10(%RSP),%R8

0x231c6a LEA	0xc(%RSP),%R9

0x231c6f XOR	%EDI,%EDI

0x231c71 MOV	%ESI,0x14(%RSP)

0x231c75 MOV	$0x22,%EDX

0x231c7a PUSH	$0x1

0x231c7c PUSH	$0x1

0x231c7e PUSH	%RAX

0x231c7f CALL	283090 <@plt_start@+0xa0>

0x231c84 ADD	$0x20,%RSP

0x231c88 VMOVSD	-0x2fdc2(%RIP),%XMM20

0x231c92 MOVSXD	0x8(%RSP),%RAX

0x231c97 CMP	%EBX,%EAX

0x231c99 JG	231ca4

0x231c9b MOVSXD	0x4(%RSP),%RSI

0x231ca0 CMP	%EAX,%ESI

0x231ca2 JGE	231d07

0x231ca4 MOV	0xc(%RSP),%EBX

0x231ca8 VMOVAPD	%XMM20,0x20(%RSP)

0x231cb0 XOR	%EDI,%EDI

0x231cb2 MOV	%EBX,%ESI

0x231cb4 CALL	2830a0 <@plt_start@+0xb0>

0x231cb9 CALL	283290 <@plt_start@+0x2a0>

0x231cbe CALL	283290 <@plt_start@+0x2a0>

0x231cc3 MOV	(%R14),%RAX

0x231cc6 VMOVAPD	0x20(%RSP),%XMM2

0x231ccc VMOVSD	(%RAX),%XMM0

0x231cd0 VCMPSD	$0x3,%XMM2,%XMM2,%K1

0x231cd7 VMINSD	%XMM2,%XMM0,%XMM1

0x231cdb VMOVSD	%XMM0,%XMM1,%XMM1{%K1}

0x231ce1 VMOVSD	%XMM1,(%RAX)

0x231ce5 CALL	2832a0 <@plt_start@+0x2b0>

0x231cea CALL	2832a0 <@plt_start@+0x2b0>

0x231cef XOR	%EDI,%EDI

0x231cf1 MOV	%EBX,%ESI

0x231cf3 CALL	2830b0 <@plt_start@+0xc0>

0x231cf8 ADD	$0x68,%RSP

0x231cfc POP	%RBX

0x231cfd POP	%R12

0x231cff POP	%R13

0x231d01 POP	%R14

0x231d03 POP	%R15

0x231d05 POP	%RBP

0x231d06 RET

0x231d07 MOV	0x18(%R14),%RCX

0x231d0b MOV	0x20(%R14),%RDX

0x231d0f VMOVSD	-0x2fe49(%RIP),%XMM20

0x231d19 VMOVDDUP	-0x2fe01(%RIP),%XMM0

0x231d21 VMOVDDUP	-0x2fe39(%RIP),%XMM2

0x231d29 VMOVSD	-0x2fe89(%RIP),%XMM3

0x231d31 LEA	(,%RAX,8),%R15

0x231d39 LEA	0x8(,%RAX,8),%RDI

0x231d41 VXORPD	%XMM1,%XMM1,%XMM1

0x231d45 MOV	%RSI,0x40(%RSP)

0x231d4a MOVSXD	(%RCX),%RCX

0x231d4d MOVSXD	(%RDX),%RDX

0x231d50 MOV	%RCX,%R8

0x231d53 DEC	%R8

0x231d56 MOV	%RDX,0x20(%RSP)

0x231d5b MOV	%RCX,0x38(%RSP)

0x231d60 MOV	%R8,0x30(%RSP)

0x231d65 JMP	231da2

0x231d67 NOPW	(%RAX,%RAX,1)

(211) 0x231d70 MOV	0x58(%RSP),%RAX

(211) 0x231d75 MOV	0x40(%RSP),%RSI

(211) 0x231d7a MOV	0x38(%RSP),%RCX

(211) 0x231d7f MOV	0x50(%RSP),%R15

(211) 0x231d84 MOV	0x18(%RSP),%RDI

(211) 0x231d89 MOV	0x48(%RSP),%RDX

(211) 0x231d8e ADD	$0x8,%R15

(211) 0x231d92 ADD	$0x8,%RDI

(211) 0x231d96 CMP	%RSI,%RAX

(211) 0x231d99 MOV	%RDX,%RAX

(211) 0x231d9c JE	231ca4

(211) 0x231da2 CMP	%ECX,0x20(%RSP)

(211) 0x231da6 JGE	231db0

(211) 0x231da8 LEA	0x1(%RAX),%RDX

(211) 0x231dac JMP	231d8e

0x231dae XCHG	%AX,%AX

(211) 0x231db0 MOV	0x40(%R14),%RCX

(211) 0x231db4 MOV	%RDI,0x18(%RSP)

(211) 0x231db9 MOV	%RAX,%RDX

(211) 0x231dbc MOV	0xc0(%R14),%R11

(211) 0x231dc3 MOV	0xe0(%R14),%R9

(211) 0x231dca MOV	%RAX,0x58(%RSP)

(211) 0x231dcf INC	%RAX

(211) 0x231dd2 MOV	0x28(%R14),%R10

(211) 0x231dd6 MOV	0x108(%R14),%R13

(211) 0x231ddd MOV	%R15,0x50(%RSP)

(211) 0x231de2 MOV	%RAX,0x48(%RSP)

(211) 0x231de7 MOV	(%RCX),%RSI

(211) 0x231dea MOV	0x88(%R14),%RCX

(211) 0x231df1 MOV	(%R11),%R12

(211) 0x231df4 MOV	(%R9),%R9

(211) 0x231df7 MOV	0x120(%R14),%R11

(211) 0x231dfe MOV	(%RCX),%RDI

(211) 0x231e01 MOV	0x48(%R14),%RCX

(211) 0x231e05 MOV	%R12,%RBP

(211) 0x231e08 IMUL	%R15,%RBP

(211) 0x231e0c SAL	$0x3,%R9

(211) 0x231e10 VMOVSD	(%R11),%XMM8

(211) 0x231e15 MOV	%RSI,%R11

(211) 0x231e18 IMUL	%R15,%R11

(211) 0x231e1c MOV	0x98(%R14),%R15

(211) 0x231e23 SUB	%R9,%RBP

(211) 0x231e26 LEA	(%R13,%RBP,1),%RBX

(211) 0x231e2b MOV	(%RCX),%R8

(211) 0x231e2e MOV	0x70(%R14),%RCX

(211) 0x231e32 SAL	$0x3,%RDI

(211) 0x231e36 SUB	%RDI,%R11

(211) 0x231e39 ADD	%R11,%R15

(211) 0x231e3c VADDSD	%XMM8,%XMM8,%XMM8

(211) 0x231e41 SUB	(%RCX),%RDX

(211) 0x231e44 MOV	0x50(%R14),%RCX

(211) 0x231e48 SAL	$0x3,%R8

(211) 0x231e4c SUB	%R8,%R10

(211) 0x231e4f MOV	0x78(%R14),%R8

(211) 0x231e53 VMOVSD	(%RCX,%RDX,8),%XMM4

(211) 0x231e58 MOV	0xa0(%R14),%RCX

(211) 0x231e5f MOV	0xf8(%R14),%RDX

(211) 0x231e66 ADD	%R11,%R8

(211) 0x231e69 VMOVSD	(%RCX),%XMM5

(211) 0x231e6d MOV	0xa8(%R14),%RCX

(211) 0x231e74 VMOVSD	(%RDX),%XMM7

(211) 0x231e78 MOV	0x110(%R14),%RDX

(211) 0x231e7f VMOVSD	(%RCX),%XMM6

(211) 0x231e83 MOV	0xb0(%R14),%RCX

(211) 0x231e8a VADDSD	%XMM7,%XMM7,%XMM7

(211) 0x231e8e VXORPD	%XMM0,%XMM5,%XMM9

(211) 0x231e92 LEA	(%RCX,%RBP,1),%RAX

(211) 0x231e96 ADD	0xe8(%R14),%RBP

(211) 0x231e9d MOV	%RAX,0x60(%RSP)

(211) 0x231ea2 MOV	0x18(%RSP),%RAX

(211) 0x231ea7 IMUL	%RAX,%R12

(211) 0x231eab IMUL	%RAX,%RSI

(211) 0x231eaf SUB	%R9,%R12

(211) 0x231eb2 SUB	%RDI,%RSI

(211) 0x231eb5 LEA	(%RDX,%R11,1),%R9

(211) 0x231eb9 MOV	0x30(%RSP),%RDI

(211) 0x231ebe ADD	%R12,%R13

(211) 0x231ec1 ADD	%RCX,%R12

(211) 0x231ec4 MOV	0x90(%R14),%RCX

(211) 0x231ecb ADD	%RDX,%RSI

(211) 0x231ece ADD	%R11,%RCX

(211) 0x231ed1 ADD	0x100(%R14),%R11

(211) 0x231ed8 JMP	232017

0x231edd NOPL	(%RAX)

  (212) 0x231ee0 MOV	0x130(%R14),%RAX

  (212) 0x231ee7 VMOVSD	(%RAX),%XMM11

  (212) 0x231eeb VMOVSD	0x8(%RCX,%RDI,8),%XMM19

  (212) 0x231ef3 VMOVSD	0x8(%R8,%RDI,8),%XMM18

  (212) 0x231efb VMOVSD	0x8(%R10,%RDI,8),%XMM17

  (212) 0x231f03 VCMPSD	$0x3,%XMM5,%XMM5,%K1

  (212) 0x231f0a VANDPD	%XMM2,%XMM16,%XMM16

  (212) 0x231f10 VANDPD	%XMM2,%XMM15,%XMM15

  (212) 0x231f14 VANDPD	%XMM2,%XMM14,%XMM14

  (212) 0x231f18 VANDPD	%XMM2,%XMM13,%XMM13

  (212) 0x231f1c VCMPSD	$0x3,%XMM14,%XMM14,%K2

  (212) 0x231f23 VADDSD	%XMM19,%XMM19,%XMM19

  (212) 0x231f29 VDIVSD	0x8(%R15,%RDI,8),%XMM19,%XMM19

  (212) 0x231f31 VMULSD	%XMM18,%XMM18,%XMM18

  (212) 0x231f37 INC	%RDI

  (212) 0x231f3a VADDSD	%XMM19,%XMM18,%XMM18

  (212) 0x231f40 VSQRTSD	%XMM18,%XMM18,%XMM18

  (212) 0x231f46 VMAXSD	%XMM5,%XMM18,%XMM19

  (212) 0x231f4c VMOVSD	%XMM18,%XMM19,%XMM19{%K1}

  (212) 0x231f52 VCMPSD	$0x3,%XMM4,%XMM4,%K1

  (212) 0x231f59 VMINSD	%XMM4,%XMM17,%XMM18

  (212) 0x231f5f VMOVSD	%XMM17,%XMM18,%XMM18{%K1}

  (212) 0x231f65 VCMPSD	$0x3,%XMM16,%XMM16,%K1

  (212) 0x231f6c VMULSD	%XMM6,%XMM18,%XMM17

  (212) 0x231f72 VMULSD	%XMM7,%XMM12,%XMM18

  (212) 0x231f78 VMULSD	%XMM8,%XMM12,%XMM12

  (212) 0x231f7d VDIVSD	%XMM19,%XMM17,%XMM17

  (212) 0x231f83 VMAXSD	%XMM16,%XMM15,%XMM19

  (212) 0x231f89 VMAXSD	%XMM14,%XMM13,%XMM16

  (212) 0x231f8f VMOVSD	%XMM15,%XMM19,%XMM19{%K1}

  (212) 0x231f95 KMOVD	%EDX,%K1

  (212) 0x231f99 VMOVSD	%XMM13,%XMM16,%XMM16{%K2}

  (212) 0x231f9f VMAXSD	%XMM10,%XMM19,%XMM15

  (212) 0x231fa5 VMAXSD	%XMM10,%XMM16,%XMM10

  (212) 0x231fab VMOVSD	%XMM19,%XMM15,%XMM15{%K1}

  (212) 0x231fb1 VMOVSD	%XMM16,%XMM10,%XMM10{%K1}

  (212) 0x231fb7 VDIVSD	%XMM15,%XMM18,%XMM15

  (212) 0x231fbd VDIVSD	%XMM10,%XMM12,%XMM10

  (212) 0x231fc2 VCMPSD	$0x3,%XMM17,%XMM17,%K1

  (212) 0x231fc9 VMINSD	%XMM17,%XMM20,%XMM12

  (212) 0x231fcf VMOVSD	%XMM20,%XMM12,%XMM12{%K1}

  (212) 0x231fd5 VCMPSD	$0x3,%XMM15,%XMM15,%K1

  (212) 0x231fdc VMINSD	%XMM15,%XMM12,%XMM13

  (212) 0x231fe1 VMOVSD	%XMM12,%XMM13,%XMM13{%K1}

  (212) 0x231fe7 VCMPSD	$0x3,%XMM10,%XMM10,%K1

  (212) 0x231fee VMINSD	%XMM10,%XMM13,%XMM12

  (212) 0x231ff3 VMOVSD	%XMM13,%XMM12,%XMM12{%K1}

  (212) 0x231ff9 VCMPSD	$0x3,%XMM11,%XMM11,%K1

  (212) 0x232000 VMINSD	%XMM11,%XMM12,%XMM20

  (212) 0x232006 VMOVSD	%XMM12,%XMM20,%XMM20{%K1}

  (212) 0x23200c CMP	%RDI,0x20(%RSP)

  (212) 0x232011 JE	231d70

  (212) 0x232017 MOV	0x60(%RSP),%RAX

  (212) 0x23201c VMOVUPD	0x8(%R12,%RDI,8),%XMM10

  (212) 0x232023 VMOVSD	0x10(%R13,%RDI,8),%XMM14

  (212) 0x23202a VMOVSD	0x10(%RBX,%RDI,8),%XMM13

  (212) 0x232030 VMOVSD	0x8(%R11,%RDI,8),%XMM12

  (212) 0x232037 VADDSD	0x8(%R13,%RDI,8),%XMM14,%XMM14

  (212) 0x23203e VADDSD	0x8(%RBX,%RDI,8),%XMM13,%XMM13

  (212) 0x232044 VMULSD	0x8(%RSI,%RDI,8),%XMM14,%XMM14

  (212) 0x23204a VMULSD	0x8(%R9,%RDI,8),%XMM13,%XMM13

  (212) 0x232051 VADDPD	0x8(%RAX,%RDI,8),%XMM10,%XMM10

  (212) 0x232057 VMULPD	0x8(%RBP,%RDI,8),%XMM10,%XMM15

  (212) 0x23205d VADDSD	%XMM12,%XMM12,%XMM17

  (212) 0x232063 VSHUFPD	$0x1,%XMM15,%XMM15,%XMM16

  (212) 0x23206a VADDSD	%XMM1,%XMM16,%XMM10

  (212) 0x232070 VSUBSD	%XMM15,%XMM10,%XMM11

  (212) 0x232075 VMULSD	%XMM5,%XMM12,%XMM10

  (212) 0x232079 VADDSD	%XMM14,%XMM11,%XMM11

  (212) 0x23207e VUCOMISD	%XMM10,%XMM10

  (212) 0x232083 VSUBSD	%XMM13,%XMM11,%XMM11

  (212) 0x232088 SETP	%DL

  (212) 0x23208b VDIVSD	%XMM17,%XMM11,%XMM11

  (212) 0x232091 VUCOMISD	%XMM11,%XMM9

  (212) 0x232096 JBE	231ee0

  (212) 0x23209c VDIVSD	%XMM11,%XMM3,%XMM11

  (212) 0x2320a1 MOV	0x128(%R14),%RAX

  (212) 0x2320a8 VMULSD	(%RAX),%XMM11,%XMM11

  (212) 0x2320ac JMP	231eeb

0x2320b1 INT	$0x3

0x2320b2 INT	$0x3

0x2320b3 INT	$0x3

0x2320b4 INT	$0x3

0x2320b5 INT	$0x3

0x2320b6 INT	$0x3

0x2320b7 INT	$0x3

0x2320b8 INT	$0x3

0x2320b9 INT	$0x3

0x2320ba INT	$0x3

0x2320bb INT	$0x3

0x2320bc INT	$0x3

0x2320bd INT	$0x3

0x2320be INT	$0x3

0x2320bf INT	$0x3

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	calc_dt_kernel.f90:89-135
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-99,107-135.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.13 to 3.25 cycles (3.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 11.13 to 0.86 cycles (12.95x speedup).

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

9% of SSE/AVX loads are used in vector version.
9% of SSE/AVX stores are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 136 bytes (17 double precision FP elements). The binary function is storing 76 bytes (9 double precision FP elements).

General properties

nb instructions	100
nb uops	89
loop length	356
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.13 cycles
front end	11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	9.50	9.50	9.50	9.50	1.25	1.25	1.25	1.25	1.00	1.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	9.50	9.50	9.50	9.50	1.25	1.25	1.25	1.25	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.13
Dispatch	9.50
Overall L1	11.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	23%
load	14%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	15%
load	14%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	11%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 11.13 cycles. At this rate:

4% of peak load performance is reached (12.22 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.13 to 9.50 cycles (1.17x speedup).

ASM code

In the binary file, the address of the function is: 231c20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RAX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVL $0x1,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EBX,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x18(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x10(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xc(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 283090 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD -0x2fdc2(%RIP),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD 0x8(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 231ca4 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x84>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0x4(%RSP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP %EAX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 231d07 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0xe7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xc(%RSP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
VMOVAPD %XMM20,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 2830a0 <@plt_start@+0xb0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 283290 <@plt_start@+0x2a0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 283290 <@plt_start@+0x2a0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV (%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD 0x20(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VCMPSD $0x3,%XMM2,%XMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,%XMM1,%XMM1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVSD %XMM1,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 2832a0 <@plt_start@+0x2b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 2832a0 <@plt_start@+0x2b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 2830b0 <@plt_start@+0xc0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x18(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x2fe49(%RIP),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2fe01(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2fe39(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x2fe89(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (,%RAX,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(,%RAX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD (%RCX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVSXD (%RDX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DEC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 231da2 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x182>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	calc_dt_kernel.f90:89-135
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.13 to 3.25 cycles (3.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

9% of SSE/AVX loads are used in vector version.
9% of SSE/AVX stores are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

unknown: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:92
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:132
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:133

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

General properties

nb instructions	100
nb uops	89
loop length	356
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.13 cycles
front end	11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	9.50	9.50	9.50	9.50	1.25	1.25	1.25	1.25	1.00	1.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	9.50	9.50	9.50	9.50	1.25	1.25	1.25	1.25	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.13
Dispatch	9.50
Overall L1	11.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	23%
load	14%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	15%
load	14%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	11%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 11.13 cycles. At this rate:

4% of peak load performance is reached (12.22 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 231c20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RAX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVL $0x1,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EAX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EBX,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x18(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x10(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xc(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 283090 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD -0x2fdc2(%RIP),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSXD 0x8(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 231ca4 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x84>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0x4(%RSP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP %EAX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 231d07 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0xe7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xc(%RSP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
VMOVAPD %XMM20,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 2830a0 <@plt_start@+0xb0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 283290 <@plt_start@+0x2a0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 283290 <@plt_start@+0x2a0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV (%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD 0x20(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VCMPSD $0x3,%XMM2,%XMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMINSD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,%XMM1,%XMM1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVSD %XMM1,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 2832a0 <@plt_start@+0x2b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 2832a0 <@plt_start@+0x2b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 2830b0 <@plt_start@+0xc0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x18(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD -0x2fe49(%RIP),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2fe01(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2fe39(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x2fe89(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (,%RAX,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(,%RAX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD (%RCX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVSXD (%RDX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DEC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 231da2 <__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1_+0x182>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

Name	Coverage (%)	Time (s)
▼__nv_calc_dt_kernel_module_calc_dt_kernel__PARALLEL_F2L89_1–	3.43	1.28
▼Loop 211 - calc_dt_kernel.f90:94-132 - exec–	0.00	0.01
○Loop 212 - calc_dt_kernel.f90:107-131 - exec	3.43	1.28

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Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code