OV - exec - Function __nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57

	Function: __nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57_1	Module: exec	Source: accelerate_kernel.f90:57-81 [...]	Coverage (incl. loops): 5.30% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 57 - 81

--------------------------------------------------------------------------------

57:     !$OMP PARALLEL

58:

59:     !$OMP DO PRIVATE(j,k,stepbymass_s)

60:     DO k=y_min,y_max+1

61:     !$OMP SIMD

62:       DO j=x_min,x_max+1

63:         stepbymass_s=halfdt/((density0(j-1,k-1)*volume(j-1,k-1)  &

[...]

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

76:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

77:       ENDDO

78:     ENDDO

79:   !$OMP END DO

80:

81:   !$OMP END PARALLEL

0x224700 PUSH	%RBP

0x224701 PUSH	%R15

0x224703 PUSH	%R14

0x224705 PUSH	%R13

0x224707 PUSH	%R12

0x224709 PUSH	%RBX

0x22470a SUB	$0x158,%RSP

0x224711 MOV	0x8(%RDX),%RCX

0x224715 MOV	(%RDX),%RAX

0x224718 MOVL	$0,0xec(%RSP)

0x224723 MOV	(%RDI),%ESI

0x224725 MOV	%RDX,%R13

0x224728 MOV	(%RCX),%EBX

0x22472a MOV	(%RAX),%EAX

0x22472c MOVL	$0x1,0xe8(%RSP)

0x224737 INC	%EBX

0x224739 MOV	%EAX,0x1c(%RSP)

0x22473d MOV	%EBX,0x18(%RSP)

0x224741 SUB	$0x8,%RSP

0x224745 MOV	$0x22,%EDX

0x22474a LEA	0xf0(%RSP),%RAX

0x224752 LEA	0xf4(%RSP),%RCX

0x22475a LEA	0x24(%RSP),%R8

0x22475f LEA	0x20(%RSP),%R9

0x224764 XOR	%EDI,%EDI

0x224766 MOV	%ESI,0xec(%RSP)

0x22476d PUSH	$0x1

0x22476f PUSH	$0x1

0x224771 PUSH	%RAX

0x224772 CALL	283090 <@plt_start@+0xa0>

0x224777 ADD	$0x20,%RSP

0x22477b MOVSXD	0x1c(%RSP),%RDX

0x224780 CMP	%EBX,%EDX

0x224782 JG	2251bc

0x224788 MOVSXD	0x18(%RSP),%RAX

0x22478d MOV	%RAX,0x150(%RSP)

0x224795 CMP	%EDX,%EAX

0x224797 JL	2251bc

0x22479d MOV	0x18(%R13),%RCX

0x2247a1 MOV	0x10(%R13),%RAX

0x2247a5 MOV	%RDX,0x8(%RSP)

0x2247aa MOVSXD	(%RCX),%RCX

0x2247ad MOVSXD	(%RAX),%RDX

0x2247b0 MOV	%ECX,%EAX

0x2247b2 SUB	%EDX,%EAX

0x2247b4 MOV	%RDX,0x120(%RSP)

0x2247bc MOV	0x8(%RSP),%RDX

0x2247c1 MOV	%RCX,0xd8(%RSP)

0x2247c9 ADD	$0x2,%EAX

0x2247cc TEST	%EAX,%EAX

0x2247ce JLE	2251bc

0x2247d4 MOV	0x38(%R13),%RAX

0x2247d8 MOV	0x70(%R13),%RCX

0x2247dc MOV	0x120(%RSP),%RBX

0x2247e4 MOV	0x20(%R13),%R14

0x2247e8 MOV	0x68(%R13),%RBP

0x2247ec MOV	0xc8(%R13),%R10

0x2247f3 MOV	0xf0(%R13),%R11

0x2247fa VBROADCASTSD	-0x228cb(%RIP),%YMM1

0x224803 VBROADCASTSD	-0x228d5(%RIP),%ZMM3

0x22480d VMOVSD	-0x228dd(%RIP),%XMM2

0x224815 MOV	(%RAX),%RDI

0x224818 MOV	0x60(%R13),%RAX

0x22481c VBROADCASTSD	(%RCX),%ZMM0

0x224822 MOV	0x88(%R13),%RCX

0x224829 MOV	(%RCX),%R9

0x22482c MOV	(%RAX),%RAX

0x22482f LEA	-0x1(%RDX),%RCX

0x224833 MOV	%RDI,%R15

0x224836 IMUL	%RCX,%R15

0x22483a LEA	(%R15,%RBX,1),%RDX

0x22483e SAL	$0x3,%R15

0x224842 SUB	%RAX,%RDX

0x224845 LEA	(,%R9,8),%R8

0x22484d MOV	%R9,0x20(%RSP)

0x224852 IMUL	%RCX,%R9

0x224856 LEA	(%R14,%RDX,8),%RCX

0x22485a LEA	(%R11,%RDX,8),%RSI

0x22485e LEA	(%R10,%RDX,8),%R12

0x224862 MOV	%R8,0x148(%RSP)

0x22486a MOV	0xe0(%R13),%R8

0x224871 MOV	%RCX,0xa0(%RSP)

0x224879 LEA	(%RBP,%RDX,8),%RCX

0x22487e MOV	%RSI,0xd0(%RSP)

0x224886 MOV	%R12,0xb0(%RSP)

0x22488e MOV	%RCX,0x80(%RSP)

0x224896 LEA	(,%RDI,8),%RCX

0x22489e IMUL	0x8(%RSP),%RDI

0x2248a4 MOV	%RCX,0x140(%RSP)

0x2248ac LEA	(%RDI,%RBX,1),%RCX

0x2248b0 SAL	$0x3,%RDI

0x2248b4 SUB	%RAX,%RCX

0x2248b7 SAL	$0x3,%RAX

0x2248bb SUB	%RAX,%R15

0x2248be SUB	%RAX,%RDI

0x2248c1 LEA	(%R14,%RCX,8),%RAX

0x2248c5 LEA	(%R11,%RCX,8),%RDX

0x2248c9 LEA	(%R10,%RCX,8),%R12

0x2248cd LEA	(%R10,%R15,1),%RSI

0x2248d1 ADD	%RDI,%R10

0x2248d4 MOV	%RAX,0x68(%RSP)

0x2248d9 LEA	(%RBP,%RCX,8),%RAX

0x2248de MOV	%RDX,0x78(%RSP)

0x2248e3 LEA	(%R8,%RCX,8),%RDX

0x2248e7 MOV	%R10,0x30(%RSP)

0x2248ec MOV	0x20(%RSP),%R10

0x2248f1 MOV	%R12,0x98(%RSP)

0x2248f9 LEA	(%RBP,%R15,1),%R12

0x2248fe ADD	%RDI,%R8

0x224901 ADD	%RDI,%RBP

0x224904 IMUL	0x8(%RSP),%R10

0x22490a MOV	%R8,0x38(%RSP)

0x22490f MOV	%RAX,0x60(%RSP)

0x224914 MOV	0xa8(%R13),%RAX

0x22491b MOV	%RDX,0x70(%RSP)

0x224920 LEA	(%R11,%R15,1),%RDX

0x224924 ADD	%RDI,%R11

0x224927 ADD	%R14,%R15

0x22492a ADD	%R14,%RDI

0x22492d MOV	0xd8(%R13),%R14

0x224934 MOV	%RDX,0x48(%RSP)

0x224939 MOV	%R11,0x28(%RSP)

0x22493e MOV	0xd0(%R13),%R11

0x224945 MOV	(%RAX),%RCX

0x224948 LEA	(%R9,%RBX,1),%RAX

0x22494c SAL	$0x3,%R9

0x224950 LEA	(%R10,%RBX,1),%RDX

0x224954 SAL	$0x3,%R10

0x224958 SUB	%RCX,%RAX

0x22495b SUB	%RCX,%RDX

0x22495e SAL	$0x3,%RCX

0x224962 MOV	%RAX,0x58(%RSP)

0x224967 MOV	0x78(%R13),%RAX

0x22496b SUB	%RCX,%R10

0x22496e LEA	(%R14,%RDX,8),%R8

0x224972 SUB	%RCX,%R9

0x224975 MOV	0xb8(%R13),%RCX

0x22497c ADD	%R10,%R14

0x22497f MOV	%R14,0x40(%RSP)

0x224984 MOV	%R8,0xc8(%RSP)

0x22498c LEA	(%R11,%RDX,8),%R8

0x224990 ADD	%R10,%R11

0x224993 MOV	%R8,0xc0(%RSP)

0x22499b MOV	%RAX,0x50(%RSP)

0x2249a0 MOV	0xb0(%R13),%RAX

0x2249a7 LEA	(%RCX,%R10,1),%R13

0x2249ab ADD	%RCX,%R9

0x2249ae MOV	0x50(%RSP),%R14

0x2249b3 LEA	(%RAX,%RDX,8),%R8

0x2249b7 ADD	%R10,%RAX

0x2249ba ADD	%R14,%R10

0x2249bd MOV	%R8,0xb8(%RSP)

0x2249c5 LEA	(%R14,%RDX,8),%R8

0x2249c9 MOV	0xd8(%RSP),%R14

0x2249d1 LEA	(%RCX,%RDX,8),%RDX

0x2249d5 MOV	%R8,0xa8(%RSP)

0x2249dd MOV	0x58(%RSP),%R8

0x2249e2 MOV	%RDX,0x90(%RSP)

0x2249ea MOV	0x8(%RSP),%RDX

0x2249ef INC	%R14

0x2249f2 MOV	%R14,0xd8(%RSP)

0x2249fa LEA	(%RCX,%R8,8),%R8

0x2249fe MOV	%R8,0x88(%RSP)

0x224a06 MOV	%R14,%R8

0x224a09 SUB	%RBX,%R8

0x224a0c INC	%R8

0x224a0f MOV	%R8,%R14

0x224a12 AND	$-0x8,%R14

0x224a16 MOV	%R8,%RCX

0x224a19 MOV	%R8,0x10(%RSP)

0x224a1e AND	$-0x4,%R8

0x224a22 LEA	(%R14,%RBX,1),%RCX

0x224a26 MOV	%R8,0x138(%RSP)

0x224a2e ADD	%RBX,%R8

0x224a31 MOV	%R14,0xf0(%RSP)

0x224a39 MOV	%RCX,0x128(%RSP)

0x224a41 MOV	%R8,0x130(%RSP)

0x224a49 JMP	224b39

0x224a4e XCHG	%AX,%AX

(50) 0x224a50 MOV	0x140(%RSP),%RDX

(50) 0x224a58 MOV	0x148(%RSP),%RCX

(50) 0x224a60 ADD	%RDX,%R11

(50) 0x224a63 ADD	%RCX,%RAX

(50) 0x224a66 ADD	%RDX,%R12

(50) 0x224a69 ADD	%RDX,%R14

(50) 0x224a6c ADD	%RDX,%R8

(50) 0x224a6f ADD	%RDX,0xd0(%RSP)

(50) 0x224a77 ADD	%RDX,0xb0(%RSP)

(50) 0x224a7f ADD	%RDX,0xa0(%RSP)

(50) 0x224a87 ADD	%RDX,0x80(%RSP)

(50) 0x224a8f ADD	%RDX,0x78(%RSP)

(50) 0x224a94 ADD	%RDX,0x70(%RSP)

(50) 0x224a99 ADD	%RDX,0x98(%RSP)

(50) 0x224aa1 ADD	%RDX,0x68(%RSP)

(50) 0x224aa6 ADD	%RDX,0x60(%RSP)

(50) 0x224aab ADD	%RDX,%RSI

(50) 0x224aae ADD	%RDX,%RBX

(50) 0x224ab1 ADD	%RDX,%R15

(50) 0x224ab4 ADD	%RDX,%RBP

(50) 0x224ab7 ADD	%RDX,%RDI

(50) 0x224aba MOV	0x8(%RSP),%RDX

(50) 0x224abf ADD	%RCX,0xc0(%RSP)

(50) 0x224ac7 ADD	%RCX,0xc8(%RSP)

(50) 0x224acf ADD	%RCX,0xa8(%RSP)

(50) 0x224ad7 ADD	%RCX,0x90(%RSP)

(50) 0x224adf ADD	%RCX,0xb8(%RSP)

(50) 0x224ae7 ADD	%RCX,0x88(%RSP)

(50) 0x224aef ADD	%RCX,%R13

(50) 0x224af2 ADD	%RCX,%R10

(50) 0x224af5 ADD	%RCX,%R9

(50) 0x224af8 MOV	%R11,0x30(%RSP)

(50) 0x224afd MOV	0x50(%RSP),%R11

(50) 0x224b02 MOV	%RAX,0x40(%RSP)

(50) 0x224b07 MOV	0x58(%RSP),%RAX

(50) 0x224b0c MOV	%R12,0x48(%RSP)

(50) 0x224b11 MOV	%R14,0x28(%RSP)

(50) 0x224b16 MOV	%R8,0x38(%RSP)

(50) 0x224b1b MOV	%RBX,%R12

(50) 0x224b1e ADD	%RCX,%R11

(50) 0x224b21 ADD	%RCX,%RAX

(50) 0x224b24 MOV	%R11,%R11

(50) 0x224b27 CMP	0x150(%RSP),%RDX

(50) 0x224b2f LEA	0x1(%RDX),%RDX

(50) 0x224b33 JE	2251bc

(50) 0x224b39 MOV	%R11,0x50(%RSP)

(50) 0x224b3e MOV	%RAX,0x58(%RSP)

(50) 0x224b43 MOV	%RDX,0x8(%RSP)

(50) 0x224b48 MOV	%R12,%RBX

(50) 0x224b4b MOV	0x120(%RSP),%RDX

(50) 0x224b53 CMPQ	$0x4,0x10(%RSP)

(50) 0x224b59 MOV	0x48(%RSP),%R12

(50) 0x224b5e MOV	0x40(%RSP),%RAX

(50) 0x224b63 MOV	0x38(%RSP),%R8

(50) 0x224b68 MOV	0x30(%RSP),%R11

(50) 0x224b6d MOV	0x28(%RSP),%R14

(50) 0x224b72 JB	225060

(50) 0x224b78 CMPQ	$0x8,0x10(%RSP)

(50) 0x224b7e MOV	%R13,0xf8(%RSP)

(50) 0x224b86 MOV	%R10,0x20(%RSP)

(50) 0x224b8b MOV	%RBP,0x100(%RSP)

(50) 0x224b93 MOV	%RBX,0x108(%RSP)

(50) 0x224b9b MOV	%RSI,0x110(%RSP)

(50) 0x224ba3 MOV	%R9,0x118(%RSP)

(50) 0x224bab JAE	224dd0

(50) 0x224bb1 XOR	%ECX,%ECX

(50) 0x224bb3 MOV	0x60(%RSP),%R9

(50) 0x224bb8 MOV	0x68(%RSP),%RSI

(50) 0x224bbd MOV	0x80(%RSP),%R12

(50) 0x224bc5 MOV	0x78(%RSP),%RAX

(50) 0x224bca MOV	0x70(%RSP),%RBX

(50) 0x224bcf MOV	0xa0(%RSP),%RDX

(50) 0x224bd7 MOV	0x98(%RSP),%R13

(50) 0x224bdf MOV	0xa8(%RSP),%R14

(50) 0x224be7 MOV	0x90(%RSP),%RBP

(50) 0x224bef MOV	0x88(%RSP),%R8

(50) 0x224bf7 MOV	0x138(%RSP),%R10

(50) 0x224bff NOP

  (52) 0x224c00 VMOVUPD	-0x8(%R9,%RCX,8),%YMM4

  (52) 0x224c07 VMOVUPD	(%R9,%RCX,8),%YMM5

  (52) 0x224c0d VMOVUPD	(%R12,%RCX,8),%YMM6

  (52) 0x224c13 MOV	0xb8(%RSP),%R11

  (52) 0x224c1b VMOVUPD	-0x8(%R13,%RCX,8),%YMM10

  (52) 0x224c22 VMOVUPD	(%R13,%RCX,8),%YMM11

  (52) 0x224c29 VMOVUPD	(%R8,%RCX,8),%YMM9

  (52) 0x224c2f VMOVUPD	(%RBP,%RCX,8),%YMM13

  (52) 0x224c35 VMOVUPD	(%RBX,%RCX,8),%YMM18

  (52) 0x224c3c VMOVUPD	-0x8(%RAX,%RCX,8),%YMM16

  (52) 0x224c47 VMOVUPD	(%RAX,%RCX,8),%YMM14

  (52) 0x224c4c VMULPD	-0x8(%RSI,%RCX,8),%YMM4,%YMM4

  (52) 0x224c52 VMULPD	(%RSI,%RCX,8),%YMM5,%YMM5

  (52) 0x224c57 VMULPD	(%RDX,%RCX,8),%YMM6,%YMM6

  (52) 0x224c5c VSUBPD	%YMM10,%YMM11,%YMM12

  (52) 0x224c61 VSUBPD	%YMM16,%YMM14,%YMM15

  (52) 0x224c67 VADDPD	%YMM5,%YMM4,%YMM4

  (52) 0x224c6b VMOVUPD	-0x8(%R12,%RCX,8),%YMM5

  (52) 0x224c72 VMULPD	%YMM13,%YMM12,%YMM12

  (52) 0x224c77 VMULPD	%YMM15,%YMM13,%YMM13

  (52) 0x224c7c VMULPD	-0x8(%RDX,%RCX,8),%YMM5,%YMM5

  (52) 0x224c82 VADDPD	%YMM5,%YMM6,%YMM5

  (52) 0x224c86 VADDPD	%YMM5,%YMM4,%YMM4

  (52) 0x224c8a VMOVUPD	(%R11,%RCX,8),%YMM5

  (52) 0x224c90 MOV	0xb0(%RSP),%R11

  (52) 0x224c98 VMULPD	%YMM1,%YMM4,%YMM4

  (52) 0x224c9c VMOVUPD	-0x8(%R11,%RCX,8),%YMM6

  (52) 0x224ca3 VMOVUPD	(%R11,%RCX,8),%YMM7

  (52) 0x224ca9 MOV	0xc8(%RSP),%R11

  (52) 0x224cb1 VDIVPD	%YMM4,%YMM0,%YMM4

  (52) 0x224cb5 VSUBPD	%YMM6,%YMM7,%YMM8

  (52) 0x224cb9 VSUBPD	%YMM6,%YMM10,%YMM6

  (52) 0x224cbd VMOVUPD	-0x8(%RBX,%RCX,8),%YMM10

  (52) 0x224cc3 VSUBPD	%YMM7,%YMM11,%YMM7

  (52) 0x224cc7 VMULPD	%YMM9,%YMM8,%YMM8

  (52) 0x224ccc VMULPD	%YMM18,%YMM7,%YMM7

  (52) 0x224cd2 VADDPD	%YMM12,%YMM8,%YMM8

  (52) 0x224cd7 VMULPD	%YMM6,%YMM10,%YMM6

  (52) 0x224cdb VMULPD	%YMM4,%YMM8,%YMM8

  (52) 0x224cdf VADDPD	%YMM7,%YMM6,%YMM6

  (52) 0x224ce3 VSUBPD	%YMM8,%YMM5,%YMM5

  (52) 0x224ce8 VMOVUPD	(%R11,%RCX,8),%YMM8

  (52) 0x224cee MOV	0xd0(%RSP),%R11

  (52) 0x224cf6 VMULPD	%YMM6,%YMM4,%YMM6

  (52) 0x224cfa VMOVUPD	-0x8(%R11,%RCX,8),%YMM7

  (52) 0x224d01 VMOVUPD	(%R11,%RCX,8),%YMM17

  (52) 0x224d08 MOV	0xc0(%RSP),%R11

  (52) 0x224d10 VSUBPD	%YMM6,%YMM8,%YMM6

  (52) 0x224d14 VSUBPD	%YMM7,%YMM17,%YMM11

  (52) 0x224d1a VMULPD	%YMM11,%YMM9,%YMM9

  (52) 0x224d1f VADDPD	%YMM13,%YMM9,%YMM9

  (52) 0x224d24 VMULPD	%YMM4,%YMM9,%YMM9

  (52) 0x224d28 VSUBPD	%YMM9,%YMM5,%YMM5

  (52) 0x224d2d VMOVUPD	%YMM5,(%R14,%RCX,8)

  (52) 0x224d33 VSUBPD	%YMM7,%YMM16,%YMM5

  (52) 0x224d39 VSUBPD	%YMM17,%YMM14,%YMM7

  (52) 0x224d3f VMULPD	%YMM5,%YMM10,%YMM5

  (52) 0x224d43 VMULPD	%YMM7,%YMM18,%YMM7

  (52) 0x224d49 VADDPD	%YMM5,%YMM7,%YMM5

  (52) 0x224d4d VMULPD	%YMM5,%YMM4,%YMM4

  (52) 0x224d51 VSUBPD	%YMM4,%YMM6,%YMM4

  (52) 0x224d55 VMOVUPD	%YMM4,(%R11,%RCX,8)

  (52) 0x224d5b ADD	$0x4,%RCX

  (52) 0x224d5f CMP	%RCX,%R10

  (52) 0x224d62 JNE	224c00

(50) 0x224d68 MOV	0x130(%RSP),%RDX

(50) 0x224d70 MOV	0x118(%RSP),%R9

(50) 0x224d78 MOV	0x48(%RSP),%R12

(50) 0x224d7d MOV	0x110(%RSP),%RSI

(50) 0x224d85 MOV	0x108(%RSP),%RBX

(50) 0x224d8d MOV	0x40(%RSP),%RAX

(50) 0x224d92 MOV	0x38(%RSP),%R8

(50) 0x224d97 MOV	0x100(%RSP),%RBP

(50) 0x224d9f MOV	0x30(%RSP),%R11

(50) 0x224da4 MOV	0x28(%RSP),%R14

(50) 0x224da9 MOV	0xf8(%RSP),%R13

(50) 0x224db1 CMP	%R10,0x10(%RSP)

(50) 0x224db6 MOV	0x20(%RSP),%R10

(50) 0x224dbb JE	224a50

(50) 0x224dc1 JMP	225060

0x224dc6 NOPW	%CS:(%RAX,%RAX,1)

(50) 0x224dd0 MOV	0x60(%RSP),%R9

(50) 0x224dd5 MOV	0x68(%RSP),%RSI

(50) 0x224dda MOV	0xb0(%RSP),%R12

(50) 0x224de2 MOV	0xa0(%RSP),%RDX

(50) 0x224dea MOV	0x98(%RSP),%RBX

(50) 0x224df2 MOV	0x90(%RSP),%R14

(50) 0x224dfa MOV	0x88(%RSP),%R13

(50) 0x224e02 MOV	0xf0(%RSP),%RBP

(50) 0x224e0a MOV	0x80(%RSP),%RAX

(50) 0x224e12 MOV	0x78(%RSP),%R8

(50) 0x224e17 MOV	0x70(%RSP),%R10

(50) 0x224e1c XOR	%ECX,%ECX

(50) 0x224e1e XCHG	%AX,%AX

  (51) 0x224e20 VMOVUPD	-0x8(%R9,%RCX,8),%ZMM4

  (51) 0x224e2b VMOVUPD	(%R9,%RCX,8),%ZMM5

  (51) 0x224e32 VMOVUPD	(%RAX,%RCX,8),%ZMM6

  (51) 0x224e39 VMOVUPD	-0x8(%RAX,%RCX,8),%ZMM8

  (51) 0x224e44 VMOVUPD	(%R12,%RCX,8),%ZMM7

  (51) 0x224e4b VMOVUPD	-0x8(%RBX,%RCX,8),%ZMM10

  (51) 0x224e56 VMOVUPD	(%RBX,%RCX,8),%ZMM11

  (51) 0x224e5d VMOVUPD	(%R13,%RCX,8),%ZMM9

  (51) 0x224e65 VMOVUPD	(%R14,%RCX,8),%ZMM13

  (51) 0x224e6c MOV	0xb8(%RSP),%R11

  (51) 0x224e74 VMOVUPD	-0x8(%R8,%RCX,8),%ZMM16

  (51) 0x224e7f VMULPD	-0x8(%RSI,%RCX,8),%ZMM4,%ZMM4

  (51) 0x224e8a VMULPD	(%RSI,%RCX,8),%ZMM5,%ZMM5

  (51) 0x224e91 VMULPD	(%RDX,%RCX,8),%ZMM6,%ZMM6

  (51) 0x224e98 VSUBPD	%ZMM10,%ZMM11,%ZMM12

  (51) 0x224e9e VADDPD	%ZMM5,%ZMM4,%ZMM4

  (51) 0x224ea4 VMULPD	-0x8(%RDX,%RCX,8),%ZMM8,%ZMM5

  (51) 0x224eaf VMULPD	%ZMM13,%ZMM12,%ZMM12

  (51) 0x224eb5 VADDPD	%ZMM5,%ZMM6,%ZMM5

  (51) 0x224ebb VMOVUPD	-0x8(%R12,%RCX,8),%ZMM6

  (51) 0x224ec6 VADDPD	%ZMM5,%ZMM4,%ZMM4

  (51) 0x224ecc VMOVUPD	(%R11,%RCX,8),%ZMM5

  (51) 0x224ed3 MOV	0xc8(%RSP),%R11

  (51) 0x224edb VMULPD	%ZMM3,%ZMM4,%ZMM4

  (51) 0x224ee1 VSUBPD	%ZMM6,%ZMM7,%ZMM8

  (51) 0x224ee7 VSUBPD	%ZMM6,%ZMM10,%ZMM6

  (51) 0x224eed VMOVUPD	-0x8(%R10,%RCX,8),%ZMM10

  (51) 0x224ef8 VSUBPD	%ZMM7,%ZMM11,%ZMM7

  (51) 0x224efe VMOVUPD	(%R11,%RCX,8),%ZMM14

  (51) 0x224f05 MOV	0xd0(%RSP),%R11

  (51) 0x224f0d VDIVPD	%ZMM4,%ZMM0,%ZMM4

  (51) 0x224f13 VMULPD	%ZMM9,%ZMM8,%ZMM8

  (51) 0x224f19 VMOVUPD	(%R11,%RCX,8),%ZMM17

  (51) 0x224f20 VADDPD	%ZMM12,%ZMM8,%ZMM8

  (51) 0x224f26 VMOVUPD	(%R10,%RCX,8),%ZMM12

  (51) 0x224f2d VMULPD	%ZMM10,%ZMM6,%ZMM6

  (51) 0x224f33 VMULPD	%ZMM12,%ZMM7,%ZMM7

  (51) 0x224f39 VMULPD	%ZMM8,%ZMM4,%ZMM8

  (51) 0x224f3f VADDPD	%ZMM7,%ZMM6,%ZMM6

  (51) 0x224f45 VMOVUPD	-0x8(%R11,%RCX,8),%ZMM7

  (51) 0x224f50 VSUBPD	%ZMM8,%ZMM5,%ZMM5

  (51) 0x224f56 MOV	0xa8(%RSP),%R11

  (51) 0x224f5e VMULPD	%ZMM6,%ZMM4,%ZMM6

  (51) 0x224f64 VSUBPD	%ZMM6,%ZMM14,%ZMM6

  (51) 0x224f6a VMOVUPD	(%R8,%RCX,8),%ZMM14

  (51) 0x224f71 VSUBPD	%ZMM7,%ZMM17,%ZMM11

  (51) 0x224f77 VSUBPD	%ZMM7,%ZMM16,%ZMM7

  (51) 0x224f7d VMULPD	%ZMM11,%ZMM9,%ZMM9

  (51) 0x224f83 VSUBPD	%ZMM16,%ZMM14,%ZMM15

  (51) 0x224f89 VSUBPD	%ZMM17,%ZMM14,%ZMM8

  (51) 0x224f8f VMULPD	%ZMM15,%ZMM13,%ZMM13

  (51) 0x224f95 VADDPD	%ZMM13,%ZMM9,%ZMM9

  (51) 0x224f9b VMULPD	%ZMM9,%ZMM4,%ZMM9

  (51) 0x224fa1 VSUBPD	%ZMM9,%ZMM5,%ZMM5

  (51) 0x224fa7 VMOVUPD	%ZMM5,(%R11,%RCX,8)

  (51) 0x224fae VMULPD	%ZMM7,%ZMM10,%ZMM5

  (51) 0x224fb4 VMULPD	%ZMM8,%ZMM12,%ZMM7

  (51) 0x224fba MOV	0xc0(%RSP),%R11

  (51) 0x224fc2 VADDPD	%ZMM5,%ZMM7,%ZMM5

  (51) 0x224fc8 VMULPD	%ZMM5,%ZMM4,%ZMM4

  (51) 0x224fce VSUBPD	%ZMM4,%ZMM6,%ZMM4

  (51) 0x224fd4 VMOVUPD	%ZMM4,(%R11,%RCX,8)

  (51) 0x224fdb ADD	$0x8,%RCX

  (51) 0x224fdf CMP	%RCX,%RBP

  (51) 0x224fe2 JNE	224e20

(50) 0x224fe8 MOV	0x118(%RSP),%R9

(50) 0x224ff0 MOV	0x48(%RSP),%R12

(50) 0x224ff5 MOV	0x110(%RSP),%RSI

(50) 0x224ffd MOV	0x108(%RSP),%RBX

(50) 0x225005 MOV	0x40(%RSP),%RAX

(50) 0x22500a MOV	0x38(%RSP),%R8

(50) 0x22500f MOV	0x20(%RSP),%R10

(50) 0x225014 MOV	0x30(%RSP),%R11

(50) 0x225019 MOV	0x28(%RSP),%R14

(50) 0x22501e MOV	0xf8(%RSP),%R13

(50) 0x225026 CMP	%RBP,0x10(%RSP)

(50) 0x22502b MOV	0x100(%RSP),%RBP

(50) 0x225033 JE	224a50

(50) 0x225039 MOV	0xf0(%RSP),%RCX

(50) 0x225041 MOV	0x128(%RSP),%RDX

(50) 0x225049 TESTB	$0x4,0x10(%RSP)

(50) 0x22504e JNE	224bb3

(50) 0x225054 NOPW	%CS:(%RAX,%RAX,1)

(50) 0x225060 DEC	%RDX

(50) 0x225063 NOPW	%CS:(%RAX,%RAX,1)

  (49) 0x225070 VMOVSD	(%RBP,%RDX,8),%XMM4

  (49) 0x225076 VMOVSD	0x8(%RBP,%RDX,8),%XMM5

  (49) 0x22507c VMOVSD	0x8(%RBX,%RDX,8),%XMM6

  (49) 0x225082 VMOVSD	0x8(%RSI,%RDX,8),%XMM7

  (49) 0x225088 VMOVSD	(%R11,%RDX,8),%XMM10

  (49) 0x22508e VMOVSD	0x8(%R11,%RDX,8),%XMM11

  (49) 0x225095 VMOVSD	0x8(%R9,%RDX,8),%XMM9

  (49) 0x22509c VMOVSD	0x8(%R13,%RDX,8),%XMM13

  (49) 0x2250a3 VMOVSD	0x8(%RAX,%RDX,8),%XMM14

  (49) 0x2250a9 VMOVSD	0x8(%R12,%RDX,8),%XMM17

  (49) 0x2250b1 VMOVSD	(%R14,%RDX,8),%XMM16

  (49) 0x2250b8 MOV	0x58(%RSP),%RCX

  (49) 0x2250bd VMULSD	(%RDI,%RDX,8),%XMM4,%XMM4

  (49) 0x2250c2 VMULSD	0x8(%RDI,%RDX,8),%XMM5,%XMM5

  (49) 0x2250c8 VMULSD	0x8(%R15,%RDX,8),%XMM6,%XMM6

  (49) 0x2250cf VSUBSD	%XMM10,%XMM11,%XMM12

  (49) 0x2250d4 VADDSD	%XMM5,%XMM4,%XMM4

  (49) 0x2250d8 VMOVSD	(%RBX,%RDX,8),%XMM5

  (49) 0x2250dd VMULSD	%XMM13,%XMM12,%XMM12

  (49) 0x2250e2 VMULSD	(%R15,%RDX,8),%XMM5,%XMM5

  (49) 0x2250e8 VADDSD	%XMM5,%XMM6,%XMM5

  (49) 0x2250ec VMOVSD	(%RSI,%RDX,8),%XMM6

  (49) 0x2250f1 VADDSD	%XMM5,%XMM4,%XMM4

  (49) 0x2250f5 VMOVSD	0x8(%RCX,%RDX,8),%XMM5

  (49) 0x2250fb MOV	0x50(%RSP),%RCX

  (49) 0x225100 VMULSD	%XMM2,%XMM4,%XMM4

  (49) 0x225104 VSUBSD	%XMM6,%XMM7,%XMM8

  (49) 0x225108 VSUBSD	%XMM6,%XMM10,%XMM6

  (49) 0x22510c VMOVSD	(%R8,%RDX,8),%XMM10

  (49) 0x225112 VSUBSD	%XMM7,%XMM11,%XMM7

  (49) 0x225116 VDIVSD	%XMM4,%XMM0,%XMM4

  (49) 0x22511a VMULSD	%XMM9,%XMM8,%XMM8

  (49) 0x22511f VADDSD	%XMM12,%XMM8,%XMM8

  (49) 0x225124 VMOVSD	0x8(%R8,%RDX,8),%XMM12

  (49) 0x22512b VMULSD	%XMM6,%XMM10,%XMM6

  (49) 0x22512f VMULSD	%XMM7,%XMM12,%XMM7

  (49) 0x225133 VMULSD	%XMM4,%XMM8,%XMM8

  (49) 0x225137 VADDSD	%XMM7,%XMM6,%XMM6

  (49) 0x22513b VMOVSD	(%R12,%RDX,8),%XMM7

  (49) 0x225141 VSUBSD	%XMM8,%XMM5,%XMM5

  (49) 0x225146 VMULSD	%XMM6,%XMM4,%XMM6

  (49) 0x22514a VSUBSD	%XMM6,%XMM14,%XMM6

  (49) 0x22514e VMOVSD	0x8(%R14,%RDX,8),%XMM14

  (49) 0x225155 VSUBSD	%XMM7,%XMM17,%XMM11

  (49) 0x22515b VMULSD	%XMM11,%XMM9,%XMM9

  (49) 0x225160 VSUBSD	%XMM16,%XMM14,%XMM15

  (49) 0x225166 VMULSD	%XMM15,%XMM13,%XMM13

  (49) 0x22516b VADDSD	%XMM13,%XMM9,%XMM9

  (49) 0x225170 VMULSD	%XMM4,%XMM9,%XMM9

  (49) 0x225174 VSUBSD	%XMM9,%XMM5,%XMM5

  (49) 0x225179 VMOVSD	%XMM5,0x8(%R10,%RDX,8)

  (49) 0x225180 VSUBSD	%XMM7,%XMM16,%XMM5

  (49) 0x225186 VSUBSD	%XMM17,%XMM14,%XMM7

  (49) 0x22518c VMULSD	%XMM5,%XMM10,%XMM5

  (49) 0x225190 VMULSD	%XMM7,%XMM12,%XMM7

  (49) 0x225194 VADDSD	%XMM5,%XMM7,%XMM5

  (49) 0x225198 VMULSD	%XMM5,%XMM4,%XMM4

  (49) 0x22519c VSUBSD	%XMM4,%XMM6,%XMM4

  (49) 0x2251a0 VMOVSD	%XMM4,0x8(%RCX,%RDX,8)

  (49) 0x2251a6 INC	%RDX

  (49) 0x2251a9 CMP	%RDX,0xd8(%RSP)

  (49) 0x2251b1 JNE	225070

(50) 0x2251b7 JMP	224a50

0x2251bc MOV	0xe4(%RSP),%EBX

0x2251c3 XOR	%EDI,%EDI

0x2251c5 MOV	%EBX,%ESI

0x2251c7 VZEROUPPER

0x2251ca CALL	2830a0 <@plt_start@+0xb0>

0x2251cf XOR	%EDI,%EDI

0x2251d1 MOV	%EBX,%ESI

0x2251d3 CALL	2830b0 <@plt_start@+0xc0>

0x2251d8 ADD	$0x158,%RSP

0x2251df POP	%RBX

0x2251e0 POP	%R12

0x2251e2 POP	%R13

0x2251e4 POP	%R14

0x2251e6 POP	%R15

0x2251e8 POP	%RBP

0x2251e9 RET

0x2251ea INT	$0x3

0x2251eb INT	$0x3

0x2251ec INT	$0x3

0x2251ed INT	$0x3

0x2251ee INT	$0x3

0x2251ef INT	$0x3

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	accelerate_kernel.f90:57-81
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:57-63,69-81.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.63 to 2.00 cycles (12.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 24.63 to 1.97 cycles (12.51x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:60
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:78
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:79

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 320 bytes. The binary function is storing 300 bytes.

General properties

nb instructions	202
nb uops	197
loop length	910
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	2
nb stack references	41

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.63 cycles
front end	24.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	14.83	14.83	14.83	14.83	14.83	14.83	21.75	21.75	21.75	21.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	14.83	14.83	14.83	14.83	14.83	14.83	21.75	21.75	21.75	21.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.63
Dispatch	21.75
Overall L1	24.63

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	11%
load	6%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.63 cycles. At this rate:

5% of peak load performance is reached (12.99 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.63 to 21.75 cycles (1.13x speedup).

ASM code

In the binary file, the address of the function is: 224700

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x158,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0,0xec(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0x1,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EBX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0xf0(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xf4(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x24(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x20(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,0xec(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 283090 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD 0x1c(%RSP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP %EBX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 2251bc <__nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57_1_+0xabc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0x18(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x150(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 2251bc <__nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57_1_+0xabc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%R13),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD (%RCX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVSXD (%RAX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2251bc <__nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57_1_+0xabc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x38(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%R13),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x120(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%R13),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x68(%R13),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc8(%R13),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xf0(%R13),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VBROADCASTSD -0x228cb(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x228d5(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD -0x228dd(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VBROADCASTSD (%RCX),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x88(%R13),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA -0x1(%RDX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R15,%RBX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%R9,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL %RCX,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R14,%RDX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RDX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%RDX,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,0x148(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xe0(%R13),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RBP,%RDX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (,%RDI,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL 0x8(%RSP),%RDI	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDI,%RBX,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RAX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R14,%RCX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RCX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%RCX,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%R15,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RBP,%RCX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R8,%RCX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R10,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RBP,%R15,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDI,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL 0x8(%RSP),%R10	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
MOV %R8,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa8(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R11,%R15,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R14,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R14,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xd8(%R13),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xd0(%R13),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R9,%RBX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R10,%RBX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RCX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R14,%RDX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xb8(%R13),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R10,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R11,%RDX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xb0(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RCX,%R10,1),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x50(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RDX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R14,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R14,%RDX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0xd8(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RCX,%RDX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%R8,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R14,%RBX,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 224b39 <__nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57_1_+0x439>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xe4(%RSP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2830a0 <@plt_start@+0xb0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 2830b0 <@plt_start@+0xc0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x158,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	accelerate_kernel.f90:57-81
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:60
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:78
- /home/eoseret/qaas_runs_ZEN5/174-049-0948/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:79

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 320 bytes. The binary function is storing 300 bytes.

General properties

nb instructions	202
nb uops	197
loop length	910
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	2
nb stack references	41

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.63 cycles
front end	24.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	14.83	14.83	14.83	14.83	14.83	14.83	21.75	21.75	21.75	21.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	14.83	14.83	14.83	14.83	14.83	14.83	21.75	21.75	21.75	21.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.63
Dispatch	21.75
Overall L1	24.63

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	11%
load	6%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.63 cycles. At this rate:

5% of peak load performance is reached (12.99 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 224700

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x158,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0,0xec(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0x1,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
INC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EBX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0xf0(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xf4(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x24(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x20(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,0xec(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 283090 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD 0x1c(%RSP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP %EBX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 2251bc <__nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57_1_+0xabc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0x18(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x150(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 2251bc <__nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57_1_+0xabc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%R13),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD (%RCX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVSXD (%RAX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2251bc <__nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57_1_+0xabc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x38(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%R13),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x120(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%R13),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x68(%R13),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc8(%R13),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xf0(%R13),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VBROADCASTSD -0x228cb(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x228d5(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD -0x228dd(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VBROADCASTSD (%RCX),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x88(%R13),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA -0x1(%RDX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R15,%RBX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%R9,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
IMUL %RCX,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R14,%RDX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RDX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%RDX,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,0x148(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xe0(%R13),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RBP,%RDX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (,%RDI,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL 0x8(%RSP),%RDI	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDI,%RBX,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RAX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R14,%RCX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RCX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%RCX,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%R15,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RBP,%RCX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R8,%RCX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R10,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RBP,%R15,1),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDI,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL 0x8(%RSP),%R10	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
MOV %R8,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa8(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R11,%R15,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R14,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R14,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xd8(%R13),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xd0(%R13),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R9,%RBX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R10,%RBX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RCX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R14,%RDX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xb8(%R13),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R10,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R11,%RDX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xb0(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RCX,%R10,1),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x50(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RDX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R14,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R14,%RDX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0xd8(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RCX,%RDX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%R8,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R14,%RBX,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 224b39 <__nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57_1_+0x439>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xe4(%RSP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2830a0 <@plt_start@+0xb0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 2830b0 <@plt_start@+0xc0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x158,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

Name	Coverage (%)	Time (s)
▼__nv_accelerate_kernel_module_accelerate_kernel__PARALLEL_F2L57_1–	5.30	1.98
▼Loop 50 - accelerate_kernel.f90:63-78 - exec–	0.00	0.01
○Loop 51 - accelerate_kernel.f90:63-75 - exec	5.29	1.97
○Loop 49 - accelerate_kernel.f90:63-77 - exec	0.00	0.00
○Loop 52 - accelerate_kernel.f90:63-75 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code