Loop Id: 256 | Module: exec | Source: advec_mom_kernel.f90:213-241 [...] | Coverage: 0.01% |
---|
Loop Id: 256 | Module: exec | Source: advec_mom_kernel.f90:213-241 [...] | Coverage: 0.01% |
---|
0x432d40 MOV -0x38(%RBP),%RCX |
0x432d44 INC %RCX |
0x432d47 INC %R11 |
0x432d4a MOV %RCX,%RAX |
0x432d4d MOV %RCX,-0x38(%RBP) |
0x432d51 CMP -0x68(%RBP),%RCX |
0x432d55 JE 43284f |
0x432d5b MOV -0x88(%RBP),%EAX |
0x432d61 CMP -0x40(%RBP),%EAX |
0x432d64 JL 432d40 |
0x432d66 MOV -0x38(%RBP),%RCX |
0x432d6a MOV -0x70(%RBP),%RAX |
0x432d6e LEA (%RCX,%RAX,1),%RBX |
0x432d72 LEA (%RCX,%RAX,1),%ESI |
0x432d75 DEC %ESI |
0x432d77 MOV -0x60(%RBP),%RAX |
0x432d7b LEA (%RAX,%RCX,1),%R13D |
0x432d7f MOV %RBX,%RAX |
0x432d82 SUB %R9,%RAX |
0x432d85 MOV %RAX,-0x58(%RBP) |
0x432d89 LEA 0x2(%RBX),%ECX |
0x432d8c LEA -0x1(%RBX),%EAX |
0x432d8f MOV %EAX,-0x48(%RBP) |
0x432d92 MOV -0x78(%RBP),%RDX |
0x432d96 JMP 432dde |
(257) 0x432da0 MOVAPD %XMM3,%XMM10 |
(257) 0x432da5 SUBSD %XMM7,%XMM10 |
(257) 0x432daa MULSD %XMM9,%XMM10 |
(257) 0x432daf ADDSD %XMM8,%XMM10 |
(257) 0x432db4 MULSD %XMM6,%XMM10 |
(257) 0x432db9 MOV 0x150(%RBP),%RAX |
(257) 0x432dc0 MOV (%RAX),%RAX |
(257) 0x432dc3 IMUL %R11,%RAX |
(257) 0x432dc7 ADD -0x30(%RBP),%RAX |
(257) 0x432dcb MOVSD %XMM10,0x10(%RAX,%RDX,8) |
(257) 0x432dd2 INC %RDX |
(257) 0x432dd5 CMP %RDX,%R12 |
(257) 0x432dd8 JE 432d40 |
(257) 0x432dde MOV 0x108(%RBP),%RAX |
(257) 0x432de5 MOV (%RAX),%RAX |
(257) 0x432de8 IMUL %R11,%RAX |
(257) 0x432dec ADD -0x50(%RBP),%RAX |
(257) 0x432df0 MOVSD 0x10(%RAX,%RDX,8),%XMM6 |
(257) 0x432df6 XORPD %XMM9,%XMM9 |
(257) 0x432dfb UCOMISD %XMM6,%XMM9 |
(257) 0x432e00 MOV %ESI,%R14D |
(257) 0x432e03 CMOVA %ECX,%R14D |
(257) 0x432e07 MOV %EBX,%EAX |
(257) 0x432e09 CMOVA %R13D,%EAX |
(257) 0x432e0d MOV %R13D,%R15D |
(257) 0x432e10 CMOVA %EBX,%R15D |
(257) 0x432e14 MOVAPD %XMM6,%XMM7 |
(257) 0x432e18 ANDPD %XMM0,%XMM7 |
(257) 0x432e1c CLTQ |
(257) 0x432e1e SUB %R9,%RAX |
(257) 0x432e21 MOV 0x130(%RBP),%R8 |
(257) 0x432e28 MOV (%R8),%R8 |
(257) 0x432e2b IMUL %RAX,%R8 |
(257) 0x432e2f ADD %RDI,%R8 |
(257) 0x432e32 DIVSD 0x10(%R8,%RDX,8),%XMM7 |
(257) 0x432e39 MOV 0x158(%RBP),%R8 |
(257) 0x432e40 MOV (%R8),%R8 |
(257) 0x432e43 IMUL %R8,%RAX |
(257) 0x432e47 MOVSXD %R14D,%R14 |
(257) 0x432e4a SUB %R9,%R14 |
(257) 0x432e4d IMUL %R8,%R14 |
(257) 0x432e51 MOVSXD %R15D,%R15 |
(257) 0x432e54 SUB %R9,%R15 |
(257) 0x432e57 IMUL %R8,%R15 |
(257) 0x432e5b ADD %R10,%RAX |
(257) 0x432e5e MOVSD 0x10(%RAX,%RDX,8),%XMM8 |
(257) 0x432e65 ADD %R10,%R15 |
(257) 0x432e68 MOVAPD %XMM8,%XMM11 |
(257) 0x432e6d MOVHPD 0x10(%R15,%RDX,8),%XMM11 |
(257) 0x432e74 ADD %R10,%R14 |
(257) 0x432e77 MOVSD 0x10(%R14,%RDX,8),%XMM10 |
(257) 0x432e7e UNPCKLPD %XMM8,%XMM10 |
(257) 0x432e83 SUBPD %XMM10,%XMM11 |
(257) 0x432e88 MOVAPD %XMM11,%XMM10 |
(257) 0x432e8d UNPCKHPD %XMM11,%XMM10 |
(257) 0x432e92 MOVAPD %XMM10,%XMM12 |
(257) 0x432e97 MULSD %XMM11,%XMM12 |
(257) 0x432e9c UCOMISD %XMM9,%XMM12 |
(257) 0x432ea1 JBE 432da0 |
(257) 0x432ea7 UCOMISD %XMM6,%XMM1 |
(257) 0x432eab MOV -0x48(%RBP),%EAX |
(257) 0x432eae CMOVA %R13D,%EAX |
(257) 0x432eb2 ANDPD %XMM0,%XMM11 |
(257) 0x432eb7 MOVAPD %XMM2,%XMM9 |
(257) 0x432ebc SUBSD %XMM7,%XMM9 |
(257) 0x432ec1 MOVAPD %XMM7,%XMM13 |
(257) 0x432ec6 ADDSD %XMM3,%XMM13 |
(257) 0x432ecb UNPCKLPD %XMM9,%XMM13 |
(257) 0x432ed0 CLTQ |
(257) 0x432ed2 SUB %R9,%RAX |
(257) 0x432ed5 MOV 0x18(%RBP),%R8 |
(257) 0x432ed9 MOV -0x58(%RBP),%R14 |
(257) 0x432edd MOVSD (%R8,%R14,8),%XMM12 |
(257) 0x432ee3 MULPD %XMM11,%XMM13 |
(257) 0x432ee8 MOVSD (%R8,%RAX,8),%XMM9 |
(257) 0x432eee UNPCKLPD %XMM12,%XMM9 |
(257) 0x432ef3 DIVPD %XMM9,%XMM13 |
(257) 0x432ef8 MOVAPD %XMM13,%XMM9 |
(257) 0x432efd UNPCKHPD %XMM13,%XMM9 |
(257) 0x432f02 ADDSD %XMM13,%XMM9 |
(257) 0x432f07 MULSD %XMM4,%XMM12 |
(257) 0x432f0c MULSD %XMM9,%XMM12 |
(257) 0x432f11 PSHUFD $-0x12,%XMM11,%XMM9 |
(257) 0x432f17 MOVAPD %XMM11,%XMM13 |
(257) 0x432f1c CMPSD $0x2,%XMM9,%XMM13 |
(257) 0x432f22 ANDPD %XMM13,%XMM11 |
(257) 0x432f27 ANDNPD %XMM9,%XMM13 |
(257) 0x432f2c ORPD %XMM11,%XMM13 |
(257) 0x432f31 MOVAPD %XMM12,%XMM9 |
(257) 0x432f36 CMPSD $0x2,%XMM13,%XMM9 |
(257) 0x432f3c ANDPD %XMM9,%XMM12 |
(257) 0x432f41 ANDNPD %XMM13,%XMM9 |
(257) 0x432f46 ORPD %XMM12,%XMM9 |
(257) 0x432f4b CMPSD $0x2,%XMM1,%XMM10 |
(257) 0x432f51 MOVAPD %XMM10,%XMM11 |
(257) 0x432f56 ANDNPD %XMM9,%XMM11 |
(257) 0x432f5b XORPD %XMM5,%XMM9 |
(257) 0x432f60 ANDPD %XMM10,%XMM9 |
(257) 0x432f65 ORPD %XMM11,%XMM9 |
(257) 0x432f6a JMP 432da0 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-861-0321/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 213 - 241 |
-------------------------------------------------------------------------------- |
213: DO k=y_min-1,y_max+1 |
214: DO j=x_min,x_max+1 |
215: IF(node_flux(j,k).LT.0.0)THEN |
[...] |
221: upwind=k-1 |
222: donor=k |
223: downwind=k+1 |
224: dif=upwind |
225: ENDIF |
226: |
227: sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor)) |
228: width=celldy(k) |
229: vdiffuw=vel1(j,donor)-vel1(j,upwind) |
230: vdiffdw=vel1(j,downwind)-vel1(j,donor) |
231: limiter=0.0 |
232: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
233: auw=ABS(vdiffuw) |
234: adw=ABS(vdiffdw) |
235: wind=1.0_8 |
236: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
237: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw) |
238: ENDIF |
239: advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter |
240: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
241: ENDDO |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 6.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.13 |
Bottlenecks | |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:213-215,advec_mom_kernel.f90:221-223,advec_mom_kernel.f90:228-228 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.33 |
CQA cycles if no scalar integer | 3.33 |
CQA cycles if FP arith vectorized | 3.33 |
CQA cycles if fully vectorized | 0.56 |
Front-end cycles | 3.28 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 2.50 |
P1 cycles | 2.33 |
P2 cycles | 2.33 |
P3 cycles | 1.33 |
P4 cycles | 3.00 |
P5 cycles | 3.00 |
P6 cycles | 3.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 20.00 |
Nb uops | 19.67 |
Nb loads | 6.67 |
Nb stores | 2.33 |
Nb stack references | 7.33 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.56 |
Bytes prefetched | 0.00 |
Bytes loaded | 45.33 |
Bytes stored | 16.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 5.33 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 10.94 |
Vector-efficiency ratio load | 11.11 |
Vector-efficiency ratio store | 11.11 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 10.42 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 10.42 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 5.71 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.11 |
Bottlenecks | P5, P6, P7, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:213-215,advec_mom_kernel.f90:221-223,advec_mom_kernel.f90:228-228 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 1.67 |
CQA cycles if no scalar integer | 1.67 |
CQA cycles if FP arith vectorized | 1.67 |
CQA cycles if fully vectorized | 0.29 |
Front-end cycles | 1.50 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 1.00 |
P4 cycles | 1.67 |
P5 cycles | 1.67 |
P6 cycles | 1.67 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 10.00 |
Nb uops | 9.00 |
Nb loads | 4.00 |
Nb stores | 1.00 |
Nb stack references | 4.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 19.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 24.00 |
Bytes stored | 8.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 6.06 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.14 |
Bottlenecks | micro-operation queue, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:213-215,advec_mom_kernel.f90:221-223,advec_mom_kernel.f90:228-228 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.17 |
CQA cycles if no scalar integer | 4.17 |
CQA cycles if FP arith vectorized | 4.17 |
CQA cycles if fully vectorized | 0.69 |
Front-end cycles | 4.17 |
DIV/SQRT cycles | 3.25 |
P0 cycles | 3.25 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 1.50 |
P4 cycles | 3.67 |
P5 cycles | 3.67 |
P6 cycles | 3.67 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 25.00 |
Nb uops | 25.00 |
Nb loads | 8.00 |
Nb stores | 3.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.24 |
Bytes prefetched | 0.00 |
Bytes loaded | 56.00 |
Bytes stored | 20.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 8.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 10.16 |
Vector-efficiency ratio load | 10.42 |
Vector-efficiency ratio store | 10.42 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 9.38 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.38 |
Path / |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:213-241 |
Module | exec |
nb instructions | 20 |
nb uops | 19.67 |
loop length | 71.33 |
used x86 registers | 7.33 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7.33 |
micro-operation queue | 3.28 cycles |
front end | 3.28 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 2.33 | 2.33 | 1.33 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 2.50 | 2.50 | 2.33 | 2.33 | 1.33 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 3.28 |
Dispatch | 3.00 |
Data deps. | 0.00 |
Overall L1 | 3.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 10% |
load | 11% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 10% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:213-241 |
Module | exec |
nb instructions | 10 |
nb uops | 9 |
loop length | 38 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 4 |
micro-operation queue | 1.50 cycles |
front end | 1.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.67 | 1.67 | 1.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.67 | 1.67 | 1.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 1.50 |
Dispatch | 1.67 |
Data deps. | 0.00 |
Overall L1 | 1.67 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
INC %RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
INC %R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP -0x68(%RBP),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JE 43284f <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x5af> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x88(%RBP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP -0x40(%RBP),%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JL 432d40 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0xaa0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:213-241 |
Module | exec |
nb instructions | 25 |
nb uops | 25 |
loop length | 88 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 4.17 cycles |
front end | 4.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.25 | 3.25 | 3.00 | 3.00 | 1.50 | 3.67 | 3.67 | 3.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 3.25 | 3.25 | 3.00 | 3.00 | 1.50 | 3.67 | 3.67 | 3.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 4.17 |
Dispatch | 3.67 |
Data deps. | 0.00 |
Overall L1 | 4.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 10% |
load | 10% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 9% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
INC %RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
INC %R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP -0x68(%RBP),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JE 43284f <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x5af> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x88(%RBP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP -0x40(%RBP),%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JL 432d40 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0xaa0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x70(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RCX,%RAX,1),%RBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RCX,%RAX,1),%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RAX,%RCX,1),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RBX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R9,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LEA 0x2(%RBX),%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x1(%RBX),%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x78(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
JMP 432dde <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0xb3e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |