Loop Id: 11 | Module: exec | Source: PdV_kernel.f90:114-135 [...] | Coverage: 6.37% |
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Loop Id: 11 | Module: exec | Source: PdV_kernel.f90:114-135 [...] | Coverage: 6.37% |
---|
0x406490 MOV 0x378(%RSP),%RDX [26] |
0x406498 VMOVUPD (%RDX,%RAX,1),%ZMM8 [25] |
0x40649f MOV 0x368(%RSP),%RDX [26] |
0x4064a7 VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM13 [12] |
0x4064ae VMOVUPD (%RDX,%RAX,1),%ZMM12 [22] |
0x4064b5 MOV 0x360(%RSP),%RDX [26] |
0x4064bd VADDPD (%RSI,%RAX,1),%ZMM12,%ZMM14 [16] |
0x4064c4 VMOVUPD (%R9,%RAX,1),%ZMM12 [14] |
0x4064cb VMOVUPD (%RDX,%RAX,1),%ZMM15 [10] |
0x4064d2 MOV 0x358(%RSP),%RDX [26] |
0x4064da VADDPD (%RBX,%RAX,1),%ZMM15,%ZMM2 [2] |
0x4064e1 VADDPD %ZMM14,%ZMM13,%ZMM8 |
0x4064e7 VADDPD (%R15,%RAX,1),%ZMM12,%ZMM14 [5] |
0x4064ee VMOVUPD (%RDX,%RAX,1),%ZMM5 [6] |
0x4064f5 VADDPD (%R13,%RAX,1),%ZMM5,%ZMM3 [24] |
0x4064fd MOV 0x340(%RSP),%RDX [26] |
0x406505 VADDPD %ZMM3,%ZMM2,%ZMM13 |
0x40650b VMULPD (%RDX,%RAX,1),%ZMM13,%ZMM13 [8] |
0x406512 VMOVQ %XMM4,%RDX |
0x406517 VMOVUPD (%RDX,%RAX,1),%ZMM15 [15] |
0x40651e MOV 0x350(%RSP),%RDX [26] |
0x406526 VADDPD (%R11,%RAX,1),%ZMM15,%ZMM2 [17] |
0x40652d VMOVUPD (%RDX,%RAX,1),%ZMM5 [29] |
0x406534 VMOVQ %XMM10,%RDX |
0x406539 VADDPD (%RDX,%RAX,1),%ZMM5,%ZMM3 [18] |
0x406540 MOV 0x348(%RSP),%RDX [26] |
0x406548 VADDPD %ZMM2,%ZMM14,%ZMM14 |
0x40654e VMOVUPD (%RDX,%RAX,1),%ZMM12 [20] |
0x406555 VADDPD (%R8,%RAX,1),%ZMM12,%ZMM15 [27] |
0x40655c MOV 0x338(%RSP),%RDX [26] |
0x406564 VADDPD %ZMM15,%ZMM3,%ZMM2 |
0x40656a VMULPD (%RDX,%RAX,1),%ZMM2,%ZMM5 [4] |
0x406571 VMOVQ %XMM6,%RDX |
0x406576 VMOVUPD (%R12,%RAX,1),%ZMM2 [28] |
0x40657d VFMADD231PD (%RDX,%RAX,1),%ZMM14,%ZMM5 [19] |
0x406584 MOV 0x370(%RSP),%RDX [26] |
0x40658c VFMADD132PD (%RDX,%RAX,1),%ZMM13,%ZMM8 [3] |
0x406593 VSUBPD %ZMM8,%ZMM5,%ZMM8 |
0x406599 VMULSD (%RDI),%XMM7,%XMM13 [13] |
0x40659d VBROADCASTSD %XMM13,%ZMM14 |
0x4065a3 VMULPD %ZMM14,%ZMM8,%ZMM15 |
0x4065a9 VADDPD (%R12,%RAX,1),%ZMM15,%ZMM3 [28] |
0x4065b0 MOV 0x330(%RSP),%RDX [26] |
0x4065b8 VDIVPD %ZMM2,%ZMM9,%ZMM14 |
0x4065be VMOVUPD (%RDX,%RAX,1),%ZMM12 [23] |
0x4065c5 VADDPD (%R14,%RAX,1),%ZMM12,%ZMM13 [21] |
0x4065cc MOV 0x328(%RSP),%RDX [26] |
0x4065d4 VDIVPD (%R10,%RAX,1),%ZMM13,%ZMM8 [9] |
0x4065db VDIVPD %ZMM3,%ZMM2,%ZMM5 |
0x4065e1 VMULPD %ZMM14,%ZMM8,%ZMM3 |
0x4065e7 VFNMADD213PD (%RDX,%RAX,1),%ZMM3,%ZMM15 [11] |
0x4065ee MOV 0x320(%RSP),%RDX [26] |
0x4065f6 VMOVUPD %ZMM15,(%RDX,%RAX,1) [7] |
0x4065fd VMULPD (%R10,%RAX,1),%ZMM5,%ZMM15 [9] |
0x406604 MOV 0x318(%RSP),%RDX [26] |
0x40660c VMOVUPD %ZMM15,(%RDX,%RAX,1) [1] |
0x406613 MOV 0x310(%RSP),%RDX [26] |
0x40661b ADD $0x40,%RAX |
0x40661f CMP %RDX,%RAX |
0x406622 JNE 406490 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-861-0321/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90: 114 - 135 |
-------------------------------------------------------------------------------- |
114: +xvel1(j ,k )+xvel1(j ,k+1)))*0.25_8*dt |
115: right_flux= (xarea(j+1,k )*(xvel0(j+1,k )+xvel0(j+1,k+1) & |
116: +xvel1(j+1,k )+xvel1(j+1,k+1)))*0.25_8*dt |
117: bottom_flux=(yarea(j ,k )*(yvel0(j ,k )+yvel0(j+1,k ) & |
118: +yvel1(j ,k )+yvel1(j+1,k )))*0.25_8*dt |
119: top_flux= (yarea(j ,k+1)*(yvel0(j ,k+1)+yvel0(j+1,k+1) & |
120: +yvel1(j ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt |
121: total_flux=right_flux-left_flux+top_flux-bottom_flux |
122: |
123: volume_change_s=volume(j,k)/(volume(j,k)+total_flux) |
[...] |
129: recip_volume=1.0/volume(j,k) |
130: |
131: energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume |
132: |
133: energy1(j,k)=energy0(j,k)-energy_change |
134: |
135: density1(j,k)=density0(j,k)*volume_change_s |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.14 |
Bottlenecks | P8, P9, |
Function | __pdv_kernel_module_MOD_pdv_kernel._omp_fn.0 |
Source | PdV_kernel.f90:114-123,PdV_kernel.f90:129-135 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 27.00 |
CQA cycles if no scalar integer | 27.00 |
CQA cycles if FP arith vectorized | 27.00 |
CQA cycles if fully vectorized | 27.00 |
Front-end cycles | 10.17 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 23.67 |
P5 cycles | 23.67 |
P6 cycles | 23.67 |
P7 cycles | 12.50 |
P8 cycles | 11.50 |
P9 cycles | 15.00 |
P10 cycles | 15.00 |
P11 cycles | 3.50 |
P12 cycles | 3.50 |
P13 cycles | 27.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 60.00 |
Nb uops | 61.00 |
Nb loads | 42.00 |
Nb stores | 2.00 |
Nb stack references | 14.00 |
FLOP/cycle | 8.63 |
Nb FLOP add-sub | 120.00 |
Nb FLOP mul | 41.00 |
Nb FLOP fma | 24.00 |
Nb FLOP div | 24.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 73.19 |
Bytes prefetched | 0.00 |
Bytes loaded | 1848.00 |
Bytes stored | 128.00 |
Stride 0 | 2.00 |
Stride 1 | 9.00 |
Stride n | 2.00 |
Stride unknown | 1.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 88.37 |
Vectorization ratio load | 96.43 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 83.33 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 89.83 |
Vector-efficiency ratio load | 96.88 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 85.42 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.14 |
Bottlenecks | P8, P9, |
Function | __pdv_kernel_module_MOD_pdv_kernel._omp_fn.0 |
Source | PdV_kernel.f90:114-123,PdV_kernel.f90:129-135 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 27.00 |
CQA cycles if no scalar integer | 27.00 |
CQA cycles if FP arith vectorized | 27.00 |
CQA cycles if fully vectorized | 27.00 |
Front-end cycles | 10.17 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 23.67 |
P5 cycles | 23.67 |
P6 cycles | 23.67 |
P7 cycles | 12.50 |
P8 cycles | 11.50 |
P9 cycles | 15.00 |
P10 cycles | 15.00 |
P11 cycles | 3.50 |
P12 cycles | 3.50 |
P13 cycles | 27.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 60.00 |
Nb uops | 61.00 |
Nb loads | 42.00 |
Nb stores | 2.00 |
Nb stack references | 14.00 |
FLOP/cycle | 8.63 |
Nb FLOP add-sub | 120.00 |
Nb FLOP mul | 41.00 |
Nb FLOP fma | 24.00 |
Nb FLOP div | 24.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 73.19 |
Bytes prefetched | 0.00 |
Bytes loaded | 1848.00 |
Bytes stored | 128.00 |
Stride 0 | 2.00 |
Stride 1 | 9.00 |
Stride n | 2.00 |
Stride unknown | 1.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 88.37 |
Vectorization ratio load | 96.43 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 83.33 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 89.83 |
Vector-efficiency ratio load | 96.88 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 85.42 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | __pdv_kernel_module_MOD_pdv_kernel._omp_fn.0 |
Source file and lines | PdV_kernel.f90:114-135 |
Module | exec |
nb instructions | 60 |
nb uops | 61 |
loop length | 408 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 9 |
nb stack references | 14 |
ADD-SUB / MUL ratio | 2.50 |
micro-operation queue | 10.17 cycles |
front end | 10.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 14.67 | 14.67 | 14.67 | 6.50 | 6.50 | 7.50 | 7.50 | 3.50 | 3.50 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 23.67 | 23.67 | 23.67 | 12.50 | 11.50 | 15.00 | 15.00 | 3.50 | 3.50 |
Cycles executing div or sqrt instructions | 27.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 10.17 |
Dispatch | 23.67 |
DIV/SQRT | 27.00 |
Data deps. | 1.00 |
Overall L1 | 27.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 95% |
load | 96% |
store | 100% |
mul | 83% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 0% |
all | 88% |
load | 96% |
store | 100% |
mul | 83% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 95% |
load | 96% |
store | 100% |
mul | 85% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 12% |
all | 89% |
load | 96% |
store | 100% |
mul | 85% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x378(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVUPD (%RDX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x368(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x360(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD (%RSI,%RAX,1),%ZMM12,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%R9,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x358(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD (%RBX,%RAX,1),%ZMM15,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM14,%ZMM13,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD (%R15,%RAX,1),%ZMM12,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R13,%RAX,1),%ZMM5,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x340(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD %ZMM3,%ZMM2,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD (%RDX,%RAX,1),%ZMM13,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM4,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x350(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD (%R11,%RAX,1),%ZMM15,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM10,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VADDPD (%RDX,%RAX,1),%ZMM5,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x348(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD %ZMM2,%ZMM14,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R8,%RAX,1),%ZMM12,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x338(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD %ZMM15,%ZMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD (%RDX,%RAX,1),%ZMM2,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM6,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVUPD (%R12,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFMADD231PD (%RDX,%RAX,1),%ZMM14,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
MOV 0x370(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VFMADD132PD (%RDX,%RAX,1),%ZMM13,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VSUBPD %ZMM8,%ZMM5,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULSD (%RDI),%XMM7,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMULPD %ZMM14,%ZMM8,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R12,%RAX,1),%ZMM15,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x330(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VDIVPD %ZMM2,%ZMM9,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R14,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x328(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VDIVPD (%R10,%RAX,1),%ZMM13,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM3,%ZMM2,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMULPD %ZMM14,%ZMM8,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VFNMADD213PD (%RDX,%RAX,1),%ZMM3,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
MOV 0x320(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVUPD %ZMM15,(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMULPD (%R10,%RAX,1),%ZMM5,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x318(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVUPD %ZMM15,(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
MOV 0x310(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RDX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 406490 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x1e40> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | __pdv_kernel_module_MOD_pdv_kernel._omp_fn.0 |
Source file and lines | PdV_kernel.f90:114-135 |
Module | exec |
nb instructions | 60 |
nb uops | 61 |
loop length | 408 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 9 |
nb stack references | 14 |
ADD-SUB / MUL ratio | 2.50 |
micro-operation queue | 10.17 cycles |
front end | 10.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 14.67 | 14.67 | 14.67 | 6.50 | 6.50 | 7.50 | 7.50 | 3.50 | 3.50 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 23.67 | 23.67 | 23.67 | 12.50 | 11.50 | 15.00 | 15.00 | 3.50 | 3.50 |
Cycles executing div or sqrt instructions | 27.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 10.17 |
Dispatch | 23.67 |
DIV/SQRT | 27.00 |
Data deps. | 1.00 |
Overall L1 | 27.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 95% |
load | 96% |
store | 100% |
mul | 83% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 0% |
all | 88% |
load | 96% |
store | 100% |
mul | 83% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 95% |
load | 96% |
store | 100% |
mul | 85% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 12% |
all | 89% |
load | 96% |
store | 100% |
mul | 85% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x378(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVUPD (%RDX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x368(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x360(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD (%RSI,%RAX,1),%ZMM12,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%R9,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x358(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD (%RBX,%RAX,1),%ZMM15,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM14,%ZMM13,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD (%R15,%RAX,1),%ZMM12,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R13,%RAX,1),%ZMM5,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x340(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD %ZMM3,%ZMM2,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD (%RDX,%RAX,1),%ZMM13,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM4,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x350(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD (%R11,%RAX,1),%ZMM15,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM10,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VADDPD (%RDX,%RAX,1),%ZMM5,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x348(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD %ZMM2,%ZMM14,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R8,%RAX,1),%ZMM12,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x338(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD %ZMM15,%ZMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD (%RDX,%RAX,1),%ZMM2,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM6,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVUPD (%R12,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFMADD231PD (%RDX,%RAX,1),%ZMM14,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
MOV 0x370(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VFMADD132PD (%RDX,%RAX,1),%ZMM13,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VSUBPD %ZMM8,%ZMM5,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULSD (%RDI),%XMM7,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMULPD %ZMM14,%ZMM8,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R12,%RAX,1),%ZMM15,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x330(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VDIVPD %ZMM2,%ZMM9,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R14,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x328(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VDIVPD (%R10,%RAX,1),%ZMM13,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM3,%ZMM2,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMULPD %ZMM14,%ZMM8,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VFNMADD213PD (%RDX,%RAX,1),%ZMM3,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
MOV 0x320(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVUPD %ZMM15,(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMULPD (%R10,%RAX,1),%ZMM5,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x318(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVUPD %ZMM15,(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
MOV 0x310(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RDX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 406490 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x1e40> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |