Loop Id: 114 | Module: exec | Source: advec_mom_kernel.f90:96-97 | Coverage: 2.93% |
---|
Loop Id: 114 | Module: exec | Source: advec_mom_kernel.f90:96-97 | Coverage: 2.93% |
---|
0x41ed97 VMOVUPD (%R13,%RAX,1),%ZMM0 [4] |
0x41ed9f VADDPD (%RSI,%RAX,1),%ZMM0,%ZMM7 [6] |
0x41eda6 MOV 0xe8(%RSP),%RDX [8] |
0x41edae VSUBPD (%R12,%RAX,1),%ZMM7,%ZMM13 [7] |
0x41edb5 VMOVUPD %ZMM13,(%RDI,%RAX,1) [5] |
0x41edbc VMOVUPD (%R14,%RAX,1),%ZMM14 [3] |
0x41edc3 VSUBPD (%R9,%RAX,1),%ZMM14,%ZMM5 [2] |
0x41edca VADDPD %ZMM13,%ZMM5,%ZMM15 |
0x41edd0 VMOVUPD %ZMM15,(%RCX,%RAX,1) [1] |
0x41edd7 VMOVUPD 0x40(%R13,%RAX,1),%ZMM4 [4] |
0x41eddf VADDPD 0x40(%RAX,%RSI,1),%ZMM4,%ZMM2 [9] |
0x41ede7 VSUBPD 0x40(%R12,%RAX,1),%ZMM2,%ZMM0 [7] |
0x41edef VMOVUPD %ZMM0,0x40(%RDI,%RAX,1) [5] |
0x41edf7 VMOVUPD 0x40(%R14,%RAX,1),%ZMM7 [3] |
0x41edff VSUBPD 0x40(%R9,%RAX,1),%ZMM7,%ZMM13 [2] |
0x41ee07 VADDPD %ZMM0,%ZMM13,%ZMM14 |
0x41ee0d VMOVUPD %ZMM14,0x40(%RCX,%RAX,1) [1] |
0x41ee15 VMOVUPD 0x80(%R13,%RAX,1),%ZMM5 [4] |
0x41ee1d VADDPD 0x80(%RAX,%RSI,1),%ZMM5,%ZMM15 [9] |
0x41ee25 VSUBPD 0x80(%R12,%RAX,1),%ZMM15,%ZMM0 [7] |
0x41ee2d VMOVUPD %ZMM0,0x80(%RDI,%RAX,1) [5] |
0x41ee35 VMOVUPD 0x80(%R14,%RAX,1),%ZMM4 [3] |
0x41ee3d VSUBPD 0x80(%R9,%RAX,1),%ZMM4,%ZMM2 [2] |
0x41ee45 VADDPD %ZMM0,%ZMM2,%ZMM7 |
0x41ee4b VMOVUPD %ZMM7,0x80(%RCX,%RAX,1) [1] |
0x41ee53 VMOVUPD 0xc0(%R13,%RAX,1),%ZMM13 [4] |
0x41ee5b VADDPD 0xc0(%RAX,%RSI,1),%ZMM13,%ZMM14 [9] |
0x41ee63 VSUBPD 0xc0(%R12,%RAX,1),%ZMM14,%ZMM5 [7] |
0x41ee6b VMOVUPD %ZMM5,0xc0(%RDI,%RAX,1) [5] |
0x41ee73 VMOVUPD 0xc0(%R14,%RAX,1),%ZMM15 [3] |
0x41ee7b VSUBPD 0xc0(%R9,%RAX,1),%ZMM15,%ZMM0 [2] |
0x41ee83 VADDPD %ZMM5,%ZMM0,%ZMM4 |
0x41ee89 VMOVUPD %ZMM4,0xc0(%RCX,%RAX,1) [1] |
0x41ee91 ADD $0x100,%RAX |
0x41ee97 CMP %RDX,%RAX |
0x41ee9a JNE 41ed97 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-861-0321/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 96 - 97 |
-------------------------------------------------------------------------------- |
96: post_vol(j,k)= volume(j,k)+vol_flux_x(j+1,k )-vol_flux_x(j,k) |
97: pre_vol(j,k)=post_vol(j,k)+vol_flux_y(j ,k+1)-vol_flux_y(j,k) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.02 |
Bottlenecks | P5, P6, P7, |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source | advec_mom_kernel.f90:96-97 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 16.33 |
CQA cycles if no scalar integer | 16.33 |
CQA cycles if FP arith vectorized | 16.33 |
CQA cycles if fully vectorized | 16.33 |
Front-end cycles | 7.17 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 16.33 |
P5 cycles | 16.33 |
P6 cycles | 16.33 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 16.00 |
P10 cycles | 16.00 |
P11 cycles | 8.00 |
P12 cycles | 8.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 36.00 |
Nb uops | 43.00 |
Nb loads | 21.00 |
Nb stores | 8.00 |
Nb stack references | 1.00 |
FLOP/cycle | 7.84 |
Nb FLOP add-sub | 128.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 110.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 1288.00 |
Bytes stored | 512.00 |
Stride 0 | 1.00 |
Stride 1 | 6.00 |
Stride n | 2.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.02 |
Bottlenecks | P5, P6, P7, |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source | advec_mom_kernel.f90:96-97 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 16.33 |
CQA cycles if no scalar integer | 16.33 |
CQA cycles if FP arith vectorized | 16.33 |
CQA cycles if fully vectorized | 16.33 |
Front-end cycles | 7.17 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 16.33 |
P5 cycles | 16.33 |
P6 cycles | 16.33 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 16.00 |
P10 cycles | 16.00 |
P11 cycles | 8.00 |
P12 cycles | 8.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 36.00 |
Nb uops | 43.00 |
Nb loads | 21.00 |
Nb stores | 8.00 |
Nb stack references | 1.00 |
FLOP/cycle | 7.84 |
Nb FLOP add-sub | 128.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 110.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 1288.00 |
Bytes stored | 512.00 |
Stride 0 | 1.00 |
Stride 1 | 6.00 |
Stride n | 2.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source file and lines | advec_mom_kernel.f90:96-97 |
Module | exec |
nb instructions | 36 |
nb uops | 43 |
loop length | 265 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 8 |
nb stack references | 1 |
micro-operation queue | 7.17 cycles |
front end | 7.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 9.67 | 9.67 | 9.67 | 0.00 | 0.00 | 8.00 | 8.00 | 8.00 | 8.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 16.33 | 16.33 | 16.33 | 0.00 | 0.00 | 16.00 | 16.00 | 8.00 | 8.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 7.17 |
Dispatch | 16.33 |
Data deps. | 1.00 |
Overall L1 | 16.33 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R13,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%RSI,%RAX,1),%ZMM0,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0xe8(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VSUBPD (%R12,%RAX,1),%ZMM7,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM13,(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD (%R14,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD (%R9,%RAX,1),%ZMM14,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM13,%ZMM5,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM15,(%RCX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R13,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%RAX,%RSI,1),%ZMM4,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R12,%RAX,1),%ZMM2,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0x40(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R14,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R9,%RAX,1),%ZMM7,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM0,%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM14,0x40(%RCX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x80(%R13,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x80(%RAX,%RSI,1),%ZMM5,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x80(%R12,%RAX,1),%ZMM15,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0x80(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x80(%R14,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD 0x80(%R9,%RAX,1),%ZMM4,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM0,%ZMM2,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM7,0x80(%RCX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0xc0(%R13,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0xc0(%RAX,%RSI,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0xc0(%R12,%RAX,1),%ZMM14,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM5,0xc0(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0xc0(%R14,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD 0xc0(%R9,%RAX,1),%ZMM15,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM5,%ZMM0,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM4,0xc0(%RCX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
ADD $0x100,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RDX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 41ed97 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x557> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source file and lines | advec_mom_kernel.f90:96-97 |
Module | exec |
nb instructions | 36 |
nb uops | 43 |
loop length | 265 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 8 |
nb stack references | 1 |
micro-operation queue | 7.17 cycles |
front end | 7.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 9.67 | 9.67 | 9.67 | 0.00 | 0.00 | 8.00 | 8.00 | 8.00 | 8.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 16.33 | 16.33 | 16.33 | 0.00 | 0.00 | 16.00 | 16.00 | 8.00 | 8.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 7.17 |
Dispatch | 16.33 |
Data deps. | 1.00 |
Overall L1 | 16.33 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R13,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%RSI,%RAX,1),%ZMM0,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0xe8(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VSUBPD (%R12,%RAX,1),%ZMM7,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM13,(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD (%R14,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD (%R9,%RAX,1),%ZMM14,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM13,%ZMM5,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM15,(%RCX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R13,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%RAX,%RSI,1),%ZMM4,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R12,%RAX,1),%ZMM2,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0x40(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R14,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R9,%RAX,1),%ZMM7,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM0,%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM14,0x40(%RCX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x80(%R13,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x80(%RAX,%RSI,1),%ZMM5,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x80(%R12,%RAX,1),%ZMM15,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0x80(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x80(%R14,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD 0x80(%R9,%RAX,1),%ZMM4,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM0,%ZMM2,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM7,0x80(%RCX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0xc0(%R13,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0xc0(%RAX,%RSI,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0xc0(%R12,%RAX,1),%ZMM14,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM5,0xc0(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0xc0(%R14,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD 0xc0(%R9,%RAX,1),%ZMM15,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM5,%ZMM0,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM4,0xc0(%RCX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
ADD $0x100,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RDX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 41ed97 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x557> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |