Loop Id: 148 | Module: exec | Source: flux_calc_kernel.f90:58-60 | Coverage: 4.17% |
---|
Loop Id: 148 | Module: exec | Source: flux_calc_kernel.f90:58-60 | Coverage: 4.17% |
---|
0x4284fd MOV 0x140(%RSP),%RSI [24] |
0x428505 MOV 0x178(%RSP),%RDX [24] |
0x42850d VMULSD (%R15),%XMM2,%XMM22 [12] |
0x428513 VBROADCASTSD %XMM22,%ZMM24 |
0x428519 VMULPD (%R12,%RAX,1),%ZMM24,%ZMM25 [10] |
0x428520 MOV 0x170(%RSP),%RCX [24] |
0x428528 VMOVUPD (%RSI,%RAX,1),%ZMM7 [6] |
0x42852f VMOVUPD (%RDX,%RAX,1),%ZMM0 [1] |
0x428536 VADDPD (%R9,%RAX,1),%ZMM7,%ZMM6 [2] |
0x42853d VADDPD (%R8,%RAX,1),%ZMM0,%ZMM23 [16] |
0x428544 VADDPD %ZMM23,%ZMM6,%ZMM1 |
0x42854a VMULPD %ZMM25,%ZMM1,%ZMM7 |
0x428550 VMOVUPD %ZMM7,(%R13,%RAX,1) [3] |
0x428558 VMOVUPD (%RDI,%RAX,1),%ZMM6 [7] |
0x42855f VMOVUPD (%R11,%RAX,1),%ZMM1 [9] |
0x428566 VADDPD (%R10,%RAX,1),%ZMM6,%ZMM0 [4] |
0x42856d VADDPD (%RBX,%RAX,1),%ZMM1,%ZMM27 [5] |
0x428574 VMULSD (%R15),%XMM2,%XMM26 [12] |
0x42857a VBROADCASTSD %XMM26,%ZMM28 |
0x428580 VMULPD (%R14,%RAX,1),%ZMM28,%ZMM29 [20] |
0x428587 VADDPD %ZMM27,%ZMM0,%ZMM7 |
0x42858d VMULPD %ZMM29,%ZMM7,%ZMM6 |
0x428593 VMOVUPD %ZMM6,(%RCX,%RAX,1) [19] |
0x42859a VMOVUPD 0x40(%RAX,%RSI,1),%ZMM0 [23] |
0x4285a2 MOV 0x178(%RSP),%RSI [24] |
0x4285aa VADDPD 0x40(%RAX,%R9,1),%ZMM0,%ZMM7 [13] |
0x4285b2 VMULSD (%R15),%XMM2,%XMM22 [12] |
0x4285b8 VBROADCASTSD %XMM22,%ZMM24 |
0x4285be VMULPD 0x40(%RAX,%R12,1),%ZMM24,%ZMM25 [22] |
0x4285c6 VMOVUPD 0x40(%RAX,%RSI,1),%ZMM1 [18] |
0x4285ce VADDPD 0x40(%RAX,%R8,1),%ZMM1,%ZMM23 [8] |
0x4285d6 VADDPD %ZMM23,%ZMM7,%ZMM6 |
0x4285dc VMULPD %ZMM25,%ZMM6,%ZMM0 |
0x4285e2 VMOVUPD %ZMM0,0x40(%RAX,%R13,1) [21] |
0x4285ea VMOVUPD 0x40(%RAX,%RDI,1),%ZMM7 [17] |
0x4285f2 VMOVUPD 0x40(%RAX,%R11,1),%ZMM6 [14] |
0x4285fa VADDPD 0x40(%R10,%RAX,1),%ZMM7,%ZMM1 [4] |
0x428602 VADDPD 0x40(%RBX,%RAX,1),%ZMM6,%ZMM27 [5] |
0x42860a VMULSD (%R15),%XMM2,%XMM26 [12] |
0x428610 VBROADCASTSD %XMM26,%ZMM28 |
0x428616 VMULPD 0x40(%RAX,%R14,1),%ZMM28,%ZMM29 [11] |
0x42861e SUB $-0x80,%RAX |
0x428622 VADDPD %ZMM27,%ZMM1,%ZMM0 |
0x428628 VMULPD %ZMM29,%ZMM0,%ZMM7 |
0x42862e VMOVUPD %ZMM7,-0x40(%RAX,%RCX,1) [15] |
0x428636 MOV 0x160(%RSP),%RCX [24] |
0x42863e CMP %RCX,%RAX |
0x428641 JNE 4284fd |
/beegfs/hackathon/users/eoseret/qaas_runs/170-861-0321/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90: 58 - 60 |
-------------------------------------------------------------------------------- |
58: *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1)) |
59: vol_flux_y(j,k)=0.25_8*dt*yarea(j,k) & |
60: *(yvel0(j,k)+yvel0(j+1,k)+yvel1(j,k)+yvel1(j+1,k)) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.06 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.06 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.36 |
Bottlenecks | P5, P6, P7, |
Function | __flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0 |
Source | flux_calc_kernel.f90:58-60 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 17.67 |
CQA cycles if no scalar integer | 16.67 |
CQA cycles if FP arith vectorized | 17.67 |
CQA cycles if fully vectorized | 16.67 |
Front-end cycles | 8.50 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 17.67 |
P5 cycles | 17.67 |
P6 cycles | 17.67 |
P7 cycles | 13.00 |
P8 cycles | 9.50 |
P9 cycles | 12.50 |
P10 cycles | 13.00 |
P11 cycles | 4.00 |
P12 cycles | 4.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 48.00 |
Nb uops | 51.00 |
Nb loads | 29.00 |
Nb stores | 4.00 |
Nb stack references | 4.00 |
FLOP/cycle | 9.28 |
Nb FLOP add-sub | 96.00 |
Nb FLOP mul | 68.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 91.02 |
Bytes prefetched | 0.00 |
Bytes loaded | 1352.00 |
Bytes stored | 256.00 |
Stride 0 | 2.00 |
Stride 1 | 3.00 |
Stride n | 18.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 80.00 |
Vectorization ratio load | 83.33 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 66.67 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 82.50 |
Vector-efficiency ratio load | 85.42 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 70.83 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.06 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.06 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.36 |
Bottlenecks | P5, P6, P7, |
Function | __flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0 |
Source | flux_calc_kernel.f90:58-60 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 17.67 |
CQA cycles if no scalar integer | 16.67 |
CQA cycles if FP arith vectorized | 17.67 |
CQA cycles if fully vectorized | 16.67 |
Front-end cycles | 8.50 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 17.67 |
P5 cycles | 17.67 |
P6 cycles | 17.67 |
P7 cycles | 13.00 |
P8 cycles | 9.50 |
P9 cycles | 12.50 |
P10 cycles | 13.00 |
P11 cycles | 4.00 |
P12 cycles | 4.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 48.00 |
Nb uops | 51.00 |
Nb loads | 29.00 |
Nb stores | 4.00 |
Nb stack references | 4.00 |
FLOP/cycle | 9.28 |
Nb FLOP add-sub | 96.00 |
Nb FLOP mul | 68.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 91.02 |
Bytes prefetched | 0.00 |
Bytes loaded | 1352.00 |
Bytes stored | 256.00 |
Stride 0 | 2.00 |
Stride 1 | 3.00 |
Stride n | 18.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 80.00 |
Vectorization ratio load | 83.33 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 66.67 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 82.50 |
Vector-efficiency ratio load | 85.42 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 70.83 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | __flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0 |
Source file and lines | flux_calc_kernel.f90:58-60 |
Module | exec |
nb instructions | 48 |
nb uops | 51 |
loop length | 330 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 10 |
nb stack references | 4 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 8.50 cycles |
front end | 8.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 11.00 | 11.00 | 11.00 | 7.50 | 7.00 | 7.00 | 6.50 | 4.00 | 4.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 17.67 | 17.67 | 17.67 | 13.00 | 9.50 | 12.50 | 13.00 | 4.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 8.50 |
Dispatch | 17.67 |
Data deps. | 1.00 |
Overall L1 | 17.67 |
all | 80% |
load | 83% |
store | 100% |
mul | 66% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 82% |
load | 85% |
store | 100% |
mul | 70% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x140(%RSP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x178(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMULSD (%R15),%XMM2,%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM22,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMULPD (%R12,%RAX,1),%ZMM24,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x170(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVUPD (%RSI,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R9,%RAX,1),%ZMM7,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD (%R8,%RAX,1),%ZMM0,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM23,%ZMM6,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM25,%ZMM1,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM7,(%R13,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD (%RDI,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD (%R11,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R10,%RAX,1),%ZMM6,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD (%RBX,%RAX,1),%ZMM1,%ZMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULSD (%R15),%XMM2,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM26,%ZMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMULPD (%R14,%RAX,1),%ZMM28,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %ZMM27,%ZMM0,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM29,%ZMM7,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM6,(%RCX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%RAX,%RSI,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x178(%RSP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD 0x40(%RAX,%R9,1),%ZMM0,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULSD (%R15),%XMM2,%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM22,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMULPD 0x40(%RAX,%R12,1),%ZMM24,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%RAX,%RSI,1),%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%RAX,%R8,1),%ZMM1,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM23,%ZMM7,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM25,%ZMM6,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0x40(%RAX,%R13,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%RAX,%RDI,1),%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%RAX,%R11,1),%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%R10,%RAX,1),%ZMM7,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%RBX,%RAX,1),%ZMM6,%ZMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULSD (%R15),%XMM2,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM26,%ZMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMULPD 0x40(%RAX,%R14,1),%ZMM28,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB $-0x80,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VADDPD %ZMM27,%ZMM1,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM29,%ZMM0,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM7,-0x40(%RAX,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
MOV 0x160(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %RCX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 4284fd <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0+0x6ad> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | __flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0 |
Source file and lines | flux_calc_kernel.f90:58-60 |
Module | exec |
nb instructions | 48 |
nb uops | 51 |
loop length | 330 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 10 |
nb stack references | 4 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 8.50 cycles |
front end | 8.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 11.00 | 11.00 | 11.00 | 7.50 | 7.00 | 7.00 | 6.50 | 4.00 | 4.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 17.67 | 17.67 | 17.67 | 13.00 | 9.50 | 12.50 | 13.00 | 4.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 8.50 |
Dispatch | 17.67 |
Data deps. | 1.00 |
Overall L1 | 17.67 |
all | 80% |
load | 83% |
store | 100% |
mul | 66% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 82% |
load | 85% |
store | 100% |
mul | 70% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x140(%RSP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x178(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMULSD (%R15),%XMM2,%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM22,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMULPD (%R12,%RAX,1),%ZMM24,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x170(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVUPD (%RSI,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R9,%RAX,1),%ZMM7,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD (%R8,%RAX,1),%ZMM0,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM23,%ZMM6,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM25,%ZMM1,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM7,(%R13,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD (%RDI,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD (%R11,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R10,%RAX,1),%ZMM6,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD (%RBX,%RAX,1),%ZMM1,%ZMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULSD (%R15),%XMM2,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM26,%ZMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMULPD (%R14,%RAX,1),%ZMM28,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %ZMM27,%ZMM0,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM29,%ZMM7,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM6,(%RCX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%RAX,%RSI,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x178(%RSP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VADDPD 0x40(%RAX,%R9,1),%ZMM0,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULSD (%R15),%XMM2,%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM22,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMULPD 0x40(%RAX,%R12,1),%ZMM24,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%RAX,%RSI,1),%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%RAX,%R8,1),%ZMM1,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM23,%ZMM7,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM25,%ZMM6,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0x40(%RAX,%R13,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%RAX,%RDI,1),%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%RAX,%R11,1),%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%R10,%RAX,1),%ZMM7,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%RBX,%RAX,1),%ZMM6,%ZMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULSD (%R15),%XMM2,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM26,%ZMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMULPD 0x40(%RAX,%R14,1),%ZMM28,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB $-0x80,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VADDPD %ZMM27,%ZMM1,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM29,%ZMM0,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM7,-0x40(%RAX,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
MOV 0x160(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %RCX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 4284fd <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0.lto_priv.0+0x6ad> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |