Loop Id: 72 | Module: exec | Source: advec_cell_kernel.f90:256-261 | Coverage: 3.4% |
---|
Loop Id: 72 | Module: exec | Source: advec_cell_kernel.f90:256-261 | Coverage: 3.4% |
---|
0x41abbc VMOVUPD (%R8,%RAX,1),%ZMM2 [13] |
0x41abc3 VMULPD (%R15,%RAX,1),%ZMM2,%ZMM1 [3] |
0x41abca VMOVQ %XMM10,%RDX |
0x41abcf VMOVQ %XMM9,%RCX |
0x41abd4 VMOVUPD (%RDX,%RAX,1),%ZMM0 [10] |
0x41abdb VADDPD (%R15,%RAX,1),%ZMM0,%ZMM15 [3] |
0x41abe2 VMOVUPD (%R9,%RAX,1),%ZMM12 [2] |
0x41abe9 VMOVQ %XMM9,%RDX |
0x41abee VSUBPD (%R10,%RAX,1),%ZMM1,%ZMM6 [1] |
0x41abf5 VSUBPD (%RCX,%RAX,1),%ZMM12,%ZMM13 [7] |
0x41abfc VMOVQ %XMM3,%RCX |
0x41ac01 VADDPD (%RSI,%RAX,1),%ZMM6,%ZMM14 [11] |
0x41ac08 VSUBPD (%RCX,%RAX,1),%ZMM15,%ZMM11 [8] |
0x41ac0f VFMADD132PD (%RDI,%RAX,1),%ZMM13,%ZMM1 [6] |
0x41ac16 VMOVQ %XMM10,%RCX |
0x41ac1b VDIVPD %ZMM14,%ZMM1,%ZMM2 |
0x41ac21 VDIVPD %ZMM11,%ZMM14,%ZMM5 |
0x41ac27 VMOVUPD %ZMM5,(%R8,%RAX,1) [13] |
0x41ac2e VMOVUPD %ZMM2,(%RDI,%RAX,1) [6] |
0x41ac35 VMOVUPD 0x40(%R8,%RAX,1),%ZMM6 [13] |
0x41ac3d VMULPD 0x40(%R15,%RAX,1),%ZMM6,%ZMM1 [3] |
0x41ac45 VMOVUPD 0x40(%RCX,%RAX,1),%ZMM15 [5] |
0x41ac4d VADDPD 0x40(%R15,%RAX,1),%ZMM15,%ZMM11 [3] |
0x41ac55 VMOVUPD 0x40(%R9,%RAX,1),%ZMM13 [2] |
0x41ac5d VSUBPD 0x40(%RDX,%RAX,1),%ZMM13,%ZMM0 [9] |
0x41ac65 MOV 0xa8(%RSP),%RCX [12] |
0x41ac6d VSUBPD 0x40(%R10,%RAX,1),%ZMM1,%ZMM14 [1] |
0x41ac75 VMOVQ %XMM3,%RDX |
0x41ac7a VFMADD132PD 0x40(%RDI,%RAX,1),%ZMM0,%ZMM1 [6] |
0x41ac82 VSUBPD 0x40(%RDX,%RAX,1),%ZMM11,%ZMM5 [4] |
0x41ac8a VADDPD 0x40(%RSI,%RAX,1),%ZMM14,%ZMM12 [11] |
0x41ac92 VDIVPD %ZMM5,%ZMM12,%ZMM2 |
0x41ac98 VDIVPD %ZMM12,%ZMM1,%ZMM6 |
0x41ac9e VMOVUPD %ZMM2,0x40(%R8,%RAX,1) [13] |
0x41aca6 VMOVUPD %ZMM6,0x40(%RDI,%RAX,1) [6] |
0x41acae SUB $-0x80,%RAX |
0x41acb2 CMP %RCX,%RAX |
0x41acb5 JNE 41abbc |
/beegfs/hackathon/users/eoseret/qaas_runs/170-861-0321/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 256 - 261 |
-------------------------------------------------------------------------------- |
256: pre_mass_s=density1(j,k)*pre_vol(j,k) |
257: post_mass_s=pre_mass_s+mass_flux_y(j,k)-mass_flux_y(j,k+1) |
258: post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j,k+1))/post_mass_s |
259: advec_vol_s=pre_vol(j,k)+vol_flux_y(j,k)-vol_flux_y(j,k+1) |
260: density1(j,k)=post_mass_s/advec_vol_s |
261: energy1(j,k)=post_ener_s |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.40 |
Bottlenecks | P8, P9, |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source | advec_cell_kernel.f90:256-261 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 36.00 |
CQA cycles if no scalar integer | 36.00 |
CQA cycles if FP arith vectorized | 36.00 |
CQA cycles if fully vectorized | 36.00 |
Front-end cycles | 6.83 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 15.00 |
P5 cycles | 15.00 |
P6 cycles | 15.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 10.00 |
P10 cycles | 10.00 |
P11 cycles | 7.00 |
P12 cycles | 7.00 |
P13 cycles | 36.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 38.00 |
Nb uops | 41.00 |
Nb loads | 21.00 |
Nb stores | 4.00 |
Nb stack references | 1.00 |
FLOP/cycle | 4.44 |
Nb FLOP add-sub | 80.00 |
Nb FLOP mul | 16.00 |
Nb FLOP fma | 16.00 |
Nb FLOP div | 32.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 42.89 |
Bytes prefetched | 0.00 |
Bytes loaded | 1288.00 |
Bytes stored | 256.00 |
Stride 0 | 1.00 |
Stride 1 | 5.00 |
Stride n | 3.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 82.35 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 84.56 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.40 |
Bottlenecks | P8, P9, |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source | advec_cell_kernel.f90:256-261 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 36.00 |
CQA cycles if no scalar integer | 36.00 |
CQA cycles if FP arith vectorized | 36.00 |
CQA cycles if fully vectorized | 36.00 |
Front-end cycles | 6.83 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 15.00 |
P5 cycles | 15.00 |
P6 cycles | 15.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 10.00 |
P10 cycles | 10.00 |
P11 cycles | 7.00 |
P12 cycles | 7.00 |
P13 cycles | 36.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 38.00 |
Nb uops | 41.00 |
Nb loads | 21.00 |
Nb stores | 4.00 |
Nb stack references | 1.00 |
FLOP/cycle | 4.44 |
Nb FLOP add-sub | 80.00 |
Nb FLOP mul | 16.00 |
Nb FLOP fma | 16.00 |
Nb FLOP div | 32.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 42.89 |
Bytes prefetched | 0.00 |
Bytes loaded | 1288.00 |
Bytes stored | 256.00 |
Stride 0 | 1.00 |
Stride 1 | 5.00 |
Stride n | 3.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 82.35 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 84.56 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source file and lines | advec_cell_kernel.f90:256-261 |
Module | exec |
nb instructions | 38 |
nb uops | 41 |
loop length | 255 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 10 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 5.00 |
micro-operation queue | 6.83 cycles |
front end | 6.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 8.33 | 8.33 | 8.33 | 4.00 | 4.00 | 5.00 | 5.00 | 7.00 | 7.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 15.00 | 15.00 | 15.00 | 8.00 | 8.00 | 10.00 | 10.00 | 7.00 | 7.00 |
Cycles executing div or sqrt instructions | 36.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 6.83 |
Dispatch | 15.00 |
DIV/SQRT | 36.00 |
Data deps. | 1.00 |
Overall L1 | 36.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 82% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 84% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R8,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPD (%R15,%RAX,1),%ZMM2,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM10,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM9,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R15,%RAX,1),%ZMM0,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%R9,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM9,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VSUBPD (%R10,%RAX,1),%ZMM1,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%RCX,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVQ %XMM3,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VADDPD (%RSI,%RAX,1),%ZMM6,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%RCX,%RAX,1),%ZMM15,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VFMADD132PD (%RDI,%RAX,1),%ZMM13,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VMOVQ %XMM10,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VDIVPD %ZMM14,%ZMM1,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM11,%ZMM14,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMOVUPD %ZMM5,(%R8,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM2,(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R8,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPD 0x40(%R15,%RAX,1),%ZMM6,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%RCX,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%R15,%RAX,1),%ZMM15,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%R9,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%RDX,%RAX,1),%ZMM13,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0xa8(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VSUBPD 0x40(%R10,%RAX,1),%ZMM1,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVQ %XMM3,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VFMADD132PD 0x40(%RDI,%RAX,1),%ZMM0,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VSUBPD 0x40(%RDX,%RAX,1),%ZMM11,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%RSI,%RAX,1),%ZMM14,%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VDIVPD %ZMM5,%ZMM12,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM12,%ZMM1,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMOVUPD %ZMM2,0x40(%R8,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM6,0x40(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
SUB $-0x80,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RCX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 41abbc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x27cc> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source file and lines | advec_cell_kernel.f90:256-261 |
Module | exec |
nb instructions | 38 |
nb uops | 41 |
loop length | 255 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 10 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 5.00 |
micro-operation queue | 6.83 cycles |
front end | 6.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 8.33 | 8.33 | 8.33 | 4.00 | 4.00 | 5.00 | 5.00 | 7.00 | 7.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 15.00 | 15.00 | 15.00 | 8.00 | 8.00 | 10.00 | 10.00 | 7.00 | 7.00 |
Cycles executing div or sqrt instructions | 36.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 6.83 |
Dispatch | 15.00 |
DIV/SQRT | 36.00 |
Data deps. | 1.00 |
Overall L1 | 36.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 82% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 84% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R8,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPD (%R15,%RAX,1),%ZMM2,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM10,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM9,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVUPD (%RDX,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R15,%RAX,1),%ZMM0,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%R9,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM9,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VSUBPD (%R10,%RAX,1),%ZMM1,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%RCX,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVQ %XMM3,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VADDPD (%RSI,%RAX,1),%ZMM6,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%RCX,%RAX,1),%ZMM15,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VFMADD132PD (%RDI,%RAX,1),%ZMM13,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VMOVQ %XMM10,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VDIVPD %ZMM14,%ZMM1,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM11,%ZMM14,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMOVUPD %ZMM5,(%R8,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM2,(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R8,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPD 0x40(%R15,%RAX,1),%ZMM6,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%RCX,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%R15,%RAX,1),%ZMM15,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%R9,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%RDX,%RAX,1),%ZMM13,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0xa8(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VSUBPD 0x40(%R10,%RAX,1),%ZMM1,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVQ %XMM3,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VFMADD132PD 0x40(%RDI,%RAX,1),%ZMM0,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VSUBPD 0x40(%RDX,%RAX,1),%ZMM11,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%RSI,%RAX,1),%ZMM14,%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VDIVPD %ZMM5,%ZMM12,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM12,%ZMM1,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMOVUPD %ZMM2,0x40(%R8,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM6,0x40(%RDI,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
SUB $-0x80,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RCX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 41abbc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x27cc> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |