Loop Id: 228 | Module: exec | Source: advec_cell_kernel.f90:164-170 | Coverage: 2.72% |
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Loop Id: 228 | Module: exec | Source: advec_cell_kernel.f90:164-170 | Coverage: 2.72% |
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0x42fca0 VMOVUPD (%RSI,%R8,8),%ZMM11 [5] |
0x42fca7 VMULPD (%R12,%R8,8),%ZMM11,%ZMM12 [1] |
0x42fcae VADDPD -0x8(%RCX,%R8,8),%ZMM12,%ZMM13 [3] |
0x42fcb9 VSUBPD (%RCX,%R8,8),%ZMM13,%ZMM13 [3] |
0x42fcc0 VMOVUPD (%R13,%R8,8),%ZMM14 [2] |
0x42fcc8 VFMADD213PD -0x8(%R9,%R8,8),%ZMM12,%ZMM14 [4] |
0x42fcd3 VSUBPD (%R9,%R8,8),%ZMM14,%ZMM12 [4] |
0x42fcda VDIVPD %ZMM13,%ZMM12,%ZMM12 |
0x42fce0 VADDPD -0x8(%RDX,%R8,8),%ZMM11,%ZMM11 [6] |
0x42fceb VSUBPD (%RDX,%R8,8),%ZMM11,%ZMM11 [6] |
0x42fcf2 VDIVPD %ZMM11,%ZMM13,%ZMM11 |
0x42fcf8 VMOVUPD %ZMM11,(%R12,%R8,8) [1] |
0x42fcff VMOVUPD %ZMM12,(%R13,%R8,8) [2] |
0x42fd07 ADD $0x8,%R8 |
0x42fd0b CMP %RBX,%R8 |
0x42fd0e JB 42fca0 |
/scratch_na/users/xoserete/qaas_runs/171-419-3245/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 164 - 170 |
-------------------------------------------------------------------------------- |
164: DO j=x_min,x_max |
165: pre_mass_s=density1(j,k)*pre_vol(j,k) |
166: post_mass_s=pre_mass_s+mass_flux_x(j,k)-mass_flux_x(j+1,k) |
167: post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j+1,k))/post_mass_s |
168: advec_vol_s=pre_vol(j,k)+vol_flux_x(j,k)-vol_flux_x(j+1,k) |
169: density1(j,k)=post_mass_s/advec_vol_s |
170: energy1(j,k)=post_ener_s |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 4.92 |
Bottlenecks | P0, |
Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_cell_kernel.f90:164-170 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 |
CQA cycles if no scalar integer | 32.00 |
CQA cycles if FP arith vectorized | 32.00 |
CQA cycles if fully vectorized | 32.00 |
Front-end cycles | 4.33 |
DIV/SQRT cycles | 6.50 |
P0 cycles | 3.50 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 1.00 |
P4 cycles | 6.50 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 0.00 |
P10 cycles | 3.00 |
P11 cycles | 32.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 32.29 - 32.31 |
Stall cycles (UFS) | 27.11 - 27.13 |
Nb insns | 16.00 |
Nb uops | 19.00 |
Nb loads | 9.00 |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.50 |
Nb FLOP add-sub | 40.00 |
Nb FLOP mul | 8.00 |
Nb FLOP fma | 8.00 |
Nb FLOP div | 16.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 22.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 576.00 |
Bytes stored | 128.00 |
Stride 0 | 0.00 |
Stride 1 | 3.00 |
Stride n | 3.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 4.92 |
Bottlenecks | P0, |
Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_cell_kernel.f90:164-170 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 |
CQA cycles if no scalar integer | 32.00 |
CQA cycles if FP arith vectorized | 32.00 |
CQA cycles if fully vectorized | 32.00 |
Front-end cycles | 4.33 |
DIV/SQRT cycles | 6.50 |
P0 cycles | 3.50 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 1.00 |
P4 cycles | 6.50 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 0.00 |
P10 cycles | 3.00 |
P11 cycles | 32.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 32.29 - 32.31 |
Stall cycles (UFS) | 27.11 - 27.13 |
Nb insns | 16.00 |
Nb uops | 19.00 |
Nb loads | 9.00 |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.50 |
Nb FLOP add-sub | 40.00 |
Nb FLOP mul | 8.00 |
Nb FLOP fma | 8.00 |
Nb FLOP div | 16.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 22.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 576.00 |
Bytes stored | 128.00 |
Stride 0 | 0.00 |
Stride 1 | 3.00 |
Stride n | 3.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | NA |
Path / |
Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_cell_kernel.f90:164-170 |
Module | exec |
nb instructions | 16 |
nb uops | 19 |
loop length | 112 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 4 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 5.00 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.50 | 0.00 | 3.00 | 3.00 | 1.00 | 6.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
cycles | 6.50 | 3.50 | 3.00 | 3.00 | 1.00 | 6.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
Cycles executing div or sqrt instructions | 32.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 32.29-32.31 |
Stall cycles | 27.11-27.13 |
ROB full (events) | 28.34-28.36 |
RS full (events) | 0.15 |
Front-end | 4.33 |
Dispatch | 6.50 |
DIV/SQRT | 32.00 |
Data deps. | 1.00 |
Overall L1 | 32.00 |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%RSI,%R8,8),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMULPD (%R12,%R8,8),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD -0x8(%RCX,%R8,8),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD (%RCX,%R8,8),%ZMM13,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD (%R13,%R8,8),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFMADD213PD -0x8(%R9,%R8,8),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSUBPD (%R9,%R8,8),%ZMM14,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD %ZMM13,%ZMM12,%ZMM12 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VADDPD -0x8(%RDX,%R8,8),%ZMM11,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD (%RDX,%R8,8),%ZMM11,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD %ZMM11,%ZMM13,%ZMM11 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VMOVUPD %ZMM11,(%R12,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD %ZMM12,(%R13,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RBX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42fca0 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0xe60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_cell_kernel.f90:164-170 |
Module | exec |
nb instructions | 16 |
nb uops | 19 |
loop length | 112 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 4 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 5.00 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.50 | 0.00 | 3.00 | 3.00 | 1.00 | 6.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
cycles | 6.50 | 3.50 | 3.00 | 3.00 | 1.00 | 6.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
Cycles executing div or sqrt instructions | 32.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 32.29-32.31 |
Stall cycles | 27.11-27.13 |
ROB full (events) | 28.34-28.36 |
RS full (events) | 0.15 |
Front-end | 4.33 |
Dispatch | 6.50 |
DIV/SQRT | 32.00 |
Data deps. | 1.00 |
Overall L1 | 32.00 |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%RSI,%R8,8),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMULPD (%R12,%R8,8),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD -0x8(%RCX,%R8,8),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD (%RCX,%R8,8),%ZMM13,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD (%R13,%R8,8),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFMADD213PD -0x8(%R9,%R8,8),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSUBPD (%R9,%R8,8),%ZMM14,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD %ZMM13,%ZMM12,%ZMM12 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VADDPD -0x8(%RDX,%R8,8),%ZMM11,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD (%RDX,%R8,8),%ZMM11,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD %ZMM11,%ZMM13,%ZMM11 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VMOVUPD %ZMM11,(%R12,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD %ZMM12,(%R13,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RBX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42fca0 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0xe60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |