Function: field_summary_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: field_summary_kernel.f90:54-74 | Coverage: 0.28% |
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Function: field_summary_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: field_summary_kernel.f90:54-74 | Coverage: 0.28% |
---|
/scratch_na/users/xoserete/qaas_runs/171-419-3245/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 54 - 74 |
-------------------------------------------------------------------------------- |
54: !$OMP PARALLEL |
55: !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke) |
56: DO k=y_min,y_max |
57: !$OMP SIMD |
58: DO j=x_min,x_max |
59: vsqrd=0.0 |
60: DO kv=k,k+1 |
61: DO jv=j,j+1 |
62: vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2) |
63: ENDDO |
64: ENDDO |
65: cell_vol=volume(j,k) |
66: cell_mass=cell_vol*density0(j,k) |
67: vol=vol+cell_vol |
68: mass=mass+cell_mass |
69: ie=ie+cell_mass*energy0(j,k) |
70: ke=ke+cell_mass*0.5*vsqrd |
71: press=press+cell_vol*pressure(j,k) |
72: ENDDO |
73: ENDDO |
74: !$OMP END DO |
0x441980 PUSH %RBP |
0x441981 MOV %RSP,%RBP |
0x441984 PUSH %R15 |
0x441986 PUSH %R14 |
0x441988 PUSH %R13 |
0x44198a PUSH %R12 |
0x44198c PUSH %RBX |
0x44198d SUB $0x68,%RSP |
0x441991 MOV 0x70(%RBP),%EBX |
0x441994 MOV 0x68(%RBP),%EAX |
0x441997 SUB %EBX,%EAX |
0x441999 MOVL $0,-0x48(%RBP) |
0x4419a0 JS 442117 |
0x4419a6 MOV %R9,%R15 |
0x4419a9 MOV %RCX,%R14 |
0x4419ac MOV %RDI,-0x30(%RBP) |
0x4419b0 MOV (%RDI),%ESI |
0x4419b2 MOVL $0,-0x38(%RBP) |
0x4419b9 MOV %EAX,-0x34(%RBP) |
0x4419bc MOVL $0x1,-0x44(%RBP) |
0x4419c3 SUB $0x8,%RSP |
0x4419c7 LEA -0x44(%RBP),%RAX |
0x4419cb LEA -0x48(%RBP),%RCX |
0x4419cf LEA -0x38(%RBP),%R8 |
0x4419d3 LEA -0x34(%RBP),%R9 |
0x4419d7 MOV $0x74b290,%EDI |
0x4419dc MOV %ESI,-0x3c(%RBP) |
0x4419df MOV $0x22,%EDX |
0x4419e4 PUSH $0x1 |
0x4419e6 PUSH $0x1 |
0x4419e8 PUSH %RAX |
0x4419e9 CALL 4044c0 <__kmpc_for_static_init_4@plt> |
0x4419ee ADD $0x20,%RSP |
0x4419f2 MOV -0x38(%RBP),%R10D |
0x4419f6 MOV -0x34(%RBP),%EAX |
0x4419f9 VXORPD %XMM1,%XMM1,%XMM1 |
0x4419fd VXORPD %XMM2,%XMM2,%XMM2 |
0x441a01 VXORPD %XMM3,%XMM3,%XMM3 |
0x441a05 VXORPD %XMM0,%XMM0,%XMM0 |
0x441a09 VXORPD %XMM4,%XMM4,%XMM4 |
0x441a0d SUB %R10D,%EAX |
0x441a10 MOV %EAX,-0x40(%RBP) |
0x441a13 JAE 441b00 |
0x441a19 MOV 0x30(%RBP),%R15 |
0x441a1d MOV 0x28(%RBP),%R14 |
0x441a21 MOV 0x20(%RBP),%R12 |
0x441a25 MOV 0x18(%RBP),%RBX |
0x441a29 MOV 0x10(%RBP),%R13 |
0x441a2d VMOVSD %XMM4,-0x70(%RBP) |
0x441a32 VMOVSD %XMM0,-0x68(%RBP) |
0x441a37 VMOVSD %XMM3,-0x60(%RBP) |
0x441a3c VMOVSD %XMM2,-0x58(%RBP) |
0x441a41 VMOVSD %XMM1,-0x50(%RBP) |
0x441a46 MOV $0x74b2b0,%EDI |
0x441a4b MOV -0x3c(%RBP),%ESI |
0x441a4e VZEROUPPER |
0x441a51 CALL 4040b0 <__kmpc_for_static_fini@plt> |
0x441a56 MOV -0x30(%RBP),%RAX |
0x441a5a MOV (%RAX),%ESI |
0x441a5c SUB $0x8,%RSP |
0x441a60 LEA -0x70(%RBP),%R8 |
0x441a64 MOV $0x74b370,%EDI |
0x441a69 MOV $0x442140,%R9D |
0x441a6f MOV $0x5,%EDX |
0x441a74 MOV $0x28,%ECX |
0x441a79 PUSH $0x75233c |
0x441a7e CALL 4046b0 <__kmpc_reduce@plt> |
0x441a83 ADD $0x10,%RSP |
0x441a87 CMP $0x2,%EAX |
0x441a8a JGE 442080 |
0x441a90 CMP $0x1,%EAX |
0x441a93 MOV -0x30(%RBP),%RDI |
0x441a97 JNE 442117 |
0x441a9d VMOVSD -0x70(%RBP),%XMM0 |
0x441aa2 VADDSD (%R15),%XMM0,%XMM0 |
0x441aa7 VMOVSD %XMM0,(%R15) |
0x441aac VMOVSD -0x68(%RBP),%XMM0 |
0x441ab1 VADDSD (%R14),%XMM0,%XMM0 |
0x441ab6 VMOVSD %XMM0,(%R14) |
0x441abb VMOVSD -0x60(%RBP),%XMM0 |
0x441ac0 VADDSD (%R13),%XMM0,%XMM0 |
0x441ac6 VMOVSD %XMM0,(%R13) |
0x441acc VMOVSD -0x58(%RBP),%XMM0 |
0x441ad1 VADDSD (%R12),%XMM0,%XMM0 |
0x441ad7 VMOVSD %XMM0,(%R12) |
0x441add VMOVSD -0x50(%RBP),%XMM0 |
0x441ae2 VADDSD (%RBX),%XMM0,%XMM0 |
0x441ae6 VMOVSD %XMM0,(%RBX) |
0x441aea MOV (%RDI),%ESI |
0x441aec MOV $0x74b390,%EDI |
0x441af1 JMP 442109 |
0x441af6 NOPW %CS:(%RAX,%RAX,1) |
0x441b00 ADD %EBX,%R10D |
0x441b03 MOVSXD %R14D,%RAX |
0x441b06 MOV %RAX,-0x88(%RBP) |
0x441b0d MOVSXD %R15D,%R15 |
0x441b10 ADD $-0x2,%R15 |
0x441b14 VMOVDQA64 0xc63a2(%RIP),%ZMM5 |
0x441b1e VPBROADCASTQ 0xc7300(%RIP),%ZMM6 |
0x441b28 VBROADCASTSD 0xc72ee(%RIP),%ZMM7 |
0x441b32 XOR %ECX,%ECX |
0x441b34 MOV %R10,-0x80(%RBP) |
0x441b38 JMP 441c2a |
0x441b3d NOPL (%RAX) |
(334) 0x441b40 VEXTRACTF64X4 $0x1,%ZMM12,%YMM13 |
(334) 0x441b47 VADDPD %ZMM13,%ZMM12,%ZMM12 |
(334) 0x441b4d VMOVAPD %XMM12,%XMM13 |
(334) 0x441b52 VEXTRACTF128 $0x1,%YMM12,%XMM12 |
(334) 0x441b58 VADDPD %XMM12,%XMM13,%XMM12 |
(334) 0x441b5d VSHUFPD $0x1,%XMM12,%XMM12,%XMM13 |
(334) 0x441b63 VADDSD %XMM13,%XMM12,%XMM12 |
(334) 0x441b68 VADDSD %XMM3,%XMM12,%XMM3 |
(334) 0x441b6c VEXTRACTF64X4 $0x1,%ZMM11,%YMM12 |
(334) 0x441b73 VADDPD %ZMM12,%ZMM11,%ZMM11 |
(334) 0x441b79 VMOVAPD %XMM11,%XMM12 |
(334) 0x441b7e VEXTRACTF128 $0x1,%YMM11,%XMM11 |
(334) 0x441b84 VADDPD %XMM11,%XMM12,%XMM11 |
(334) 0x441b89 VSHUFPD $0x1,%XMM11,%XMM11,%XMM12 |
(334) 0x441b8f VADDSD %XMM12,%XMM11,%XMM11 |
(334) 0x441b94 VADDSD %XMM1,%XMM11,%XMM1 |
(334) 0x441b98 VEXTRACTF64X4 $0x1,%ZMM10,%YMM11 |
(334) 0x441b9f VADDPD %ZMM11,%ZMM10,%ZMM10 |
(334) 0x441ba5 VMOVAPD %XMM10,%XMM11 |
(334) 0x441baa VEXTRACTF128 $0x1,%YMM10,%XMM10 |
(334) 0x441bb0 VADDPD %XMM10,%XMM11,%XMM10 |
(334) 0x441bb5 VSHUFPD $0x1,%XMM10,%XMM10,%XMM11 |
(334) 0x441bbb VADDSD %XMM11,%XMM10,%XMM10 |
(334) 0x441bc0 VADDSD %XMM2,%XMM10,%XMM2 |
(334) 0x441bc4 VEXTRACTF64X4 $0x1,%ZMM9,%YMM10 |
(334) 0x441bcb VADDPD %ZMM10,%ZMM9,%ZMM9 |
(334) 0x441bd1 VMOVAPD %XMM9,%XMM10 |
(334) 0x441bd6 VEXTRACTF128 $0x1,%YMM9,%XMM9 |
(334) 0x441bdc VADDPD %XMM9,%XMM10,%XMM9 |
(334) 0x441be1 VSHUFPD $0x1,%XMM9,%XMM9,%XMM10 |
(334) 0x441be7 VADDSD %XMM10,%XMM9,%XMM9 |
(334) 0x441bec VADDSD %XMM0,%XMM9,%XMM0 |
(334) 0x441bf0 VEXTRACTF64X4 $0x1,%ZMM8,%YMM9 |
(334) 0x441bf7 VADDPD %ZMM9,%ZMM8,%ZMM8 |
(334) 0x441bfd VMOVAPD %XMM8,%XMM9 |
(334) 0x441c02 VEXTRACTF128 $0x1,%YMM8,%XMM8 |
(334) 0x441c08 VADDPD %XMM8,%XMM9,%XMM8 |
(334) 0x441c0d VSHUFPD $0x1,%XMM8,%XMM8,%XMM9 |
(334) 0x441c13 VADDSD %XMM9,%XMM8,%XMM8 |
(334) 0x441c18 VADDSD %XMM4,%XMM8,%XMM4 |
(334) 0x441c1c LEA 0x1(%RCX),%EAX |
(334) 0x441c1f CMP -0x40(%RBP),%ECX |
(334) 0x441c22 MOV %EAX,%ECX |
(334) 0x441c24 JE 441a19 |
(334) 0x441c2a MOV 0x80(%RBP),%RAX |
(334) 0x441c31 MOVSXD (%RAX),%R8 |
(334) 0x441c34 MOV 0x78(%RBP),%RAX |
(334) 0x441c38 MOV (%RAX),%EAX |
(334) 0x441c3a CMP %R8D,%EAX |
(334) 0x441c3d JS 441c1c |
(334) 0x441c3f MOV %RCX,-0x78(%RBP) |
(334) 0x441c43 ADD %R10D,%ECX |
(334) 0x441c46 MOV 0x88(%RBP),%RDX |
(334) 0x441c4d MOV (%RDX),%RDI |
(334) 0x441c50 MOV 0x90(%RBP),%RDX |
(334) 0x441c57 MOV (%RDX),%R9 |
(334) 0x441c5a SUB %R8D,%EAX |
(334) 0x441c5d INC %EAX |
(334) 0x441c5f CMP $0x2,%EAX |
(334) 0x441c62 MOV $0x1,%EDX |
(334) 0x441c67 CMOVL %EDX,%EAX |
(334) 0x441c6a MOVSXD %ECX,%RDX |
(334) 0x441c6d SUB -0x88(%RBP),%RDX |
(334) 0x441c74 LEA 0x2(%RDX),%RSI |
(334) 0x441c78 MOV %RDI,%R13 |
(334) 0x441c7b IMUL %RSI,%R13 |
(334) 0x441c7f MOV 0x40(%RBP),%RCX |
(334) 0x441c83 ADD %RCX,%R13 |
(334) 0x441c86 ADD $0x3,%RDX |
(334) 0x441c8a IMUL %RDX,%RDI |
(334) 0x441c8e IMUL %R9,%RDX |
(334) 0x441c92 IMUL %RSI,%R9 |
(334) 0x441c96 MOV 0x38(%RBP),%R11 |
(334) 0x441c9a ADD %R11,%R9 |
(334) 0x441c9d ADD %RCX,%RDI |
(334) 0x441ca0 ADD %R11,%RDX |
(334) 0x441ca3 MOV 0x98(%RBP),%RCX |
(334) 0x441caa MOV (%RCX),%R11 |
(334) 0x441cad IMUL %RSI,%R11 |
(334) 0x441cb1 ADD 0x60(%RBP),%R11 |
(334) 0x441cb5 MOV 0xa0(%RBP),%RCX |
(334) 0x441cbc MOV (%RCX),%R12 |
(334) 0x441cbf IMUL %RSI,%R12 |
(334) 0x441cc3 ADD 0x58(%RBP),%R12 |
(334) 0x441cc7 MOV 0xa8(%RBP),%RCX |
(334) 0x441cce MOV (%RCX),%R14 |
(334) 0x441cd1 IMUL %RSI,%R14 |
(334) 0x441cd5 ADD 0x50(%RBP),%R14 |
(334) 0x441cd9 MOV 0xb0(%RBP),%RCX |
(334) 0x441ce0 IMUL (%RCX),%RSI |
(334) 0x441ce4 ADD 0x48(%RBP),%RSI |
(334) 0x441ce8 CMP $0x8,%EAX |
(334) 0x441ceb JAE 441d00 |
(334) 0x441ced XOR %EBX,%EBX |
(334) 0x441cef MOV -0x78(%RBP),%RCX |
(334) 0x441cf3 JMP 441eff |
0x441cf8 NOPL (%RAX,%RAX,1) |
(334) 0x441d00 VMOVQ %R8,%XMM8 |
(334) 0x441d05 MOV %EAX,%EBX |
(334) 0x441d07 AND $0x7ffffff8,%EBX |
(334) 0x441d0d VXORPD %XMM12,%XMM12,%XMM12 |
(334) 0x441d12 VMOVDQA %XMM8,%XMM13 |
(334) 0x441d17 VXORPD %XMM11,%XMM11,%XMM11 |
(334) 0x441d1c VXORPD %XMM10,%XMM10,%XMM10 |
(334) 0x441d21 VXORPD %XMM9,%XMM9,%XMM9 |
(334) 0x441d26 VPXOR %XMM8,%XMM8,%XMM8 |
(334) 0x441d2b XOR %ECX,%ECX |
(334) 0x441d2d VMOVDQA64 %ZMM5,%ZMM14 |
(334) 0x441d33 NOPW %CS:(%RAX,%RAX,1) |
(335) 0x441d40 VMOVDQA %XMM14,%XMM15 |
(335) 0x441d45 VPADDQ %XMM13,%XMM14,%XMM15 |
(335) 0x441d4a VMOVQ %XMM15,%R10 |
(335) 0x441d4f SUB %R15,%R10 |
(335) 0x441d52 VMOVUPD (%R13,%R10,8),%ZMM15 |
(335) 0x441d5a VMOVUPD 0x8(%R13,%R10,8),%ZMM16 |
(335) 0x441d65 VMOVUPD (%R9,%R10,8),%ZMM17 |
(335) 0x441d6c VMOVUPD 0x8(%R9,%R10,8),%ZMM18 |
(335) 0x441d77 VMOVUPD (%RDI,%R10,8),%ZMM19 |
(335) 0x441d7e VMOVUPD 0x8(%RDI,%R10,8),%ZMM20 |
(335) 0x441d89 VMOVUPD (%RDX,%R10,8),%ZMM21 |
(335) 0x441d90 VMOVUPD (%R11,%R10,8),%ZMM22 |
(335) 0x441d97 VMULPD (%R12,%R10,8),%ZMM22,%ZMM23 |
(335) 0x441d9e VFMADD231PD (%R14,%R10,8),%ZMM23,%ZMM10 |
(335) 0x441da5 VMOVUPD 0x8(%RDX,%R10,8),%ZMM24 |
(335) 0x441db0 VFMADD231PD (%RSI,%R10,8),%ZMM22,%ZMM12 |
(335) 0x441db7 VMULPD %ZMM15,%ZMM15,%ZMM15 |
(335) 0x441dbd VFMADD213PD %ZMM15,%ZMM17,%ZMM17 |
(335) 0x441dc3 VFMADD231PD %ZMM16,%ZMM16,%ZMM17 |
(335) 0x441dc9 VFMADD231PD %ZMM18,%ZMM18,%ZMM17 |
(335) 0x441dcf VFMADD213PD %ZMM17,%ZMM19,%ZMM19 |
(335) 0x441dd5 VFMADD213PD %ZMM19,%ZMM21,%ZMM21 |
(335) 0x441ddb VFMADD231PD %ZMM20,%ZMM20,%ZMM21 |
(335) 0x441de1 VFMADD231PD %ZMM24,%ZMM24,%ZMM21 |
(335) 0x441de7 VADDPD %ZMM22,%ZMM8,%ZMM8 |
(335) 0x441ded VADDPD %ZMM23,%ZMM9,%ZMM9 |
(335) 0x441df3 VMULPD %ZMM21,%ZMM23,%ZMM15 |
(335) 0x441df9 VFMADD231PD %ZMM7,%ZMM15,%ZMM11 |
(335) 0x441dff VPADDQ %ZMM6,%ZMM14,%ZMM14 |
(335) 0x441e05 ADD $0x8,%RCX |
(335) 0x441e09 CMP %RBX,%RCX |
(335) 0x441e0c JB 441d40 |
(334) 0x441e12 VEXTRACTF64X4 $0x1,%ZMM12,%YMM13 |
(334) 0x441e19 VADDPD %ZMM13,%ZMM12,%ZMM12 |
(334) 0x441e1f VMOVAPD %XMM12,%XMM13 |
(334) 0x441e24 VEXTRACTF128 $0x1,%YMM12,%XMM12 |
(334) 0x441e2a VADDPD %XMM12,%XMM13,%XMM12 |
(334) 0x441e2f VSHUFPD $0x1,%XMM12,%XMM12,%XMM13 |
(334) 0x441e35 VADDSD %XMM13,%XMM12,%XMM12 |
(334) 0x441e3a VADDSD %XMM3,%XMM12,%XMM3 |
(334) 0x441e3e VEXTRACTF64X4 $0x1,%ZMM11,%YMM12 |
(334) 0x441e45 VADDPD %ZMM12,%ZMM11,%ZMM11 |
(334) 0x441e4b VMOVAPD %XMM11,%XMM12 |
(334) 0x441e50 VEXTRACTF128 $0x1,%YMM11,%XMM11 |
(334) 0x441e56 VADDPD %XMM11,%XMM12,%XMM11 |
(334) 0x441e5b VSHUFPD $0x1,%XMM11,%XMM11,%XMM12 |
(334) 0x441e61 VADDSD %XMM12,%XMM11,%XMM11 |
(334) 0x441e66 VADDSD %XMM1,%XMM11,%XMM1 |
(334) 0x441e6a VEXTRACTF64X4 $0x1,%ZMM10,%YMM11 |
(334) 0x441e71 VADDPD %ZMM11,%ZMM10,%ZMM10 |
(334) 0x441e77 VMOVAPD %XMM10,%XMM11 |
(334) 0x441e7c VEXTRACTF128 $0x1,%YMM10,%XMM10 |
(334) 0x441e82 VADDPD %XMM10,%XMM11,%XMM10 |
(334) 0x441e87 VSHUFPD $0x1,%XMM10,%XMM10,%XMM11 |
(334) 0x441e8d VADDSD %XMM11,%XMM10,%XMM10 |
(334) 0x441e92 VADDSD %XMM2,%XMM10,%XMM2 |
(334) 0x441e96 VEXTRACTF64X4 $0x1,%ZMM9,%YMM10 |
(334) 0x441e9d VADDPD %ZMM10,%ZMM9,%ZMM9 |
(334) 0x441ea3 VMOVAPD %XMM9,%XMM10 |
(334) 0x441ea8 VEXTRACTF128 $0x1,%YMM9,%XMM9 |
(334) 0x441eae VADDPD %XMM9,%XMM10,%XMM9 |
(334) 0x441eb3 VSHUFPD $0x1,%XMM9,%XMM9,%XMM10 |
(334) 0x441eb9 VADDSD %XMM10,%XMM9,%XMM9 |
(334) 0x441ebe VADDSD %XMM0,%XMM9,%XMM0 |
(334) 0x441ec2 VEXTRACTF64X4 $0x1,%ZMM8,%YMM9 |
(334) 0x441ec9 VADDPD %ZMM9,%ZMM8,%ZMM8 |
(334) 0x441ecf VMOVAPD %XMM8,%XMM9 |
(334) 0x441ed4 VEXTRACTF128 $0x1,%YMM8,%XMM8 |
(334) 0x441eda VADDPD %XMM8,%XMM9,%XMM8 |
(334) 0x441edf VSHUFPD $0x1,%XMM8,%XMM8,%XMM9 |
(334) 0x441ee5 VADDSD %XMM9,%XMM8,%XMM8 |
(334) 0x441eea VADDSD %XMM4,%XMM8,%XMM4 |
(334) 0x441eee CMP %RAX,%RBX |
(334) 0x441ef1 MOV -0x80(%RBP),%R10 |
(334) 0x441ef5 MOV -0x78(%RBP),%RCX |
(334) 0x441ef9 JE 441c1c |
(334) 0x441eff SUB %RBX,%RAX |
(334) 0x441f02 VPBROADCASTQ %RAX,%ZMM13 |
(334) 0x441f08 VXORPD %XMM12,%XMM12,%XMM12 |
(334) 0x441f0d ADD %RBX,%R8 |
(334) 0x441f10 VMOVQ %R8,%XMM14 |
(334) 0x441f15 VXORPD %XMM11,%XMM11,%XMM11 |
(334) 0x441f1a VXORPD %XMM10,%XMM10,%XMM10 |
(334) 0x441f1f VXORPD %XMM9,%XMM9,%XMM9 |
(334) 0x441f24 VXORPD %XMM8,%XMM8,%XMM8 |
(334) 0x441f29 VMOVDQA64 %ZMM5,%ZMM15 |
(334) 0x441f2f JMP 441f75 |
0x441f31 NOPW %CS:(%RAX,%RAX,1) |
(336) 0x441f40 VMOVAPD %ZMM16,%ZMM8{%K1} |
(336) 0x441f46 VMOVAPD %ZMM17,%ZMM9{%K1} |
(336) 0x441f4c VMOVAPD %ZMM18,%ZMM10{%K1} |
(336) 0x441f52 VMOVAPD %ZMM19,%ZMM11{%K1} |
(336) 0x441f58 VMOVAPD %ZMM20,%ZMM12{%K1} |
(336) 0x441f5e VPADDQ %ZMM6,%ZMM15,%ZMM15 |
(336) 0x441f64 VPCMPLTUQ %ZMM13,%ZMM15,%K0 |
(336) 0x441f6b KORTESTB %K0,%K0 |
(336) 0x441f6f JE 441b40 |
(336) 0x441f75 VPCMPLTUQ %ZMM13,%ZMM15,%K1 |
(336) 0x441f7c KORTESTB %K1,%K1 |
(336) 0x441f80 VXORPD %XMM16,%XMM16,%XMM16 |
(336) 0x441f86 VXORPD %XMM17,%XMM17,%XMM17 |
(336) 0x441f8c VXORPD %XMM18,%XMM18,%XMM18 |
(336) 0x441f92 VXORPD %XMM19,%XMM19,%XMM19 |
(336) 0x441f98 VXORPD %XMM20,%XMM20,%XMM20 |
(336) 0x441f9e JE 441f40 |
(336) 0x441fa0 VMOVDQA64 %XMM15,%XMM16 |
(336) 0x441fa6 VPADDQ %XMM15,%XMM14,%XMM16 |
(336) 0x441fac VMOVQ %XMM16,%RAX |
(336) 0x441fb2 SUB %R15,%RAX |
(336) 0x441fb5 VMOVUPD (%R13,%RAX,8),%ZMM16{%K1}{z} |
(336) 0x441fbd VMULPD %ZMM16,%ZMM16,%ZMM16 |
(336) 0x441fc3 VMOVUPD (%R9,%RAX,8),%ZMM17{%K1}{z} |
(336) 0x441fca VMOVUPD 0x8(%R13,%RAX,8),%ZMM18{%K1}{z} |
(336) 0x441fd5 VMOVUPD 0x8(%R9,%RAX,8),%ZMM19{%K1}{z} |
(336) 0x441fe0 VFMADD213PD %ZMM16,%ZMM17,%ZMM17 |
(336) 0x441fe6 VFMADD213PD %ZMM17,%ZMM18,%ZMM18 |
(336) 0x441fec VMOVUPD (%RDI,%RAX,8),%ZMM16{%K1}{z} |
(336) 0x441ff3 VMOVUPD (%RDX,%RAX,8),%ZMM17{%K1}{z} |
(336) 0x441ffa VFMADD231PD %ZMM19,%ZMM19,%ZMM18 |
(336) 0x442000 VFMADD213PD %ZMM18,%ZMM16,%ZMM16 |
(336) 0x442006 VMOVUPD 0x8(%RDI,%RAX,8),%ZMM19{%K1}{z} |
(336) 0x442011 VMOVUPD 0x8(%RDX,%RAX,8),%ZMM18{%K1}{z} |
(336) 0x44201c VFMADD231PD %ZMM17,%ZMM17,%ZMM16 |
(336) 0x442022 VFMADD213PD %ZMM16,%ZMM19,%ZMM19 |
(336) 0x442028 VMOVUPD (%R11,%RAX,8),%ZMM21{%K1}{z} |
(336) 0x44202f VMOVUPD (%R12,%RAX,8),%ZMM16{%K1}{z} |
(336) 0x442036 VFMADD231PD %ZMM18,%ZMM18,%ZMM19 |
(336) 0x44203c VMULPD %ZMM21,%ZMM16,%ZMM20 |
(336) 0x442042 VADDPD %ZMM21,%ZMM8,%ZMM16 |
(336) 0x442048 VADDPD %ZMM20,%ZMM9,%ZMM17 |
(336) 0x44204e VMOVUPD (%R14,%RAX,8),%ZMM18{%K1}{z} |
(336) 0x442055 VFMADD213PD %ZMM10,%ZMM20,%ZMM18 |
(336) 0x44205b VMULPD %ZMM19,%ZMM20,%ZMM19 |
(336) 0x442061 VFMADD132PD %ZMM7,%ZMM11,%ZMM19 |
(336) 0x442067 VMOVUPD (%RSI,%RAX,8),%ZMM20{%K1}{z} |
(336) 0x44206e VFMADD213PD %ZMM12,%ZMM21,%ZMM20 |
(336) 0x442074 JMP 441f40 |
0x442079 NOPL (%RAX) |
0x442080 MOV -0x30(%RBP),%RDI |
0x442084 JNE 442117 |
0x44208a VMOVSD -0x70(%RBP),%XMM0 |
0x44208f MOV (%RDI),%ESI |
0x442091 MOV $0x74b2d0,%EDI |
0x442096 MOV %R15,%RDX |
0x442099 CALL 4041a0 <__kmpc_atomic_float8_add@plt> |
0x44209e VMOVSD -0x68(%RBP),%XMM0 |
0x4420a3 MOV -0x30(%RBP),%RAX |
0x4420a7 MOV (%RAX),%ESI |
0x4420a9 MOV $0x74b2f0,%EDI |
0x4420ae MOV %R14,%RDX |
0x4420b1 CALL 4041a0 <__kmpc_atomic_float8_add@plt> |
0x4420b6 VMOVSD -0x60(%RBP),%XMM0 |
0x4420bb MOV -0x30(%RBP),%RAX |
0x4420bf MOV (%RAX),%ESI |
0x4420c1 MOV $0x74b310,%EDI |
0x4420c6 MOV %R13,%RDX |
0x4420c9 CALL 4041a0 <__kmpc_atomic_float8_add@plt> |
0x4420ce VMOVSD -0x58(%RBP),%XMM0 |
0x4420d3 MOV -0x30(%RBP),%RAX |
0x4420d7 MOV (%RAX),%ESI |
0x4420d9 MOV $0x74b330,%EDI |
0x4420de MOV %R12,%RDX |
0x4420e1 CALL 4041a0 <__kmpc_atomic_float8_add@plt> |
0x4420e6 VMOVSD -0x50(%RBP),%XMM0 |
0x4420eb MOV -0x30(%RBP),%RAX |
0x4420ef MOV (%RAX),%ESI |
0x4420f1 MOV $0x74b350,%EDI |
0x4420f6 MOV %RBX,%RDX |
0x4420f9 CALL 4041a0 <__kmpc_atomic_float8_add@plt> |
0x4420fe MOV -0x30(%RBP),%RAX |
0x442102 MOV (%RAX),%ESI |
0x442104 MOV $0x74b3b0,%EDI |
0x442109 MOV $0x75233c,%EDX |
0x44210e CALL 404820 <__kmpc_end_reduce@plt> |
0x442113 MOV -0x30(%RBP),%RDI |
0x442117 MOV (%RDI),%ESI |
0x442119 MOV $0x74b3d0,%EDI |
0x44211e CALL 404580 <__kmpc_barrier@plt> |
0x442123 ADD $0x68,%RSP |
0x442127 POP %RBX |
0x442128 POP %R12 |
0x44212a POP %R13 |
0x44212c POP %R14 |
0x44212e POP %R15 |
0x442130 POP %RBP |
0x442131 RET |
0x442132 NOPW %CS:(%RAX,%RAX,1) |
0x44213c NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Source file and lines | field_summary_kernel.f90:54-74 |
Module | exec |
nb instructions | 157 |
nb uops | 168 |
loop length | 670 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 3 |
nb stack references | 21 |
micro-operation queue | 28.00 cycles |
front end | 28.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.80 | 6.90 | 18.00 | 18.00 | 19.50 | 6.70 | 6.80 | 19.50 | 19.50 | 19.50 | 6.80 | 18.00 |
cycles | 6.80 | 6.90 | 18.00 | 18.00 | 19.50 | 6.70 | 6.80 | 19.50 | 19.50 | 19.50 | 6.80 | 18.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 26.29 |
Stall cycles | 0.00 |
Front-end | 28.00 |
Dispatch | 19.50 |
Overall L1 | 28.00 |
all | 5% |
load | 7% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 16% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 83% |
all | 10% |
load | 3% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 28% |
all | 10% |
load | 13% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 14% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 22% |
all | 12% |
load | 12% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 11% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x70(%RBP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVL $0,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 442117 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x797> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x44(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x48(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x38(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x34(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74b290,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4044c0 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x38(%RBP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x34(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R10D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 441b00 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x180> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x30(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM4,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM3,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x74b2b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x3c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4040b0 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x70(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74b370,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x442140,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x5,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x28,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x75233c | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4046b0 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x2,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 442080 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x700> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 442117 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x797> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD -0x70(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%R15),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%R15) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x68(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%R14),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x60(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%R13),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x58(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%R12),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x50(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%RBX),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%RBX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b390,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JMP 442109 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x789> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %EBX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R14D,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%R15 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD $-0x2,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQA64 0xc63a2(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VPBROADCASTQ 0xc7300(%RIP),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xc72ee(%RIP),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 441c2a <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x2aa> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 442117 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x797> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD -0x70(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b2d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4041a0 <__kmpc_atomic_float8_add@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x68(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b2f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4041a0 <__kmpc_atomic_float8_add@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x60(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b310,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R13,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4041a0 <__kmpc_atomic_float8_add@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x58(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b330,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4041a0 <__kmpc_atomic_float8_add@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x50(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b350,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4041a0 <__kmpc_atomic_float8_add@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b3b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x75233c,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404820 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b3d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404580 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | field_summary_kernel.f90:54-74 |
Module | exec |
nb instructions | 157 |
nb uops | 168 |
loop length | 670 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 3 |
nb stack references | 21 |
micro-operation queue | 28.00 cycles |
front end | 28.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.80 | 6.90 | 18.00 | 18.00 | 19.50 | 6.70 | 6.80 | 19.50 | 19.50 | 19.50 | 6.80 | 18.00 |
cycles | 6.80 | 6.90 | 18.00 | 18.00 | 19.50 | 6.70 | 6.80 | 19.50 | 19.50 | 19.50 | 6.80 | 18.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 26.29 |
Stall cycles | 0.00 |
Front-end | 28.00 |
Dispatch | 19.50 |
Overall L1 | 28.00 |
all | 5% |
load | 7% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 16% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 83% |
all | 10% |
load | 3% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 28% |
all | 10% |
load | 13% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 14% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 22% |
all | 12% |
load | 12% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 11% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x70(%RBP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVL $0,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 442117 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x797> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x44(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x48(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x38(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x34(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74b290,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4044c0 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x38(%RBP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x34(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R10D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 441b00 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x180> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x30(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM4,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM3,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x74b2b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x3c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4040b0 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x70(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74b370,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x442140,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x5,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x28,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x75233c | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4046b0 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x2,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 442080 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x700> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 442117 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x797> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD -0x70(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%R15),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%R15) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x68(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%R14),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x60(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%R13),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x58(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%R12),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x50(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%RBX),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%RBX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b390,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JMP 442109 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x789> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %EBX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R14D,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%R15 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD $-0x2,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVDQA64 0xc63a2(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VPBROADCASTQ 0xc7300(%RIP),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xc72ee(%RIP),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 441c2a <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x2aa> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 442117 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x797> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD -0x70(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b2d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4041a0 <__kmpc_atomic_float8_add@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x68(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b2f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4041a0 <__kmpc_atomic_float8_add@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x60(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b310,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R13,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4041a0 <__kmpc_atomic_float8_add@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x58(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b330,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4041a0 <__kmpc_atomic_float8_add@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x50(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b350,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4041a0 <__kmpc_atomic_float8_add@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b3b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x75233c,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404820 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b3d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404580 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼field_summary_kernel_.DIR.OMP.PARALLEL.2– | 0.28 | 0.09 |
▼Loop 334 - field_summary_kernel.f90:56-71 - exec– | 0 | 0 |
○Loop 335 - field_summary_kernel.f90:58-71 - exec | 0.28 | 0.09 |
○Loop 336 - field_summary_kernel.f90:58-71 - exec | 0 | 0 |