Function: calc_dt_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: calc_dt_kernel.f90:89-133 [...] | Coverage: 4.9% |
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Function: calc_dt_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: calc_dt_kernel.f90:89-133 [...] | Coverage: 4.9% |
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/home/eoseret/qaas_runs_CPU_9468/171-137-7698/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 133 |
-------------------------------------------------------------------------------- |
89: !$OMP PARALLEL |
90: |
91: !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val) |
92: DO k=y_min,y_max |
93: !$OMP SIMD |
94: DO j=x_min,x_max |
95: |
96: dsx=celldx(j) |
97: dsy=celldy(k) |
98: |
99: cc=soundspeed(j,k)*soundspeed(j,k) |
100: cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k) |
101: cc=MAX(SQRT(cc),g_small) |
102: |
103: dtct=dtc_safe*MIN(dsx,dsy)/cc |
104: |
105: div=0.0 |
106: |
107: dv1=(xvel0(j ,k)+xvel0(j ,k+1))*xarea(j ,k) |
108: dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k) |
109: |
110: div=div+dv2-dv1 |
111: |
112: dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
113: |
114: dv1=(yvel0(j,k )+yvel0(j+1,k ))*yarea(j,k ) |
115: dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1) |
116: |
117: div=div+dv2-dv1 |
118: |
119: dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
120: |
121: div=div/(2.0_8*volume(j,k)) |
122: |
123: IF(div.LT.-g_small)THEN |
[...] |
129: dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt) |
130: |
131: ENDDO |
132: ENDDO |
133: !$OMP END DO |
0x43edc0 PUSH %RBP |
0x43edc1 MOV %RSP,%RBP |
0x43edc4 PUSH %R15 |
0x43edc6 PUSH %R14 |
0x43edc8 PUSH %R13 |
0x43edca PUSH %R12 |
0x43edcc PUSH %RBX |
0x43edcd AND $-0x40,%RSP |
0x43edd1 SUB $0x400,%RSP |
0x43edd8 MOV 0x90(%RBP),%ESI |
0x43edde MOV 0x88(%RBP),%EAX |
0x43ede4 SUB %ESI,%EAX |
0x43ede6 MOVL $0,0x4c(%RSP) |
0x43edee JS 43face |
0x43edf4 MOV %R8,0x90(%RSP) |
0x43edfc MOV %RCX,%R12 |
0x43edff MOV %RDX,%R15 |
0x43ee02 MOV %R9,%R13 |
0x43ee05 MOV %RDI,0x50(%RSP) |
0x43ee0a MOV (%RDI),%ESI |
0x43ee0c MOVL $0,0x3c(%RSP) |
0x43ee14 MOV %EAX,0x38(%RSP) |
0x43ee18 MOVL $0x1,0x48(%RSP) |
0x43ee20 SUB $0x8,%RSP |
0x43ee24 LEA 0x50(%RSP),%RAX |
0x43ee29 LEA 0x54(%RSP),%RCX |
0x43ee2e LEA 0x44(%RSP),%R8 |
0x43ee33 LEA 0x40(%RSP),%R9 |
0x43ee38 MOV $0x54d0b0,%EDI |
0x43ee3d MOV %ESI,0x48(%RSP) |
0x43ee41 MOV $0x22,%EDX |
0x43ee46 PUSH $0x1 |
0x43ee48 PUSH $0x1 |
0x43ee4a PUSH %RAX |
0x43ee4b CALL 404670 <__kmpc_for_static_init_4@plt> |
0x43ee50 ADD $0x20,%RSP |
0x43ee54 MOV 0x3c(%RSP),%EAX |
0x43ee58 MOV 0x38(%RSP),%ECX |
0x43ee5c MOV %RAX,0x58(%RSP) |
0x43ee61 SUB %EAX,%ECX |
0x43ee63 MOV %ECX,0x44(%RSP) |
0x43ee67 JAE 43ee80 |
0x43ee69 VMOVSD 0xcc857(%RIP),%XMM0 |
0x43ee71 JMP 43fa47 |
0x43ee76 NOPW %CS:(%RAX,%RAX,1) |
0x43ee80 MOV 0x48(%RBP),%R9 |
0x43ee84 MOV 0x30(%RBP),%R11 |
0x43ee88 MOV 0x28(%RBP),%R10 |
0x43ee8c SAL $0x20,%R12 |
0x43ee90 MOV $-0x200000000,%RCX |
0x43ee9a LEA (%R12,%RCX,1),%RDI |
0x43ee9e MOV %RDI,%RAX |
0x43eea1 SAR $0x20,%RAX |
0x43eea5 MOV %RAX,0xa0(%RSP) |
0x43eead SAL $0x20,%R15 |
0x43eeb1 ADD %R15,%RCX |
0x43eeb4 MOV %RCX,%R14 |
0x43eeb7 SAR $0x20,%R14 |
0x43eebb TEST %RDI,%RDI |
0x43eebe MOV $-0x1,%R8 |
0x43eec5 CMOVNS %RDI,%R8 |
0x43eec9 TEST %R8,%R8 |
0x43eecc MOV $0x1,%ESI |
0x43eed1 CMOVG %RSI,%R8 |
0x43eed5 MOV $0x200000000,%RBX |
0x43eedf MOV %RBX,%RAX |
0x43eee2 SUB %R12,%RAX |
0x43eee5 MOV $-0x1,%RDX |
0x43eeec CMP %RAX,%RDI |
0x43eeef CMOVG %RDI,%RAX |
0x43eef3 SHR $0x20,%RAX |
0x43eef7 IMUL %R8,%RAX |
0x43eefb SAL $0x3,%RAX |
0x43eeff MOV $0x8,%EDI |
0x43ef04 SUB %RAX,%RDI |
0x43ef07 MOV $0x1,%R8D |
0x43ef0d MOV %R14,0x120(%RSP) |
0x43ef15 SUB %R14,%R8 |
0x43ef18 MOV %R8,0xe8(%RSP) |
0x43ef20 TEST %RCX,%RCX |
0x43ef23 CMOVNS %RCX,%RDX |
0x43ef27 TEST %RDX,%RDX |
0x43ef2a CMOVG %RSI,%RDX |
0x43ef2e MOV 0x20(%RBP),%RSI |
0x43ef32 SUB %R15,%RBX |
0x43ef35 CMP %RBX,%RCX |
0x43ef38 CMOVG %RCX,%RBX |
0x43ef3c SHR $0x20,%RBX |
0x43ef40 IMUL %RDX,%RBX |
0x43ef44 MOV %R9,%RCX |
0x43ef47 SUB %RAX,%RCX |
0x43ef4a MOV %RCX,0xe0(%RSP) |
0x43ef52 SUB %RAX,%R11 |
0x43ef55 MOV %R11,0xd8(%RSP) |
0x43ef5d SUB %RAX,%R10 |
0x43ef60 MOV %R10,0xd0(%RSP) |
0x43ef68 SUB %RAX,%RSI |
0x43ef6b MOV %RSI,0xc8(%RSP) |
0x43ef73 MOV 0x18(%RBP),%RCX |
0x43ef77 SUB %RAX,%RCX |
0x43ef7a MOV %RCX,0xc0(%RSP) |
0x43ef82 MOV 0x40(%RBP),%RCX |
0x43ef86 SUB %RAX,%RCX |
0x43ef89 MOV %RCX,0xb8(%RSP) |
0x43ef91 NEG %RBX |
0x43ef94 MOV %RBX,0xf8(%RSP) |
0x43ef9c MOV 0x50(%RBP),%RAX |
0x43efa0 MOV %R13,0x98(%RSP) |
0x43efa8 LEA (%R13,%RDI,1),%RCX |
0x43efad MOV %RCX,0xb0(%RSP) |
0x43efb5 ADD %RDI,%RAX |
0x43efb8 MOV %RAX,0xa8(%RSP) |
0x43efc0 ADD 0x10(%RBP),%RDI |
0x43efc4 MOV %RDI,0xf0(%RSP) |
0x43efcc VMOVDDUP 0xcc6f2(%RIP),%XMM28 |
0x43efd6 VBROADCASTSD 0xcc698(%RIP),%ZMM2 |
0x43efe0 VBROADCASTSD 0xcc656(%RIP),%ZMM3 |
0x43efea VBROADCASTSD 0xcc6dc(%RIP),%ZMM4 |
0x43eff4 VBROADCASTSD 0xcc6da(%RIP),%ZMM5 |
0x43effe MOV 0x90(%RBP),%EAX |
0x43f004 MOV 0x58(%RSP),%RCX |
0x43f009 LEA (%RCX,%RAX,1),%R15D |
0x43f00d XOR %R12D,%R12D |
0x43f010 JMP 43f066 |
0x43f012 NOPW %CS:(%RAX,%RAX,1) |
0x43f021 NOPW %CS:(%RAX,%RAX,1) |
0x43f030 NOPW %CS:(%RAX,%RAX,1) |
0x43f03f NOP |
(322) 0x43f040 VMOVDDUP %XMM28,%XMM28 |
(322) 0x43f046 MOV 0x34(%RSP),%R15D |
(322) 0x43f04b MOV 0x60(%RSP),%R12 |
(322) 0x43f050 LEA 0x1(%R12),%EAX |
(322) 0x43f055 INC %R15D |
(322) 0x43f058 CMP 0x44(%RSP),%R12D |
(322) 0x43f05d MOV %EAX,%R12D |
(322) 0x43f060 JE 43fa40 |
(322) 0x43f066 MOV 0xa0(%RBP),%RAX |
(322) 0x43f06d MOVSXD (%RAX),%R11 |
(322) 0x43f070 MOV 0x98(%RBP),%RAX |
(322) 0x43f077 MOV (%RAX),%ESI |
(322) 0x43f079 CMP %R11D,%ESI |
(322) 0x43f07c JS 43f050 |
(322) 0x43f07e MOV %R15D,%EDX |
(322) 0x43f081 MOV 0x90(%RBP),%EAX |
(322) 0x43f087 MOV 0x58(%RSP),%RCX |
(322) 0x43f08c ADD %ECX,%EAX |
(322) 0x43f08e ADD %R12D,%EAX |
(322) 0x43f091 MOVSXD %EAX,%RCX |
(322) 0x43f094 SUB 0x120(%RSP),%RCX |
(322) 0x43f09c MOV 0x38(%RBP),%RAX |
(322) 0x43f0a0 VMOVSD (%RAX,%RCX,8),%XMM23 |
(322) 0x43f0a7 MOV 0xa8(%RBP),%RAX |
(322) 0x43f0ae MOV (%RAX),%R15 |
(322) 0x43f0b1 MOV 0xb0(%RBP),%RAX |
(322) 0x43f0b8 MOV (%RAX),%R14 |
(322) 0x43f0bb MOV 0xb8(%RBP),%RAX |
(322) 0x43f0c2 MOV (%RAX),%R10 |
(322) 0x43f0c5 VMOVSD 0x115ca1(%RIP),%XMM25 |
(322) 0x43f0cf MOV 0xc0(%RBP),%RAX |
(322) 0x43f0d6 MOV (%RAX),%RBX |
(322) 0x43f0d9 MOV 0xc8(%RBP),%RAX |
(322) 0x43f0e0 MOV (%RAX),%R13 |
(322) 0x43f0e3 VMOVSD 0x115c7b(%RIP),%XMM24 |
(322) 0x43f0ed MOV 0xd0(%RBP),%RAX |
(322) 0x43f0f4 MOV (%RAX),%RDI |
(322) 0x43f0f7 MOV 0xd8(%RBP),%RAX |
(322) 0x43f0fe MOV (%RAX),%R8 |
(322) 0x43f101 MOV 0xe0(%RBP),%RAX |
(322) 0x43f108 MOV (%RAX),%R9 |
(322) 0x43f10b VMOVSD 0x115c4b(%RIP),%XMM26 |
(322) 0x43f115 VMOVSD 0x115c3b(%RIP),%XMM0 |
(322) 0x43f11d VXORPD 0xcc591(%RIP){1to2},%XMM0,%XMM27 |
(322) 0x43f127 SUB %R11D,%ESI |
(322) 0x43f12a INC %ESI |
(322) 0x43f12c CMP $0x2,%ESI |
(322) 0x43f12f MOV $0x1,%EAX |
(322) 0x43f134 CMOVL %EAX,%ESI |
(322) 0x43f137 MOV %RSI,%RAX |
(322) 0x43f13a AND $0x7ffffff8,%RSI |
(322) 0x43f141 MOV %R10,0x80(%RSP) |
(322) 0x43f149 MOV %RBX,0x138(%RSP) |
(322) 0x43f151 MOV %R11,0x130(%RSP) |
(322) 0x43f159 JE 43f580 |
(322) 0x43f15f MOV %RAX,0x128(%RSP) |
(322) 0x43f167 MOV %RCX,0x110(%RSP) |
(322) 0x43f16f MOV %R12,0x60(%RSP) |
(322) 0x43f174 MOV %EDX,0x34(%RSP) |
(322) 0x43f178 MOVSXD %EDX,%RAX |
(322) 0x43f17b MOV 0xe8(%RSP),%RCX |
(322) 0x43f183 ADD %RAX,%RCX |
(322) 0x43f186 ADD 0xf8(%RSP),%RAX |
(322) 0x43f18e VBROADCASTSD %XMM28,%ZMM28 |
(322) 0x43f194 MOV %R8,%RDX |
(322) 0x43f197 IMUL %RCX,%RDX |
(322) 0x43f19b MOV %R15,0x70(%RSP) |
(322) 0x43f1a0 LEA (%RDX,%R11,8),%R12 |
(322) 0x43f1a4 MOV %RDI,0x68(%RSP) |
(322) 0x43f1a9 MOV 0xb0(%RSP),%RDI |
(322) 0x43f1b1 ADD %RDI,%R12 |
(322) 0x43f1b4 MOV %R8,0x108(%RSP) |
(322) 0x43f1bc MOV %R8,%RDX |
(322) 0x43f1bf IMUL %RAX,%RDX |
(322) 0x43f1c3 MOV %R14,0x78(%RSP) |
(322) 0x43f1c8 LEA (%RDX,%R11,8),%R15 |
(322) 0x43f1cc ADD %RDI,%R15 |
(322) 0x43f1cf MOV %R13,0x100(%RSP) |
(322) 0x43f1d7 IMUL %RAX,%R13 |
(322) 0x43f1db LEA (%R13,%R11,8),%R14 |
(322) 0x43f1e0 ADD 0xa8(%RSP),%R14 |
(322) 0x43f1e8 MOV %RBX,%RDX |
(322) 0x43f1eb IMUL %RAX,%RDX |
(322) 0x43f1ef LEA (%RDX,%R11,8),%R10 |
(322) 0x43f1f3 MOV 0xf0(%RSP),%RDI |
(322) 0x43f1fb ADD %RDI,%R10 |
(322) 0x43f1fe IMUL %RCX,%RBX |
(322) 0x43f202 LEA (%RBX,%R11,8),%RBX |
(322) 0x43f206 ADD %RDI,%RBX |
(322) 0x43f209 IMUL %R9,%RCX |
(322) 0x43f20d LEA (%RCX,%R11,8),%R8 |
(322) 0x43f211 MOV 0xe0(%RSP),%RDX |
(322) 0x43f219 ADD %RDX,%R8 |
(322) 0x43f21c MOV %R9,0x118(%RSP) |
(322) 0x43f224 IMUL %RAX,%R9 |
(322) 0x43f228 LEA (%R9,%R11,8),%R13 |
(322) 0x43f22c ADD %RDX,%R13 |
(322) 0x43f22f MOV 0x68(%RSP),%RCX |
(322) 0x43f234 IMUL %RAX,%RCX |
(322) 0x43f238 LEA (%RCX,%R11,8),%R9 |
(322) 0x43f23c ADD 0xd8(%RSP),%R9 |
(322) 0x43f244 MOV 0x80(%RSP),%RCX |
(322) 0x43f24c IMUL %RAX,%RCX |
(322) 0x43f250 LEA (%RCX,%R11,8),%RDI |
(322) 0x43f254 ADD 0xd0(%RSP),%RDI |
(322) 0x43f25c MOV 0x78(%RSP),%RCX |
(322) 0x43f261 IMUL %RAX,%RCX |
(322) 0x43f265 LEA (%RCX,%R11,8),%RDX |
(322) 0x43f269 ADD 0xc8(%RSP),%RDX |
(322) 0x43f271 IMUL 0x70(%RSP),%RAX |
(322) 0x43f277 LEA (%RAX,%R11,8),%RAX |
(322) 0x43f27b ADD 0xc0(%RSP),%RAX |
(322) 0x43f283 MOV 0xb8(%RSP),%RCX |
(322) 0x43f28b LEA (%RCX,%R11,8),%R11 |
(322) 0x43f28f VBROADCASTSD %XMM23,%ZMM29 |
(322) 0x43f295 VBROADCASTSD %XMM25,%ZMM30 |
(322) 0x43f29b VBROADCASTSD %XMM24,%ZMM31 |
(322) 0x43f2a1 VBROADCASTSD %XMM26,%ZMM1 |
(322) 0x43f2a7 VBROADCASTSD %XMM27,%ZMM0 |
(322) 0x43f2ad XOR %ECX,%ECX |
(322) 0x43f2af NOP |
(323) 0x43f2b0 VMOVUPD (%R11,%RCX,8),%ZMM6 |
(323) 0x43f2b7 VMINPD %ZMM29,%ZMM6,%ZMM6 |
(323) 0x43f2bd VMOVUPD (%RDX,%RCX,8),%ZMM7 |
(323) 0x43f2c4 VADDPD %ZMM7,%ZMM7,%ZMM7 |
(323) 0x43f2ca VDIVPD (%RDI,%RCX,8),%ZMM7,%ZMM7 |
(323) 0x43f2d1 VMULPD %ZMM6,%ZMM30,%ZMM6 |
(323) 0x43f2d7 VMOVUPD (%RAX,%RCX,8),%ZMM8 |
(323) 0x43f2de VFMADD231PD %ZMM8,%ZMM8,%ZMM7 |
(323) 0x43f2e4 VSQRTPD %ZMM7,%ZMM7 |
(323) 0x43f2ea VMAXPD %ZMM2,%ZMM7,%ZMM7 |
(323) 0x43f2f0 VDIVPD %ZMM7,%ZMM6,%ZMM6 |
(323) 0x43f2f6 VMOVUPD -0x8(%RBX,%RCX,8),%ZMM7 |
(323) 0x43f301 VMOVUPD (%RBX,%RCX,8),%ZMM8 |
(323) 0x43f308 VADDPD -0x8(%R10,%RCX,8),%ZMM7,%ZMM7 |
(323) 0x43f313 VMULPD -0x8(%R14,%RCX,8),%ZMM7,%ZMM7 |
(323) 0x43f31e VADDPD (%R10,%RCX,8),%ZMM8,%ZMM8 |
(323) 0x43f325 VMULPD (%R14,%RCX,8),%ZMM8,%ZMM8 |
(323) 0x43f32c VMOVUPD (%R9,%RCX,8),%ZMM9 |
(323) 0x43f333 VADDPD %ZMM9,%ZMM9,%ZMM10 |
(323) 0x43f339 VMULPD %ZMM31,%ZMM10,%ZMM11 |
(323) 0x43f33f VANDPD %ZMM3,%ZMM7,%ZMM12 |
(323) 0x43f345 VANDPD %ZMM3,%ZMM8,%ZMM13 |
(323) 0x43f34b VMULPD %ZMM2,%ZMM9,%ZMM9 |
(323) 0x43f351 VCMPPD $0x2,%ZMM13,%ZMM9,%K1 |
(323) 0x43f358 VBLENDMPD %ZMM13,%ZMM9,%ZMM13{%K1} |
(323) 0x43f35e VCMPPD $0x2,%ZMM12,%ZMM13,%K1 |
(323) 0x43f365 VMOVAPD %ZMM12,%ZMM13{%K1} |
(323) 0x43f36b VDIVPD %ZMM13,%ZMM11,%ZMM11 |
(323) 0x43f371 VMOVUPD (%R15,%RCX,8),%ZMM12 |
(323) 0x43f378 VADDPD -0x8(%R15,%RCX,8),%ZMM12,%ZMM12 |
(323) 0x43f383 VMULPD (%R13,%RCX,8),%ZMM12,%ZMM12 |
(323) 0x43f38b VMOVUPD (%R12,%RCX,8),%ZMM13 |
(323) 0x43f392 VADDPD -0x8(%R12,%RCX,8),%ZMM13,%ZMM13 |
(323) 0x43f39d VMULPD (%R8,%RCX,8),%ZMM13,%ZMM13 |
(323) 0x43f3a4 VADDPD %ZMM12,%ZMM7,%ZMM7 |
(323) 0x43f3aa VSUBPD %ZMM7,%ZMM8,%ZMM7 |
(323) 0x43f3b0 VADDPD %ZMM13,%ZMM7,%ZMM7 |
(323) 0x43f3b6 VMULPD %ZMM1,%ZMM10,%ZMM8 |
(323) 0x43f3bc VANDPD %ZMM3,%ZMM12,%ZMM12 |
(323) 0x43f3c2 VANDPD %ZMM3,%ZMM13,%ZMM13 |
(323) 0x43f3c8 VCMPPD $0x2,%ZMM13,%ZMM9,%K1 |
(323) 0x43f3cf VMOVAPD %ZMM13,%ZMM9{%K1} |
(323) 0x43f3d5 VCMPPD $0x2,%ZMM12,%ZMM9,%K1 |
(323) 0x43f3dc VMOVAPD %ZMM12,%ZMM9{%K1} |
(323) 0x43f3e2 VDIVPD %ZMM9,%ZMM8,%ZMM8 |
(323) 0x43f3e8 VDIVPD %ZMM10,%ZMM7,%ZMM7 |
(323) 0x43f3ee VMOVAPD %ZMM28,%ZMM9 |
(323) 0x43f3f4 VCMPPD $0x1,%ZMM4,%ZMM7,%K1 |
(323) 0x43f3fb VMOVAPD %ZMM5,%ZMM28 |
(323) 0x43f401 VDIVPD %ZMM7,%ZMM0,%ZMM28{%K1} |
(323) 0x43f407 VCMPPD $0x2,%ZMM28,%ZMM8,%K1 |
(323) 0x43f40e VMOVAPD %ZMM8,%ZMM28{%K1} |
(323) 0x43f414 VCMPPD $0x2,%ZMM28,%ZMM11,%K1 |
(323) 0x43f41b VMOVAPD %ZMM11,%ZMM28{%K1} |
(323) 0x43f421 VCMPPD $0x2,%ZMM28,%ZMM6,%K1 |
(323) 0x43f428 VMOVAPD %ZMM6,%ZMM28{%K1} |
(323) 0x43f42e VCMPPD $0x2,%ZMM28,%ZMM9,%K1 |
(323) 0x43f435 VMOVAPD %ZMM9,%ZMM28{%K1} |
(323) 0x43f43b ADD $0x8,%RCX |
(323) 0x43f43f CMP %RSI,%RCX |
(323) 0x43f442 JB 43f2b0 |
(322) 0x43f448 VMOVAPD %XMM28,%XMM0 |
(322) 0x43f44e VSHUFPD $0x1,%XMM28,%XMM28,%XMM1 |
(322) 0x43f455 VMINSD %XMM28,%XMM1,%XMM6 |
(322) 0x43f45b VCMPSD $0x3,%XMM28,%XMM28,%K1 |
(322) 0x43f462 VMOVSD %XMM1,%XMM6,%XMM6{%K1} |
(322) 0x43f468 VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(322) 0x43f46f VMOVAPD %YMM28,%YMM0 |
(322) 0x43f475 VEXTRACTF32X4 $0x1,%YMM28,%XMM0 |
(322) 0x43f47c VMINSD %XMM6,%XMM0,%XMM1 |
(322) 0x43f480 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(322) 0x43f486 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(322) 0x43f48d VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(322) 0x43f492 VMINSD %XMM1,%XMM0,%XMM1 |
(322) 0x43f496 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(322) 0x43f49c VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(322) 0x43f4a3 VEXTRACTF32X4 $0x2,%ZMM28,%XMM0 |
(322) 0x43f4aa VMINSD %XMM1,%XMM0,%XMM1 |
(322) 0x43f4ae VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(322) 0x43f4b4 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(322) 0x43f4bb VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(322) 0x43f4c0 VMINSD %XMM1,%XMM0,%XMM1 |
(322) 0x43f4c4 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(322) 0x43f4ca VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(322) 0x43f4d1 VEXTRACTF32X4 $0x3,%ZMM28,%XMM0 |
(322) 0x43f4d8 VMINSD %XMM1,%XMM0,%XMM1 |
(322) 0x43f4dc VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(322) 0x43f4e2 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(322) 0x43f4e9 VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(322) 0x43f4ee VMINSD %XMM1,%XMM0,%XMM28 |
(322) 0x43f4f4 VMOVSD %XMM0,%XMM28,%XMM28{%K1} |
(322) 0x43f4fa MOV 0x128(%RSP),%RAX |
(322) 0x43f502 CMP %RAX,%RSI |
(322) 0x43f505 JE 43f040 |
(322) 0x43f50b VPBROADCASTQ %RAX,%ZMM0 |
(322) 0x43f511 MOV 0x34(%RSP),%R15D |
(322) 0x43f516 MOV 0x60(%RSP),%R12 |
(322) 0x43f51b MOV 0x78(%RSP),%R14 |
(322) 0x43f520 MOV 0x70(%RSP),%R11 |
(322) 0x43f525 MOV 0x118(%RSP),%R13 |
(322) 0x43f52d MOV 0x110(%RSP),%RCX |
(322) 0x43f535 MOV 0x108(%RSP),%R8 |
(322) 0x43f53d MOV 0x68(%RSP),%RDI |
(322) 0x43f542 MOV 0x100(%RSP),%RAX |
(322) 0x43f54a JMP 43f594 |
0x43f54c NOPW %CS:(%RAX,%RAX,1) |
0x43f55b NOPW %CS:(%RAX,%RAX,1) |
0x43f56a NOPW %CS:(%RAX,%RAX,1) |
0x43f579 NOPL (%RAX) |
(322) 0x43f580 VPBROADCASTQ %RAX,%ZMM0 |
(322) 0x43f586 XOR %ESI,%ESI |
(322) 0x43f588 MOV %R15,%R11 |
(322) 0x43f58b MOV %R13,%RAX |
(322) 0x43f58e MOV %R9,%R13 |
(322) 0x43f591 MOV %EDX,%R15D |
(322) 0x43f594 VBROADCASTSD %XMM28,%ZMM28 |
(322) 0x43f59a VPBROADCASTQ %RSI,%ZMM1 |
(322) 0x43f5a0 VPSUBQ %ZMM1,%ZMM0,%ZMM0 |
(322) 0x43f5a6 VPCMPNLEUQ 0xcb10f(%RIP),%ZMM0,%K1 |
(322) 0x43f5b1 KORTESTB %K1,%K1 |
(322) 0x43f5b5 JE 43f940 |
(322) 0x43f5bb ADD 0x130(%RSP),%RSI |
(322) 0x43f5c3 SUB 0xa0(%RSP),%RSI |
(322) 0x43f5cb MOV %RAX,%R10 |
(322) 0x43f5ce LEA 0x1(%RCX),%RDX |
(322) 0x43f5d2 MOV %R8,%RAX |
(322) 0x43f5d5 MOV %RCX,%R9 |
(322) 0x43f5d8 MOV 0x138(%RSP),%RCX |
(322) 0x43f5e0 MOV %RCX,%RBX |
(322) 0x43f5e3 IMUL %RDX,%RBX |
(322) 0x43f5e7 MOV %RDX,%R8 |
(322) 0x43f5ea MOV 0x10(%RBP),%RDX |
(322) 0x43f5ee ADD %RDX,%RBX |
(322) 0x43f5f1 VMOVUPD (%RBX,%RSI,8),%ZMM0{%K1}{z} |
(322) 0x43f5f8 VMOVUPD 0x8(%RBX,%RSI,8),%ZMM1{%K1}{z} |
(322) 0x43f603 IMUL %R9,%RCX |
(322) 0x43f607 ADD %RDX,%RCX |
(322) 0x43f60a VMOVUPD (%RCX,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f611 VMOVUPD 0x8(%RCX,%RSI,8),%ZMM7{%K1}{z} |
(322) 0x43f61c IMUL %R9,%R10 |
(322) 0x43f620 ADD 0x50(%RBP),%R10 |
(322) 0x43f624 VMOVUPD (%R10,%RSI,8),%ZMM8{%K1}{z} |
(322) 0x43f62b VMOVUPD 0x8(%R10,%RSI,8),%ZMM9{%K1}{z} |
(322) 0x43f636 IMUL %R9,%RDI |
(322) 0x43f63a ADD 0x30(%RBP),%RDI |
(322) 0x43f63e VMOVUPD (%RDI,%RSI,8),%ZMM10{%K1}{z} |
(322) 0x43f645 MOV %RAX,%RCX |
(322) 0x43f648 IMUL %R9,%RCX |
(322) 0x43f64c MOV 0x98(%RSP),%RDX |
(322) 0x43f654 ADD %RDX,%RCX |
(322) 0x43f657 VMOVUPD 0x8(%RCX,%RSI,8),%ZMM11{%K1}{z} |
(322) 0x43f662 VMOVUPD (%RCX,%RSI,8),%ZMM12{%K1}{z} |
(322) 0x43f669 IMUL %R9,%R11 |
(322) 0x43f66d IMUL %R9,%R14 |
(322) 0x43f671 MOV 0x80(%RSP),%RDI |
(322) 0x43f679 IMUL %R9,%RDI |
(322) 0x43f67d VMOVAPD 0x2c0(%RSP),%ZMM13 |
(322) 0x43f685 VMOVAPD %ZMM0,%ZMM13{%K1} |
(322) 0x43f68b IMUL %R13,%R9 |
(322) 0x43f68f MOV 0x48(%RBP),%RCX |
(322) 0x43f693 ADD %RCX,%R9 |
(322) 0x43f696 VMOVUPD (%R9,%RSI,8),%ZMM0{%K1}{z} |
(322) 0x43f69d VMOVAPD 0x280(%RSP),%ZMM29 |
(322) 0x43f6a5 VMOVAPD %ZMM6,%ZMM29{%K1} |
(322) 0x43f6ab VMOVAPD 0x240(%RSP),%ZMM30 |
(322) 0x43f6b3 VMOVAPD %ZMM8,%ZMM30{%K1} |
(322) 0x43f6b9 IMUL %R8,%RAX |
(322) 0x43f6bd ADD %RDX,%RAX |
(322) 0x43f6c0 VMOVUPD 0x8(%RAX,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f6cb VMOVUPD (%RAX,%RSI,8),%ZMM8{%K1}{z} |
(322) 0x43f6d2 VMOVAPD 0x200(%RSP),%ZMM31 |
(322) 0x43f6da VMOVAPD %ZMM1,%ZMM31{%K1} |
(322) 0x43f6e0 IMUL %R8,%R13 |
(322) 0x43f6e4 VMOVAPD 0x1c0(%RSP),%ZMM14 |
(322) 0x43f6ec VMOVAPD %ZMM7,%ZMM14{%K1} |
(322) 0x43f6f2 ADD %RCX,%R13 |
(322) 0x43f6f5 VMOVUPD (%R13,%RSI,8),%ZMM1{%K1}{z} |
(322) 0x43f6fd VMOVAPD 0x180(%RSP),%ZMM16 |
(322) 0x43f705 VMOVAPD %ZMM9,%ZMM16{%K1} |
(322) 0x43f70b VMOVAPD %ZMM10,%ZMM15{%K1} |
(322) 0x43f711 VMOVAPD %ZMM13,0x2c0(%RSP) |
(322) 0x43f719 VMOVAPD %ZMM29,0x280(%RSP) |
(322) 0x43f721 VADDPD %ZMM29,%ZMM13,%ZMM7 |
(322) 0x43f727 VMOVAPD %ZMM30,0x240(%RSP) |
(322) 0x43f72f VMULPD %ZMM7,%ZMM30,%ZMM7 |
(322) 0x43f735 VMOVAPD 0x140(%RSP),%ZMM13 |
(322) 0x43f73d VMOVAPD %ZMM11,%ZMM13{%K1} |
(322) 0x43f743 VMOVAPD %ZMM31,0x200(%RSP) |
(322) 0x43f74b VMOVAPD %ZMM14,0x1c0(%RSP) |
(322) 0x43f753 VADDPD %ZMM14,%ZMM31,%ZMM9 |
(322) 0x43f759 VMOVAPD %ZMM16,0x180(%RSP) |
(322) 0x43f761 VMULPD %ZMM16,%ZMM9,%ZMM9 |
(322) 0x43f767 VMOVAPD %ZMM12,%ZMM17{%K1} |
(322) 0x43f76d VADDPD %ZMM15,%ZMM15,%ZMM10 |
(322) 0x43f773 VMOVAPD %ZMM0,%ZMM18{%K1} |
(322) 0x43f779 VMOVAPD %ZMM13,0x140(%RSP) |
(322) 0x43f781 VADDPD %ZMM17,%ZMM13,%ZMM0 |
(322) 0x43f787 VMULPD %ZMM0,%ZMM18,%ZMM11 |
(322) 0x43f78d VMOVAPD %ZMM6,%ZMM19{%K1} |
(322) 0x43f793 VMOVAPD %ZMM8,%ZMM20{%K1} |
(322) 0x43f799 VADDPD %ZMM20,%ZMM19,%ZMM0 |
(322) 0x43f79f VMOVAPD %ZMM1,%ZMM21{%K1} |
(322) 0x43f7a5 VMULPD %ZMM21,%ZMM0,%ZMM1 |
(322) 0x43f7ab VADDPD %ZMM11,%ZMM7,%ZMM0 |
(322) 0x43f7b1 VSUBPD %ZMM0,%ZMM9,%ZMM0 |
(322) 0x43f7b7 VADDPD %ZMM1,%ZMM0,%ZMM0 |
(322) 0x43f7bd VDIVPD %ZMM10,%ZMM0,%ZMM6 |
(322) 0x43f7c3 VBROADCASTSD %XMM27,%ZMM8 |
(322) 0x43f7c9 VCMPPD $0x1,%ZMM4,%ZMM6,%K2 |
(322) 0x43f7d0 VMOVAPD %ZMM5,%ZMM0 |
(322) 0x43f7d6 VDIVPD %ZMM6,%ZMM8,%ZMM0{%K2} |
(322) 0x43f7dc MOV 0x40(%RBP),%RAX |
(322) 0x43f7e0 VMOVUPD (%RAX,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f7e7 VMOVAPD %ZMM6,%ZMM22{%K1} |
(322) 0x43f7ed ADD 0x18(%RBP),%R11 |
(322) 0x43f7f1 VMOVUPD (%R11,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f7f8 VMOVAPD 0x380(%RSP),%ZMM8 |
(322) 0x43f800 VMOVAPD %ZMM6,%ZMM8{%K1} |
(322) 0x43f806 ADD 0x20(%RBP),%R14 |
(322) 0x43f80a VMOVUPD (%R14,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f811 VMOVAPD 0x340(%RSP),%ZMM12 |
(322) 0x43f819 VMOVAPD %ZMM6,%ZMM12{%K1} |
(322) 0x43f81f MOV %RDI,%RAX |
(322) 0x43f822 ADD 0x28(%RBP),%RAX |
(322) 0x43f826 VMOVUPD (%RAX,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f82d VMOVAPD 0x300(%RSP),%ZMM13 |
(322) 0x43f835 VMOVAPD %ZMM6,%ZMM13{%K1} |
(322) 0x43f83b VMOVAPD %ZMM12,0x340(%RSP) |
(322) 0x43f843 VADDPD %ZMM12,%ZMM12,%ZMM6 |
(322) 0x43f849 VMOVAPD %ZMM13,0x300(%RSP) |
(322) 0x43f851 VDIVPD %ZMM13,%ZMM6,%ZMM6 |
(322) 0x43f857 VMOVAPD %ZMM8,0x380(%RSP) |
(322) 0x43f85f VFMADD231PD %ZMM8,%ZMM8,%ZMM6 |
(322) 0x43f865 VSQRTPD %ZMM6,%ZMM6 |
(322) 0x43f86b VBROADCASTSD %XMM23,%ZMM8 |
(322) 0x43f871 VMINPD %ZMM8,%ZMM22,%ZMM8 |
(322) 0x43f877 VBROADCASTSD %XMM25,%ZMM12 |
(322) 0x43f87d VMULPD %ZMM8,%ZMM12,%ZMM8 |
(322) 0x43f883 VMAXPD %ZMM2,%ZMM6,%ZMM6 |
(322) 0x43f889 VDIVPD %ZMM6,%ZMM8,%ZMM6 |
(322) 0x43f88f VANDPD %ZMM3,%ZMM7,%ZMM7 |
(322) 0x43f895 VANDPD %ZMM3,%ZMM9,%ZMM8 |
(322) 0x43f89b VMULPD %ZMM2,%ZMM15,%ZMM9 |
(322) 0x43f8a1 VCMPPD $0x2,%ZMM8,%ZMM9,%K2 |
(322) 0x43f8a8 VBLENDMPD %ZMM8,%ZMM9,%ZMM8{%K2} |
(322) 0x43f8ae VCMPPD $0x2,%ZMM7,%ZMM8,%K2 |
(322) 0x43f8b5 VMOVAPD %ZMM7,%ZMM8{%K2} |
(322) 0x43f8bb VBROADCASTSD %XMM24,%ZMM7 |
(322) 0x43f8c1 VMULPD %ZMM7,%ZMM10,%ZMM7 |
(322) 0x43f8c7 VDIVPD %ZMM8,%ZMM7,%ZMM7 |
(322) 0x43f8cd VBROADCASTSD %XMM26,%ZMM8 |
(322) 0x43f8d3 VMULPD %ZMM8,%ZMM10,%ZMM8 |
(322) 0x43f8d9 VANDPD %ZMM3,%ZMM1,%ZMM1 |
(322) 0x43f8df VCMPPD $0x2,%ZMM1,%ZMM9,%K2 |
(322) 0x43f8e6 VMOVAPD %ZMM1,%ZMM9{%K2} |
(322) 0x43f8ec VANDPD %ZMM3,%ZMM11,%ZMM1 |
(322) 0x43f8f2 VCMPPD $0x2,%ZMM1,%ZMM9,%K2 |
(322) 0x43f8f9 VMOVAPD %ZMM1,%ZMM9{%K2} |
(322) 0x43f8ff VDIVPD %ZMM9,%ZMM8,%ZMM1 |
(322) 0x43f905 VCMPPD $0x2,%ZMM0,%ZMM1,%K2 |
(322) 0x43f90c VMOVAPD %ZMM1,%ZMM0{%K2} |
(322) 0x43f912 VCMPPD $0x2,%ZMM0,%ZMM7,%K2 |
(322) 0x43f919 VMOVAPD %ZMM7,%ZMM0{%K2} |
(322) 0x43f91f VCMPPD $0x2,%ZMM0,%ZMM6,%K2 |
(322) 0x43f926 VMOVAPD %ZMM6,%ZMM0{%K2} |
(322) 0x43f92c VCMPPD $0x2,%ZMM0,%ZMM28,%K2 |
(322) 0x43f933 VMOVAPD %ZMM28,%ZMM0{%K2} |
(322) 0x43f939 JMP 43f944 |
0x43f93b NOPL (%RAX,%RAX,1) |
(322) 0x43f940 VPXOR %XMM0,%XMM0,%XMM0 |
(322) 0x43f944 VMOVAPD %ZMM0,%ZMM28{%K1} |
(322) 0x43f94a VEXTRACTF32X4 $0x3,%ZMM28,%XMM0 |
(322) 0x43f951 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(322) 0x43f956 VEXTRACTF32X4 $0x2,%ZMM28,%XMM6 |
(322) 0x43f95d VSHUFPD $0x1,%XMM6,%XMM6,%XMM7 |
(322) 0x43f962 VMOVAPD %YMM28,%YMM8 |
(322) 0x43f968 VEXTRACTF32X4 $0x1,%YMM28,%XMM8 |
(322) 0x43f96f VSHUFPD $0x1,%XMM8,%XMM8,%XMM9 |
(322) 0x43f975 VMOVAPD %XMM28,%XMM10 |
(322) 0x43f97b VSHUFPD $0x1,%XMM28,%XMM28,%XMM11 |
(322) 0x43f982 VMINSD %XMM28,%XMM11,%XMM12 |
(322) 0x43f988 VCMPSD $0x3,%XMM28,%XMM28,%K1 |
(322) 0x43f98f VMOVSD %XMM11,%XMM12,%XMM12{%K1} |
(322) 0x43f995 VCMPSD $0x3,%XMM12,%XMM12,%K1 |
(322) 0x43f99c VMINSD %XMM12,%XMM8,%XMM10 |
(322) 0x43f9a1 VMOVSD %XMM8,%XMM10,%XMM10{%K1} |
(322) 0x43f9a7 VCMPSD $0x3,%XMM10,%XMM10,%K1 |
(322) 0x43f9ae VMINSD %XMM10,%XMM9,%XMM8 |
(322) 0x43f9b3 VMOVSD %XMM9,%XMM8,%XMM8{%K1} |
(322) 0x43f9b9 VCMPSD $0x3,%XMM8,%XMM8,%K1 |
(322) 0x43f9c0 VMINSD %XMM8,%XMM6,%XMM8 |
(322) 0x43f9c5 VMOVSD %XMM6,%XMM8,%XMM8{%K1} |
(322) 0x43f9cb VCMPSD $0x3,%XMM8,%XMM8,%K1 |
(322) 0x43f9d2 VMINSD %XMM8,%XMM7,%XMM6 |
(322) 0x43f9d7 VMOVSD %XMM7,%XMM6,%XMM6{%K1} |
(322) 0x43f9dd VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(322) 0x43f9e4 VMINSD %XMM6,%XMM0,%XMM6 |
(322) 0x43f9e8 VMOVSD %XMM0,%XMM6,%XMM6{%K1} |
(322) 0x43f9ee VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(322) 0x43f9f5 VMINSD %XMM6,%XMM1,%XMM0 |
(322) 0x43f9f9 VMOVSD %XMM1,%XMM0,%XMM0{%K1} |
(322) 0x43f9ff VMOVDDUP %XMM0,%XMM28 |
(322) 0x43fa05 JMP 43f050 |
0x43fa0a NOPW %CS:(%RAX,%RAX,1) |
0x43fa19 NOPW %CS:(%RAX,%RAX,1) |
0x43fa28 NOPW %CS:(%RAX,%RAX,1) |
0x43fa37 NOPW (%RAX,%RAX,1) |
0x43fa40 VSHUFPD $0x1,%XMM28,%XMM28,%XMM0 |
0x43fa47 VMOVSD %XMM0,0x88(%RSP) |
0x43fa50 MOV $0x54d0d0,%EDI |
0x43fa55 MOV 0x40(%RSP),%ESI |
0x43fa59 VZEROUPPER |
0x43fa5c CALL 404230 <__kmpc_for_static_fini@plt> |
0x43fa61 MOV 0x50(%RSP),%RBX |
0x43fa66 MOV (%RBX),%ESI |
0x43fa68 SUB $0x8,%RSP |
0x43fa6c LEA 0x90(%RSP),%R8 |
0x43fa74 MOV $0x54d0f0,%EDI |
0x43fa79 MOV $0x43faf0,%R9D |
0x43fa7f MOV $0x1,%EDX |
0x43fa84 MOV $0x8,%ECX |
0x43fa89 PUSH $0x55433c |
0x43fa8e CALL 404830 <__kmpc_reduce@plt> |
0x43fa93 MOV %RBX,%RDI |
0x43fa96 ADD $0x10,%RSP |
0x43fa9a CMP $0x1,%EAX |
0x43fa9d MOV 0x90(%RSP),%RAX |
0x43faa5 JNE 43face |
0x43faa7 VMOVSD 0x88(%RSP),%XMM0 |
0x43fab0 VMINSD (%RAX),%XMM0,%XMM0 |
0x43fab4 VMOVSD %XMM0,(%RAX) |
0x43fab8 MOV (%RDI),%ESI |
0x43faba MOV $0x54d110,%EDI |
0x43fabf MOV $0x55433c,%EDX |
0x43fac4 CALL 4049b0 <__kmpc_end_reduce@plt> |
0x43fac9 MOV 0x50(%RSP),%RDI |
0x43face MOV (%RDI),%ESI |
0x43fad0 MOV $0x54d130,%EDI |
0x43fad5 CALL 404740 <__kmpc_barrier@plt> |
0x43fada LEA -0x28(%RBP),%RSP |
0x43fade POP %RBX |
0x43fadf POP %R12 |
0x43fae1 POP %R13 |
0x43fae3 POP %R14 |
0x43fae5 POP %R15 |
0x43fae7 POP %RBP |
0x43fae8 RET |
0x43fae9 NOPL (%RAX) |
Path / |
Source file and lines | calc_dt_kernel.f90:89-133 |
Module | exec |
nb instructions | 178 |
nb uops | 184 |
loop length | 927 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 4 |
nb stack references | 36 |
micro-operation queue | 30.67 cycles |
front end | 30.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.90 | 12.80 | 12.33 | 12.33 | 20.00 | 12.80 | 12.70 | 20.00 | 20.00 | 20.00 | 12.80 | 12.33 |
cycles | 12.90 | 12.80 | 12.33 | 12.33 | 20.00 | 12.80 | 12.70 | 20.00 | 20.00 | 20.00 | 12.80 | 12.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 29.87 |
Stall cycles | 0.00 |
Front-end | 30.67 |
Dispatch | 20.00 |
Overall L1 | 30.67 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 9% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 6% |
all | 10% |
load | 8% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 14% |
all | 11% |
load | 10% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x400,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVL $0,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 43face <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xd0e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x50(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x54(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x44(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x40(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x54d0b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 404670 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x3c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 43ee80 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0xcc857(%RIP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 43fa47 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc87> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x20,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $-0x200000000,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
LEA (%R12,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x20,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $-0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNS %RDI,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RSI,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x200000000,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV %RBX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R12,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RDI,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %R8,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0x8,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R14,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVG %RSI,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R15,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RCX,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RDX,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R9,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NEG %RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R13,%RDI,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0x10(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDI,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDDUP 0xcc6f2(%RIP),%XMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD 0xcc698(%RIP),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcc656(%RIP),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcc6dc(%RIP),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcc6da(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV 0x90(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%RAX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43f066 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x2a6> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VSHUFPD $0x1,%XMM28,%XMM28,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x54d0d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x40(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 404230 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x50(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x90(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x54d0f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x43faf0,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x55433c | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 404830 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 43face <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xd0e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0x88(%RSP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMINSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x54d110,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x55433c,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4049b0 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x50(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x54d130,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404740 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | calc_dt_kernel.f90:89-133 |
Module | exec |
nb instructions | 178 |
nb uops | 184 |
loop length | 927 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 4 |
nb stack references | 36 |
micro-operation queue | 30.67 cycles |
front end | 30.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.90 | 12.80 | 12.33 | 12.33 | 20.00 | 12.80 | 12.70 | 20.00 | 20.00 | 20.00 | 12.80 | 12.33 |
cycles | 12.90 | 12.80 | 12.33 | 12.33 | 20.00 | 12.80 | 12.70 | 20.00 | 20.00 | 20.00 | 12.80 | 12.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 29.87 |
Stall cycles | 0.00 |
Front-end | 30.67 |
Dispatch | 20.00 |
Overall L1 | 30.67 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 9% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 6% |
all | 10% |
load | 8% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 14% |
all | 11% |
load | 10% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x400,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVL $0,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 43face <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xd0e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x50(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x54(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x44(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x40(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x54d0b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 404670 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x3c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 43ee80 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0xcc857(%RIP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 43fa47 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc87> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x20,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $-0x200000000,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
LEA (%R12,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x20,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $-0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNS %RDI,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RSI,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x200000000,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV %RBX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R12,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RDI,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %R8,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0x8,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R14,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVG %RSI,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R15,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RCX,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RDX,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R9,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NEG %RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R13,%RDI,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0x10(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDI,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDDUP 0xcc6f2(%RIP),%XMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD 0xcc698(%RIP),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcc656(%RIP),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcc6dc(%RIP),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcc6da(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV 0x90(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%RAX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43f066 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x2a6> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VSHUFPD $0x1,%XMM28,%XMM28,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x54d0d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x40(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 404230 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x50(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x90(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x54d0f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x43faf0,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x55433c | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 404830 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 43face <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xd0e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0x88(%RSP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMINSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x54d110,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x55433c,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4049b0 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x50(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x54d130,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404740 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼calc_dt_kernel_.DIR.OMP.PARALLEL.2– | 4.9 | 1.54 |
▼Loop 322 - calc_dt_kernel.f90:92-129 - exec– | 0 | 0 |
○Loop 323 - calc_dt_kernel.f90:94-129 - exec | 4.9 | 1.54 |