Function: accelerate_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: accelerate_kernel.f90:57-79 | Coverage: 4.89% |
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Function: accelerate_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: accelerate_kernel.f90:57-79 | Coverage: 4.89% |
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/home/eoseret/qaas_runs_CPU_9468/171-137-7698/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 57 - 79 |
-------------------------------------------------------------------------------- |
57: !$OMP PARALLEL |
58: |
59: !$OMP DO PRIVATE(j,k,stepbymass_s) |
60: DO k=y_min,y_max+1 |
61: !$OMP SIMD |
62: DO j=x_min,x_max+1 |
63: stepbymass_s=halfdt/((density0(j-1,k-1)*volume(j-1,k-1) & |
64: +density0(j ,k-1)*volume(j ,k-1) & |
65: +density0(j ,k )*volume(j ,k ) & |
66: +density0(j-1,k )*volume(j-1,k )) & |
67: *0.25_8) |
68: |
69: xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j ,k )*(pressure(j ,k )-pressure(j-1,k )) & |
70: +xarea(j ,k-1)*(pressure(j ,k-1)-pressure(j-1,k-1))) |
71: yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j ,k )*(pressure(j ,k )-pressure(j ,k-1)) & |
72: +yarea(j-1,k )*(pressure(j-1,k )-pressure(j-1,k-1))) |
73: xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j ,k )*(viscosity(j ,k )-viscosity(j-1,k )) & |
74: +xarea(j ,k-1)*(viscosity(j ,k-1)-viscosity(j-1,k-1))) |
75: yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j ,k )*(viscosity(j ,k )-viscosity(j ,k-1)) & |
76: +yarea(j-1,k )*(viscosity(j-1,k )-viscosity(j-1,k-1))) |
77: ENDDO |
78: ENDDO |
79: !$OMP END DO |
0x4245a0 PUSH %RBP |
0x4245a1 MOV %RSP,%RBP |
0x4245a4 PUSH %R15 |
0x4245a6 PUSH %R14 |
0x4245a8 PUSH %R13 |
0x4245aa PUSH %R12 |
0x4245ac PUSH %RBX |
0x4245ad AND $-0x20,%RSP |
0x4245b1 SUB $0x480,%RSP |
0x4245b8 MOV %R9,0xa8(%RSP) |
0x4245c0 MOV %RCX,%RSI |
0x4245c3 MOV 0xc0(%RBP),%RAX |
0x4245ca MOV %RAX,0x1e0(%RSP) |
0x4245d2 MOV 0xb8(%RBP),%RAX |
0x4245d9 MOV %RAX,0x1d8(%RSP) |
0x4245e1 MOV 0xb0(%RBP),%RAX |
0x4245e8 MOV %RAX,0x1d0(%RSP) |
0x4245f0 MOV 0xa8(%RBP),%RAX |
0x4245f7 MOV %RAX,0x1c8(%RSP) |
0x4245ff MOV 0xa0(%RBP),%RAX |
0x424606 MOV %RAX,0x1c0(%RSP) |
0x42460e MOV 0x98(%RBP),%RAX |
0x424615 MOV %RAX,0x1b8(%RSP) |
0x42461d MOV 0x60(%RBP),%EBX |
0x424620 MOV 0x58(%RBP),%EAX |
0x424623 SUB %EBX,%EAX |
0x424625 INC %EAX |
0x424627 MOV 0x90(%RBP),%RCX |
0x42462e MOV %RCX,0x1b0(%RSP) |
0x424636 MOV 0x88(%RBP),%RCX |
0x42463d MOV %RCX,0x1a8(%RSP) |
0x424645 MOV 0x80(%RBP),%RCX |
0x42464c MOV %RCX,0x1a0(%RSP) |
0x424654 MOV 0x78(%RBP),%RCX |
0x424658 MOV %RCX,0x198(%RSP) |
0x424660 MOV 0x70(%RBP),%R13 |
0x424664 MOV 0x68(%RBP),%R9 |
0x424668 MOV 0x50(%RBP),%RCX |
0x42466c MOV %RCX,0xa0(%RSP) |
0x424674 MOV 0x48(%RBP),%RCX |
0x424678 MOV %RCX,0x98(%RSP) |
0x424680 MOV 0x40(%RBP),%RCX |
0x424684 MOV %RCX,0x90(%RSP) |
0x42468c MOV 0x38(%RBP),%RCX |
0x424690 MOV %RCX,0x88(%RSP) |
0x424698 MOV 0x30(%RBP),%RCX |
0x42469c MOV %RCX,0x80(%RSP) |
0x4246a4 MOV 0x28(%RBP),%RCX |
0x4246a8 MOV %RCX,0x78(%RSP) |
0x4246ad MOV 0x20(%RBP),%RCX |
0x4246b1 MOV %RCX,0x70(%RSP) |
0x4246b6 MOV 0x18(%RBP),%RCX |
0x4246ba MOV %RCX,0x68(%RSP) |
0x4246bf MOV 0x10(%RBP),%RCX |
0x4246c3 MOV %RCX,0x60(%RSP) |
0x4246c8 MOVL $0,0x5c(%RSP) |
0x4246d0 JS 42475f |
0x4246d6 MOV %R9,0x8(%RSP) |
0x4246db MOV %RDX,%R14 |
0x4246de MOV %R8,%R15 |
0x4246e1 MOV %RSI,0x20(%RSP) |
0x4246e6 MOV %RDI,0x110(%RSP) |
0x4246ee MOV (%RDI),%ESI |
0x4246f0 MOVL $0,0x34(%RSP) |
0x4246f8 MOV %EAX,0x30(%RSP) |
0x4246fc MOVL $0x1,0x58(%RSP) |
0x424704 SUB $0x8,%RSP |
0x424708 LEA 0x60(%RSP),%RAX |
0x42470d LEA 0x64(%RSP),%RCX |
0x424712 LEA 0x3c(%RSP),%R8 |
0x424717 LEA 0x38(%RSP),%R9 |
0x42471c MOV $0x536290,%EDI |
0x424721 MOV %ESI,0x54(%RSP) |
0x424725 MOV $0x22,%EDX |
0x42472a PUSH $0x1 |
0x42472c PUSH $0x1 |
0x42472e PUSH %RAX |
0x42472f CALL 404670 <__kmpc_for_static_init_4@plt> |
0x424734 ADD $0x20,%RSP |
0x424738 MOV 0x34(%RSP),%EAX |
0x42473c MOV 0x30(%RSP),%R12D |
0x424741 SUB %EAX,%R12D |
0x424744 JAE 424779 |
0x424746 MOV $0x5362b0,%EDI |
0x42474b MOV 0x4c(%RSP),%ESI |
0x42474f VZEROUPPER |
0x424752 CALL 404230 <__kmpc_for_static_fini@plt> |
0x424757 MOV 0x110(%RSP),%RDI |
0x42475f MOV (%RDI),%ESI |
0x424761 MOV $0x5362d0,%EDI |
0x424766 LEA -0x28(%RBP),%RSP |
0x42476a POP %RBX |
0x42476b POP %R12 |
0x42476d POP %R13 |
0x42476f POP %R14 |
0x424771 POP %R15 |
0x424773 POP %RBP |
0x424774 JMP 404740 |
0x424779 MOV %RAX,%R8 |
0x42477c VMOVQ %R14,%XMM0 |
0x424781 MOV %R15,%R9 |
0x424784 SAL $0x20,%R9 |
0x424788 MOV $-0x200000000,%RAX |
0x424792 LEA (%R9,%RAX,1),%RCX |
0x424796 MOV %RCX,%R10 |
0x424799 SAR $0x20,%R10 |
0x42479d MOV 0x20(%RSP),%RDX |
0x4247a2 SAL $0x20,%RDX |
0x4247a6 ADD %RDX,%RAX |
0x4247a9 MOV %RDX,%R14 |
0x4247ac MOV %RAX,%R11 |
0x4247af SAR $0x20,%R11 |
0x4247b3 ADD %EBX,%R8D |
0x4247b6 MOVSXD (%R13),%RBX |
0x4247ba MOV 0x8(%RSP),%RDX |
0x4247bf MOV (%RDX),%EDX |
0x4247c1 SUB %EBX,%EDX |
0x4247c3 LEA 0x1(%RDX),%ESI |
0x4247c6 MOV %ESI,0x54(%RSP) |
0x4247ca ADD $0x2,%EDX |
0x4247cd CMP $0x2,%EDX |
0x4247d0 MOV $0x1,%R15D |
0x4247d6 CMOVGE %EDX,%R15D |
0x4247da MOV %R15D,%EDX |
0x4247dd AND $0x7ffffffc,%EDX |
0x4247e3 MOV %RDX,0x20(%RSP) |
0x4247e8 TEST %RCX,%RCX |
0x4247eb MOV $-0x1,%RDX |
0x4247f2 CMOVNS %RCX,%RDX |
0x4247f6 TEST %RDX,%RDX |
0x4247f9 MOV $0x1,%ESI |
0x4247fe CMOVG %RSI,%RDX |
0x424802 MOV $0x200000000,%R13 |
0x42480c MOV %R13,%RDI |
0x42480f SUB %R9,%RDI |
0x424812 CMP %RDI,%RCX |
0x424815 CMOVG %RCX,%RDI |
0x424819 MOV %R11,0xb8(%RSP) |
0x424821 NOT %R11 |
0x424824 MOV %R11,0xb0(%RSP) |
0x42482c VPBROADCASTQ %XMM0,%YMM0 |
0x424831 MOV %R15,0x170(%RSP) |
0x424839 VPBROADCASTQ %R15,%YMM1 |
0x42483f VMOVDQA %YMM1,0x220(%RSP) |
0x424848 SHR $0x20,%RDI |
0x42484c IMUL %RDX,%RDI |
0x424850 MOV %RBX,0x180(%RSP) |
0x424858 LEA (,%RBX,8),%R11 |
0x424860 SAL $0x3,%RDI |
0x424864 SUB %RDI,%R11 |
0x424867 MOV $-0x1,%RCX |
0x42486e TEST %RAX,%RAX |
0x424871 CMOVNS %RAX,%RCX |
0x424875 TEST %RCX,%RCX |
0x424878 CMOVG %RSI,%RCX |
0x42487c MOV %R10,0x188(%RSP) |
0x424884 NOT %R10 |
0x424887 MOV %R10,0x178(%RSP) |
0x42488f SUB %R14,%R13 |
0x424892 MOV 0x90(%RSP),%RDX |
0x42489a ADD %R11,%RDX |
0x42489d MOV %RDX,0x158(%RSP) |
0x4248a5 CMP %R13,%RAX |
0x4248a8 CMOVG %RAX,%R13 |
0x4248ac MOV 0x88(%RSP),%RAX |
0x4248b4 ADD %R11,%RAX |
0x4248b7 MOV %RAX,0x150(%RSP) |
0x4248bf SHR $0x20,%R13 |
0x4248c3 IMUL %RCX,%R13 |
0x4248c7 NEG %R13 |
0x4248ca MOV %R13,0x168(%RSP) |
0x4248d2 MOV 0x80(%RSP),%RAX |
0x4248da ADD %R11,%RAX |
0x4248dd MOV %RAX,0x148(%RSP) |
0x4248e5 MOV 0x98(%RSP),%RAX |
0x4248ed LEA (%RAX,%R11,1),%RAX |
0x4248f1 MOV %RAX,0x140(%RSP) |
0x4248f9 MOV 0x78(%RSP),%RAX |
0x4248fe LEA (%RAX,%R11,1),%RAX |
0x424902 MOV %RAX,0x138(%RSP) |
0x42490a MOV 0xa8(%RSP),%RAX |
0x424912 LEA (%RAX,%R11,1),%RAX |
0x424916 MOV %RAX,0x130(%RSP) |
0x42491e MOV 0x68(%RSP),%RAX |
0x424923 ADD %R11,%RAX |
0x424926 MOV %RAX,0x128(%RSP) |
0x42492e MOV 0x60(%RSP),%RAX |
0x424933 ADD %R11,%RAX |
0x424936 MOV %RAX,0x120(%RSP) |
0x42493e MOV 0x70(%RSP),%RAX |
0x424943 ADD %R11,%RAX |
0x424946 MOV %RAX,0x118(%RSP) |
0x42494e ADD 0xa0(%RSP),%R11 |
0x424956 MOV %R11,0x160(%RSP) |
0x42495e VBROADCASTSD 0xd1101(%RIP),%YMM3 |
0x424967 XOR %R13D,%R13D |
0x42496a MOV %R8,0x190(%RSP) |
0x424972 MOV %R8D,%R15D |
0x424975 MOV %R12D,0x2c(%RSP) |
0x42497a JMP 424e23 |
0x42497f NOP |
(119) 0x424980 MOVSXD %ESI,%RSI |
(119) 0x424983 MOV 0xb0(%RSP),%RDI |
(119) 0x42498b ADD %RSI,%RDI |
(119) 0x42498e MOV %RCX,%R9 |
(119) 0x424991 IMUL %RDI,%R9 |
(119) 0x424995 MOV %R9,0xd0(%RSP) |
(119) 0x42499d MOV %RDX,%R13 |
(119) 0x4249a0 MOV %R8,%RDX |
(119) 0x4249a3 MOV %R8,%R9 |
(119) 0x4249a6 IMUL %RDI,%R9 |
(119) 0x4249aa MOV %R9,0xd8(%RSP) |
(119) 0x4249b2 MOV %R13,%R14 |
(119) 0x4249b5 IMUL %RDI,%R13 |
(119) 0x4249b9 MOV %R10,%R9 |
(119) 0x4249bc IMUL %RDI,%R10 |
(119) 0x4249c0 MOV %R11,%R8 |
(119) 0x4249c3 MOV %R11,%R12 |
(119) 0x4249c6 IMUL %RDI,%R8 |
(119) 0x4249ca SUB 0xb8(%RSP),%RSI |
(119) 0x4249d2 IMUL %RSI,%RCX |
(119) 0x4249d6 IMUL %RSI,%RDX |
(119) 0x4249da IMUL %RSI,%R14 |
(119) 0x4249de MOV %R14,0xe0(%RSP) |
(119) 0x4249e6 IMUL %RSI,%R9 |
(119) 0x4249ea MOV %R9,0xe8(%RSP) |
(119) 0x4249f2 MOV %RBX,%RAX |
(119) 0x4249f5 IMUL %RSI,%RAX |
(119) 0x4249f9 IMUL %RSI,%R12 |
(119) 0x4249fd MOV %R12,0xf8(%RSP) |
(119) 0x424a05 MOV 0x2c(%RSP),%R12D |
(119) 0x424a0a MOV 0x18(%RSP),%R9 |
(119) 0x424a0f IMUL %RSI,%R9 |
(119) 0x424a13 MOV 0x10(%RSP),%RDI |
(119) 0x424a18 IMUL %RSI,%RDI |
(119) 0x424a1c MOV 0x38(%RSP),%RBX |
(119) 0x424a21 IMUL %RSI,%RBX |
(119) 0x424a25 MOV 0x8(%RSP),%R11 |
(119) 0x424a2a IMUL %RSI,%R11 |
(119) 0x424a2e MOV %R9,0xf0(%RSP) |
(119) 0x424a36 MOV %R8,0x100(%RSP) |
(119) 0x424a3e MOV %RAX,%R9 |
(119) 0x424a41 MOV %R13,%R14 |
(119) 0x424a44 MOV 0x108(%RSP),%R13 |
(119) 0x424a4c MOV %RDX,0xc8(%RSP) |
(119) 0x424a54 MOV %RCX,0xc0(%RSP) |
(119) 0x424a5c XOR %EAX,%EAX |
(119) 0x424a5e VPBROADCASTQ %RAX,%YMM1 |
(119) 0x424a64 VMOVDQA 0x220(%RSP),%YMM2 |
(119) 0x424a6d VPSUBQ %YMM1,%YMM2,%YMM1 |
(119) 0x424a71 VPCMPNLEUQ 0xd05a4(%RIP),%YMM1,%K1 |
(119) 0x424a7c MOV 0x90(%RSP),%RDX |
(119) 0x424a84 MOV 0xd0(%RSP),%RSI |
(119) 0x424a8c ADD %RDX,%RSI |
(119) 0x424a8f ADD 0x180(%RSP),%RAX |
(119) 0x424a97 MOV 0x178(%RSP),%RCX |
(119) 0x424a9f ADD %RAX,%RCX |
(119) 0x424aa2 VMOVUPD (%RSI,%RCX,8),%YMM26{%K1}{z} |
(119) 0x424aa9 SUB 0x188(%RSP),%RAX |
(119) 0x424ab1 VMOVUPD (%RSI,%RAX,8),%YMM27{%K1}{z} |
(119) 0x424ab8 MOV 0x88(%RSP),%RSI |
(119) 0x424ac0 MOV 0xd8(%RSP),%R8 |
(119) 0x424ac8 ADD %RSI,%R8 |
(119) 0x424acb VMOVUPD (%R8,%RCX,8),%YMM28{%K1}{z} |
(119) 0x424ad2 VMOVUPD (%R8,%RAX,8),%YMM29{%K1}{z} |
(119) 0x424ad9 MOV 0xc0(%RSP),%R8 |
(119) 0x424ae1 ADD %RDX,%R8 |
(119) 0x424ae4 VMOVUPD (%R8,%RAX,8),%YMM30{%K1}{z} |
(119) 0x424aeb VMOVUPD (%R8,%RCX,8),%YMM31{%K1}{z} |
(119) 0x424af2 MOV 0xc8(%RSP),%RDX |
(119) 0x424afa ADD %RSI,%RDX |
(119) 0x424afd VMOVUPD (%RDX,%RAX,8),%YMM2{%K1}{z} |
(119) 0x424b04 VMOVUPD (%RDX,%RCX,8),%YMM1{%K1}{z} |
(119) 0x424b0b MOV 0xa0(%RSP),%RDX |
(119) 0x424b13 MOV 0xe0(%RSP),%RSI |
(119) 0x424b1b ADD %RDX,%RSI |
(119) 0x424b1e VMOVUPD (%RSI,%RAX,8),%YMM4{%K1}{z} |
(119) 0x424b25 MOV 0x80(%RSP),%RSI |
(119) 0x424b2d MOV 0xe8(%RSP),%R8 |
(119) 0x424b35 ADD %RSI,%R8 |
(119) 0x424b38 VMOVUPD (%R8,%RAX,8),%YMM5{%K1}{z} |
(119) 0x424b3f VMOVUPD (%R8,%RCX,8),%YMM18{%K1}{z} |
(119) 0x424b46 ADD %RDX,%R14 |
(119) 0x424b49 VMOVUPD (%R14,%RAX,8),%YMM19{%K1}{z} |
(119) 0x424b50 ADD %RSI,%R10 |
(119) 0x424b53 VMOVUPD (%R10,%RAX,8),%YMM20{%K1}{z} |
(119) 0x424b5a VMOVUPD (%R10,%RCX,8),%YMM21{%K1}{z} |
(119) 0x424b61 ADD 0x98(%RSP),%R9 |
(119) 0x424b69 VMOVUPD (%R9,%RAX,8),%YMM22{%K1}{z} |
(119) 0x424b70 VMOVUPD (%R9,%RCX,8),%YMM23{%K1}{z} |
(119) 0x424b77 MOV 0x78(%RSP),%RDX |
(119) 0x424b7c MOV 0xf8(%RSP),%RSI |
(119) 0x424b84 ADD %RDX,%RSI |
(119) 0x424b87 VMOVUPD (%RSI,%RAX,8),%YMM24{%K1}{z} |
(119) 0x424b8e VMOVUPD (%RSI,%RCX,8),%YMM25{%K1}{z} |
(119) 0x424b95 MOV 0x100(%RSP),%RSI |
(119) 0x424b9d ADD %RDX,%RSI |
(119) 0x424ba0 VMOVUPD (%RSI,%RCX,8),%YMM6{%K1}{z} |
(119) 0x424ba7 VMOVUPD (%RSI,%RAX,8),%YMM7{%K1}{z} |
(119) 0x424bae MOV 0xf0(%RSP),%RCX |
(119) 0x424bb6 ADD 0x70(%RSP),%RCX |
(119) 0x424bbb VMOVUPD (%RCX,%RAX,8),%YMM8{%K1}{z} |
(119) 0x424bc2 VMOVAPD 0x260(%RSP),%YMM12 |
(119) 0x424bcb VMOVAPD %YMM26,%YMM12{%K1} |
(119) 0x424bd1 VMOVAPD 0x2a0(%RSP),%YMM11 |
(119) 0x424bda VMOVAPD %YMM28,%YMM11{%K1} |
(119) 0x424be0 VMOVAPD 0x2e0(%RSP),%YMM10 |
(119) 0x424be9 VMOVAPD %YMM27,%YMM10{%K1} |
(119) 0x424bef VMOVAPD 0x320(%RSP),%YMM9 |
(119) 0x424bf8 VMOVAPD %YMM29,%YMM9{%K1} |
(119) 0x424bfe VMOVAPD 0x340(%RSP),%YMM29 |
(119) 0x424c06 VMOVAPD %YMM30,%YMM29{%K1} |
(119) 0x424c0c VMOVAPD 0x360(%RSP),%YMM28 |
(119) 0x424c14 VMOVAPD %YMM2,%YMM28{%K1} |
(119) 0x424c1a VMOVAPD 0x380(%RSP),%YMM27 |
(119) 0x424c22 VMOVAPD %YMM31,%YMM27{%K1} |
(119) 0x424c28 VMOVAPD 0x3a0(%RSP),%YMM26 |
(119) 0x424c30 VMOVAPD %YMM1,%YMM26{%K1} |
(119) 0x424c36 VMOVAPD %YMM4,%YMM17{%K1} |
(119) 0x424c3c VMOVAPD %YMM5,%YMM16{%K1} |
(119) 0x424c42 VMOVAPD %YMM18,%YMM15{%K1} |
(119) 0x424c48 VMOVAPD %YMM19,%YMM14{%K1} |
(119) 0x424c4e VMOVAPD %YMM20,%YMM13{%K1} |
(119) 0x424c54 VSUBPD %YMM16,%YMM15,%YMM1 |
(119) 0x424c5a VMULPD %YMM17,%YMM1,%YMM1 |
(119) 0x424c60 VMOVAPD 0x240(%RSP),%YMM5 |
(119) 0x424c69 VMOVAPD %YMM21,%YMM5{%K1} |
(119) 0x424c6f VSUBPD %YMM13,%YMM5,%YMM2 |
(119) 0x424c74 VFMADD213PD %YMM1,%YMM14,%YMM2 |
(119) 0x424c79 VMOVAPD 0x300(%RSP),%YMM20 |
(119) 0x424c81 VMOVAPD %YMM24,%YMM20{%K1} |
(119) 0x424c87 VMOVAPD 0x3c0(%RSP),%YMM19 |
(119) 0x424c8f VMOVAPD %YMM25,%YMM19{%K1} |
(119) 0x424c95 VMOVAPD 0x3e0(%RSP),%YMM18 |
(119) 0x424c9d VMOVAPD %YMM7,%YMM18{%K1} |
(119) 0x424ca3 VMOVAPD 0x400(%RSP),%YMM7 |
(119) 0x424cac VMOVAPD %YMM6,%YMM7{%K1} |
(119) 0x424cb2 VSUBPD %YMM20,%YMM19,%YMM1 |
(119) 0x424cb8 VFMADD213PD %YMM2,%YMM17,%YMM1 |
(119) 0x424cbe VSUBPD %YMM18,%YMM7,%YMM2 |
(119) 0x424cc4 VFMADD231PD %YMM2,%YMM14,%YMM1 |
(119) 0x424cc9 VMOVAPD %YMM11,0x2a0(%RSP) |
(119) 0x424cd2 VMOVAPD %YMM12,0x260(%RSP) |
(119) 0x424cdb VMULPD %YMM11,%YMM12,%YMM2 |
(119) 0x424ce0 VMOVAPD %YMM9,0x320(%RSP) |
(119) 0x424ce9 VMOVAPD %YMM10,0x2e0(%RSP) |
(119) 0x424cf2 VFMADD231PD %YMM9,%YMM10,%YMM2 |
(119) 0x424cf7 VMOVAPD %YMM28,0x360(%RSP) |
(119) 0x424cff VMOVAPD %YMM29,0x340(%RSP) |
(119) 0x424d07 VFMADD231PD %YMM28,%YMM29,%YMM2 |
(119) 0x424d0d VMOVAPD %YMM26,0x3a0(%RSP) |
(119) 0x424d15 VMOVAPD %YMM27,0x380(%RSP) |
(119) 0x424d1d VFMADD231PD %YMM26,%YMM27,%YMM2 |
(119) 0x424d23 VMULPD %YMM3,%YMM2,%YMM2 |
(119) 0x424d27 VDIVPD %YMM2,%YMM0,%YMM2 |
(119) 0x424d2b VMOVAPD 0x420(%RSP),%YMM4 |
(119) 0x424d34 VMOVAPD %YMM8,%YMM4{%K1} |
(119) 0x424d3a VMOVAPD %YMM4,0x420(%RSP) |
(119) 0x424d43 VFMADD213PD %YMM4,%YMM2,%YMM1 |
(119) 0x424d48 ADD 0x60(%RSP),%RDI |
(119) 0x424d4d VMOVUPD %YMM1,(%RDI,%RAX,8){%K1} |
(119) 0x424d54 ADD 0x68(%RSP),%RBX |
(119) 0x424d59 VMOVUPD (%RBX,%RAX,8),%YMM1{%K1}{z} |
(119) 0x424d60 VMOVAPD 0x280(%RSP),%YMM9 |
(119) 0x424d69 VMOVAPD %YMM22,%YMM9{%K1} |
(119) 0x424d6f VSUBPD %YMM16,%YMM13,%YMM4 |
(119) 0x424d75 VMULPD %YMM4,%YMM9,%YMM4 |
(119) 0x424d79 VMOVAPD 0x2c0(%RSP),%YMM8 |
(119) 0x424d82 VMOVAPD %YMM23,%YMM8{%K1} |
(119) 0x424d88 VMOVAPD %YMM5,0x240(%RSP) |
(119) 0x424d91 VSUBPD %YMM15,%YMM5,%YMM5 |
(119) 0x424d96 VFMADD213PD %YMM4,%YMM8,%YMM5 |
(119) 0x424d9b VMOVAPD %YMM18,0x3e0(%RSP) |
(119) 0x424da3 VMOVAPD %YMM20,0x300(%RSP) |
(119) 0x424dab VSUBPD %YMM20,%YMM18,%YMM4 |
(119) 0x424db1 VMOVAPD %YMM7,0x400(%RSP) |
(119) 0x424dba VMOVAPD %YMM19,0x3c0(%RSP) |
(119) 0x424dc2 VSUBPD %YMM19,%YMM7,%YMM6 |
(119) 0x424dc8 VMOVAPD %YMM9,0x280(%RSP) |
(119) 0x424dd1 VFMADD213PD %YMM5,%YMM9,%YMM4 |
(119) 0x424dd6 VMOVAPD %YMM8,0x2c0(%RSP) |
(119) 0x424ddf VFMADD231PD %YMM6,%YMM8,%YMM4 |
(119) 0x424de4 VMOVAPD 0x440(%RSP),%YMM5 |
(119) 0x424ded VMOVAPD %YMM1,%YMM5{%K1} |
(119) 0x424df3 VMOVAPD %YMM5,0x440(%RSP) |
(119) 0x424dfc VFMADD213PD %YMM5,%YMM2,%YMM4 |
(119) 0x424e01 ADD 0xa8(%RSP),%R11 |
(119) 0x424e09 VMOVUPD %YMM4,(%R11,%RAX,8){%K1} |
(119) 0x424e10 LEA 0x1(%R13),%EAX |
(119) 0x424e14 INC %R15D |
(119) 0x424e17 CMP %R12D,%R13D |
(119) 0x424e1a MOV %EAX,%R13D |
(119) 0x424e1d JE 424746 |
(119) 0x424e23 CMPL $0,0x54(%RSP) |
(119) 0x424e28 JS 424e10 |
(119) 0x424e2a MOV 0x190(%RSP),%RAX |
(119) 0x424e32 LEA (%RAX,%R13,1),%ESI |
(119) 0x424e36 MOV 0x198(%RSP),%RAX |
(119) 0x424e3e MOV (%RAX),%R8 |
(119) 0x424e41 MOV 0x1a0(%RSP),%RAX |
(119) 0x424e49 MOV (%RAX),%RCX |
(119) 0x424e4c MOV 0x1a8(%RSP),%RAX |
(119) 0x424e54 MOV (%RAX),%RAX |
(119) 0x424e57 MOV %RAX,0x18(%RSP) |
(119) 0x424e5c MOV 0x1b0(%RSP),%RAX |
(119) 0x424e64 MOV (%RAX),%RDX |
(119) 0x424e67 MOV 0x1b8(%RSP),%RAX |
(119) 0x424e6f MOV (%RAX),%R10 |
(119) 0x424e72 MOV 0x1c0(%RSP),%RAX |
(119) 0x424e7a MOV (%RAX),%RAX |
(119) 0x424e7d MOV %RAX,0x10(%RSP) |
(119) 0x424e82 MOV 0x1c8(%RSP),%RAX |
(119) 0x424e8a MOV (%RAX),%RAX |
(119) 0x424e8d MOV %RAX,0x38(%RSP) |
(119) 0x424e92 MOV 0x1d0(%RSP),%RAX |
(119) 0x424e9a MOV (%RAX),%RBX |
(119) 0x424e9d MOV 0x1d8(%RSP),%RAX |
(119) 0x424ea5 MOV (%RAX),%RAX |
(119) 0x424ea8 MOV %RAX,0x8(%RSP) |
(119) 0x424ead MOV 0x1e0(%RSP),%RAX |
(119) 0x424eb5 MOV (%RAX),%R11 |
(119) 0x424eb8 CMPQ $0,0x20(%RSP) |
(119) 0x424ebe MOV %R13,0x108(%RSP) |
(119) 0x424ec6 JE 424980 |
(119) 0x424ecc MOV %R15D,0x50(%RSP) |
(119) 0x424ed1 MOVSXD %R15D,%R15 |
(119) 0x424ed4 MOV 0xb0(%RSP),%RDI |
(119) 0x424edc LEA (%RDI,%R15,1),%RAX |
(119) 0x424ee0 ADD 0x168(%RSP),%R15 |
(119) 0x424ee8 MOVSXD %ESI,%RSI |
(119) 0x424eeb ADD %RSI,%RDI |
(119) 0x424eee MOV %RCX,%R12 |
(119) 0x424ef1 MOV %RCX,%R9 |
(119) 0x424ef4 IMUL %RDI,%R9 |
(119) 0x424ef8 MOV %R9,0xd0(%RSP) |
(119) 0x424f00 MOV %R8,%R9 |
(119) 0x424f03 IMUL %RDI,%R9 |
(119) 0x424f07 MOV %R9,0xd8(%RSP) |
(119) 0x424f0f SUB 0xb8(%RSP),%RSI |
(119) 0x424f17 MOV %RCX,%R9 |
(119) 0x424f1a IMUL %RSI,%R9 |
(119) 0x424f1e MOV %R9,0xc0(%RSP) |
(119) 0x424f26 MOV %R8,%R9 |
(119) 0x424f29 IMUL %RSI,%R9 |
(119) 0x424f2d MOV %R9,0xc8(%RSP) |
(119) 0x424f35 MOV %RDX,0x40(%RSP) |
(119) 0x424f3a MOV %RDX,%R9 |
(119) 0x424f3d IMUL %RSI,%R9 |
(119) 0x424f41 MOV %R9,0xe0(%RSP) |
(119) 0x424f49 MOV %R10,%R9 |
(119) 0x424f4c IMUL %RSI,%R9 |
(119) 0x424f50 MOV %R9,0xe8(%RSP) |
(119) 0x424f58 MOV %RDX,%R9 |
(119) 0x424f5b IMUL %RDI,%R9 |
(119) 0x424f5f MOV %R9,0x1f0(%RSP) |
(119) 0x424f67 MOV %R10,%R9 |
(119) 0x424f6a IMUL %RDI,%R9 |
(119) 0x424f6e MOV %R9,0x1f8(%RSP) |
(119) 0x424f76 MOV %RBX,%R9 |
(119) 0x424f79 MOV %RBX,%RDX |
(119) 0x424f7c IMUL %RSI,%R9 |
(119) 0x424f80 MOV %R9,0x200(%RSP) |
(119) 0x424f88 MOV %R11,%R9 |
(119) 0x424f8b IMUL %RSI,%R9 |
(119) 0x424f8f MOV %R9,0xf8(%RSP) |
(119) 0x424f97 IMUL %R11,%RDI |
(119) 0x424f9b MOV %RDI,0x100(%RSP) |
(119) 0x424fa3 MOV 0x18(%RSP),%RDI |
(119) 0x424fa8 IMUL %RSI,%RDI |
(119) 0x424fac MOV %RDI,0xf0(%RSP) |
(119) 0x424fb4 MOV 0x10(%RSP),%RDI |
(119) 0x424fb9 IMUL %RSI,%RDI |
(119) 0x424fbd MOV %RDI,0x208(%RSP) |
(119) 0x424fc5 MOV 0x38(%RSP),%RBX |
(119) 0x424fca MOV %RBX,%RDI |
(119) 0x424fcd IMUL %RSI,%RDI |
(119) 0x424fd1 MOV %RDI,0x210(%RSP) |
(119) 0x424fd9 MOV 0x8(%RSP),%R13 |
(119) 0x424fde IMUL %R13,%RSI |
(119) 0x424fe2 MOV %RSI,0x218(%RSP) |
(119) 0x424fea MOV %RCX,%RDI |
(119) 0x424fed IMUL %RAX,%RDI |
(119) 0x424ff1 MOV %R8,%R14 |
(119) 0x424ff4 IMUL %RAX,%R14 |
(119) 0x424ff8 MOV %R15,%RCX |
(119) 0x424ffb IMUL %R15,%R12 |
(119) 0x424fff IMUL %R15,%R8 |
(119) 0x425003 MOV %R10,%R15 |
(119) 0x425006 IMUL %RCX,%R15 |
(119) 0x42500a IMUL %RAX,%R10 |
(119) 0x42500e IMUL %RCX,%RDX |
(119) 0x425012 MOV %RDX,0x1e8(%RSP) |
(119) 0x42501a MOV %R11,%R9 |
(119) 0x42501d IMUL %RCX,%R9 |
(119) 0x425021 IMUL %RAX,%R11 |
(119) 0x425025 IMUL %RCX,%R13 |
(119) 0x425029 IMUL %RCX,%RBX |
(119) 0x42502d MOV 0x10(%RSP),%RSI |
(119) 0x425032 IMUL %RCX,%RSI |
(119) 0x425036 MOV %RSI,0x10(%RSP) |
(119) 0x42503b MOV 0x18(%RSP),%RSI |
(119) 0x425040 IMUL %RCX,%RSI |
(119) 0x425044 MOV %RSI,0x18(%RSP) |
(119) 0x425049 MOV 0x40(%RSP),%RSI |
(119) 0x42504e IMUL %RSI,%RAX |
(119) 0x425052 IMUL %RSI,%RCX |
(119) 0x425056 MOV 0x158(%RSP),%RDX |
(119) 0x42505e ADD %RDX,%RDI |
(119) 0x425061 MOV 0x150(%RSP),%RSI |
(119) 0x425069 ADD %RSI,%R14 |
(119) 0x42506c ADD %RDX,%R12 |
(119) 0x42506f MOV %R12,0x8(%RSP) |
(119) 0x425074 ADD %RSI,%R8 |
(119) 0x425077 MOV %R8,0x38(%RSP) |
(119) 0x42507c MOV 0x148(%RSP),%RSI |
(119) 0x425084 ADD %RSI,%R15 |
(119) 0x425087 ADD %RSI,%R10 |
(119) 0x42508a MOV %R10,0x40(%RSP) |
(119) 0x42508f MOV 0x1e8(%RSP),%RDX |
(119) 0x425097 ADD 0x140(%RSP),%RDX |
(119) 0x42509f MOV 0x138(%RSP),%RSI |
(119) 0x4250a7 ADD %RSI,%R9 |
(119) 0x4250aa ADD %RSI,%R11 |
(119) 0x4250ad MOV %R11,%R10 |
(119) 0x4250b0 ADD 0x130(%RSP),%R13 |
(119) 0x4250b8 MOV %R13,%R12 |
(119) 0x4250bb ADD 0x128(%RSP),%RBX |
(119) 0x4250c3 MOV %RBX,%R13 |
(119) 0x4250c6 MOV 0x10(%RSP),%R11 |
(119) 0x4250cb ADD 0x120(%RSP),%R11 |
(119) 0x4250d3 MOV 0x18(%RSP),%RBX |
(119) 0x4250d8 ADD 0x118(%RSP),%RBX |
(119) 0x4250e0 MOV 0x160(%RSP),%RSI |
(119) 0x4250e8 ADD %RSI,%RAX |
(119) 0x4250eb ADD %RSI,%RCX |
(119) 0x4250ee XOR %ESI,%ESI |
(120) 0x4250f0 VMOVUPD -0x8(%RDI,%RSI,8),%YMM1 |
(120) 0x4250f6 VMOVUPD (%RDI,%RSI,8),%YMM2 |
(120) 0x4250fb VMULPD -0x8(%R14,%RSI,8),%YMM1,%YMM1 |
(120) 0x425102 VFMADD231PD (%R14,%RSI,8),%YMM2,%YMM1 |
(120) 0x425108 MOV 0x8(%RSP),%R8 |
(120) 0x42510d VMOVUPD -0x8(%R8,%RSI,8),%YMM2 |
(120) 0x425114 VMOVUPD (%R8,%RSI,8),%YMM4 |
(120) 0x42511a MOV 0x38(%RSP),%R8 |
(120) 0x42511f VFMADD132PD (%R8,%RSI,8),%YMM1,%YMM4 |
(120) 0x425125 VFMADD231PD -0x8(%R8,%RSI,8),%YMM2,%YMM4 |
(120) 0x42512c VMULPD %YMM3,%YMM4,%YMM1 |
(120) 0x425130 VDIVPD %YMM1,%YMM0,%YMM1 |
(120) 0x425134 VMOVUPD (%RCX,%RSI,8),%YMM2 |
(120) 0x425139 VMOVUPD -0x8(%R15,%RSI,8),%YMM4 |
(120) 0x425140 VMOVUPD (%R15,%RSI,8),%YMM5 |
(120) 0x425146 VSUBPD %YMM5,%YMM4,%YMM6 |
(120) 0x42514a VMULPD %YMM2,%YMM6,%YMM6 |
(120) 0x42514e VMOVUPD (%RAX,%RSI,8),%YMM7 |
(120) 0x425153 MOV 0x40(%RSP),%R8 |
(120) 0x425158 VMOVUPD -0x8(%R8,%RSI,8),%YMM8 |
(120) 0x42515f VMOVUPD (%R8,%RSI,8),%YMM18 |
(120) 0x425166 VSUBPD %YMM18,%YMM8,%YMM19 |
(120) 0x42516c VFMADD213PD %YMM6,%YMM7,%YMM19 |
(120) 0x425172 MOV %RDX,%R8 |
(120) 0x425175 VMOVUPD -0x8(%RDX,%RSI,8),%YMM6 |
(120) 0x42517b VMOVUPD (%RDX,%RSI,8),%YMM20 |
(120) 0x425182 VSUBPD %YMM5,%YMM18,%YMM5 |
(120) 0x425188 VMULPD %YMM5,%YMM20,%YMM5 |
(120) 0x42518e VSUBPD %YMM4,%YMM8,%YMM4 |
(120) 0x425192 VFMADD213PD %YMM5,%YMM6,%YMM4 |
(120) 0x425197 VMOVUPD -0x8(%R9,%RSI,8),%YMM5 |
(120) 0x42519e VMOVUPD (%R9,%RSI,8),%YMM8 |
(120) 0x4251a4 MOV %R10,%R8 |
(120) 0x4251a7 VMOVUPD -0x8(%R10,%RSI,8),%YMM18 |
(120) 0x4251b2 VMOVUPD (%R10,%RSI,8),%YMM21 |
(120) 0x4251b9 VSUBPD %YMM8,%YMM5,%YMM22 |
(120) 0x4251bf VSUBPD %YMM21,%YMM18,%YMM23 |
(120) 0x4251c5 VFMADD213PD %YMM19,%YMM2,%YMM22 |
(120) 0x4251cb VFMADD231PD %YMM23,%YMM7,%YMM22 |
(120) 0x4251d1 VFMADD213PD (%RBX,%RSI,8),%YMM1,%YMM22 |
(120) 0x4251d8 VMOVUPD %YMM22,(%R11,%RSI,8) |
(120) 0x4251df VSUBPD %YMM8,%YMM21,%YMM2 |
(120) 0x4251e5 VSUBPD %YMM5,%YMM18,%YMM5 |
(120) 0x4251eb VFMADD213PD %YMM4,%YMM20,%YMM2 |
(120) 0x4251f1 VFMADD231PD %YMM5,%YMM6,%YMM2 |
(120) 0x4251f6 VFMADD213PD (%R13,%RSI,8),%YMM1,%YMM2 |
(120) 0x4251fd VMOVUPD %YMM2,(%R12,%RSI,8) |
(120) 0x425203 ADD $0x4,%RSI |
(120) 0x425207 CMP 0x20(%RSP),%RSI |
(120) 0x42520c JB 4250f0 |
(119) 0x425212 MOV 0x20(%RSP),%RCX |
(119) 0x425217 MOV %RCX,%RAX |
(119) 0x42521a CMP 0x170(%RSP),%RCX |
(119) 0x425222 MOV 0x2c(%RSP),%R12D |
(119) 0x425227 MOV 0x50(%RSP),%R15D |
(119) 0x42522c MOV 0x108(%RSP),%R13 |
(119) 0x425234 MOV 0x218(%RSP),%R11 |
(119) 0x42523c MOV 0x210(%RSP),%RBX |
(119) 0x425244 MOV 0x208(%RSP),%RDI |
(119) 0x42524c MOV 0x200(%RSP),%R9 |
(119) 0x425254 MOV 0x1f8(%RSP),%R10 |
(119) 0x42525c MOV 0x1f0(%RSP),%R14 |
(119) 0x425264 JNE 424a5e |
(119) 0x42526a JMP 424e10 |
0x42526f NOP |
Path / |
Source file and lines | accelerate_kernel.f90:57-79 |
Module | exec |
nb instructions | 202 |
nb uops | 205 |
loop length | 993 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 3 |
used zmm registers | 0 |
nb stack references | 76 |
micro-operation queue | 34.17 cycles |
front end | 34.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.40 | 12.40 | 16.67 | 16.67 | 30.50 | 12.40 | 12.40 | 30.50 | 30.50 | 30.50 | 12.40 | 16.67 |
cycles | 12.40 | 12.40 | 16.67 | 16.67 | 30.50 | 12.40 | 12.40 | 30.50 | 30.50 | 30.50 | 12.40 | 16.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 33.83 |
Stall cycles | 0.00 |
Front-end | 34.17 |
Dispatch | 30.50 |
Overall L1 | 34.17 |
all | 2% |
load | 0% |
store | 2% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 3% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 2% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 3% |
all | 11% |
load | 11% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 11% |
load | 11% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x480,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1e0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1d8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1d0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1c8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1b8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x1b0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x1a8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x1a0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x198(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 42475f <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x1bf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x34(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x60(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x64(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3c(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x38(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x536290,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 404670 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x34(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RSP),%R12D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EAX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 424779 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x1d9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x5362b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x4c(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 404230 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x110(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x5362d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 404740 <__kmpc_barrier@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVQ %R14,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %R15,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x20,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $-0x200000000,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
LEA (%R9,%RAX,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x20,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %EBX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD (%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RDX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ESI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %EDX,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7ffffffc,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $-0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNS %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RSI,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x200000000,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R9,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RDI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RCX,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOT %R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %XMM0,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %R15,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQA %YMM1,0x220(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
SHR $0x20,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RDX,%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RBX,0x180(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RBX,8),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x3,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SUB %RDI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x1,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %RAX,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVG %RSI,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x188(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOT %R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R14,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R13,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RAX,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RCX,%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NEG %R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R13,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0xa0(%RSP),%R11 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R11,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD 0xd1101(%RIP),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,0x190(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 424e23 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x883> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | accelerate_kernel.f90:57-79 |
Module | exec |
nb instructions | 202 |
nb uops | 205 |
loop length | 993 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 3 |
used zmm registers | 0 |
nb stack references | 76 |
micro-operation queue | 34.17 cycles |
front end | 34.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.40 | 12.40 | 16.67 | 16.67 | 30.50 | 12.40 | 12.40 | 30.50 | 30.50 | 30.50 | 12.40 | 16.67 |
cycles | 12.40 | 12.40 | 16.67 | 16.67 | 30.50 | 12.40 | 12.40 | 30.50 | 30.50 | 30.50 | 12.40 | 16.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 33.83 |
Stall cycles | 0.00 |
Front-end | 34.17 |
Dispatch | 30.50 |
Overall L1 | 34.17 |
all | 2% |
load | 0% |
store | 2% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 3% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 2% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 3% |
all | 11% |
load | 11% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 11% |
load | 11% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x480,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1e0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1d8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1d0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1c8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x1b8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x1b0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x1a8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x1a0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x198(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 42475f <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x1bf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x34(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x60(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x64(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3c(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x38(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x536290,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 404670 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x34(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RSP),%R12D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EAX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 424779 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x1d9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x5362b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x4c(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 404230 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x110(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x5362d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 404740 <__kmpc_barrier@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVQ %R14,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %R15,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x20,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $-0x200000000,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
LEA (%R9,%RAX,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x20,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %EBX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD (%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RDX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ESI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %EDX,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7ffffffc,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $-0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNS %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RSI,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x200000000,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R9,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RDI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RCX,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOT %R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %XMM0,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %R15,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQA %YMM1,0x220(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
SHR $0x20,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RDX,%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RBX,0x180(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RBX,8),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x3,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SUB %RDI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x1,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %RAX,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVG %RSI,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x188(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOT %R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R14,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R13,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RAX,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RCX,%R13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NEG %R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R13,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0xa0(%RSP),%R11 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R11,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD 0xd1101(%RIP),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,0x190(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 424e23 <accelerate_kernel_module_mp_accelerate_kernel_.DIR.OMP.PARALLEL.2+0x883> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼accelerate_kernel_.DIR.OMP.PARALLEL.2– | 4.89 | 1.66 |
▼Loop 119 - accelerate_kernel.f90:60-76 - exec– | 0 | 0 |
○Loop 120 - accelerate_kernel.f90:62-76 - exec | 4.89 | 1.65 |