Loop Id: 101 | Module: exec | Source: advec_mom_kernel.f90:248-248 | Coverage: 3.61% |
---|
Loop Id: 101 | Module: exec | Source: advec_mom_kernel.f90:248-248 | Coverage: 3.61% |
---|
0x41e2af VMOVUPD (%R11,%RAX,1),%YMM11 [5] |
0x41e2b5 VMOVUPD (%RSI,%RAX,1),%YMM10 [4] |
0x41e2ba VMOVUPD 0x20(%RSI,%RAX,1),%YMM15 [4] |
0x41e2c0 VMOVUPD 0x40(%RSI,%RAX,1),%YMM3 [4] |
0x41e2c6 VFMSUB132PD (%RBX,%RAX,1),%YMM11,%YMM10 [2] |
0x41e2cc VMOVUPD 0x60(%RSI,%RAX,1),%YMM6 [4] |
0x41e2d2 VADDPD (%R10,%RAX,1),%YMM10,%YMM12 [3] |
0x41e2d8 VDIVPD (%R8,%RAX,1),%YMM12,%YMM13 [1] |
0x41e2de VMOVUPD %YMM13,(%RSI,%RAX,1) [4] |
0x41e2e3 VMOVUPD 0x20(%R11,%RAX,1),%YMM1 [5] |
0x41e2ea VFMSUB132PD 0x20(%RBX,%RAX,1),%YMM1,%YMM15 [2] |
0x41e2f1 VADDPD 0x20(%R10,%RAX,1),%YMM15,%YMM5 [3] |
0x41e2f8 VDIVPD 0x20(%R8,%RAX,1),%YMM5,%YMM14 [1] |
0x41e2ff VMOVUPD %YMM14,0x20(%RSI,%RAX,1) [4] |
0x41e305 VMOVUPD 0x40(%R11,%RAX,1),%YMM8 [5] |
0x41e30c VFMSUB132PD 0x40(%RBX,%RAX,1),%YMM8,%YMM3 [2] |
0x41e313 VADDPD 0x40(%R10,%RAX,1),%YMM3,%YMM2 [3] |
0x41e31a VDIVPD 0x40(%R8,%RAX,1),%YMM2,%YMM0 [1] |
0x41e321 VMOVUPD %YMM0,0x40(%RSI,%RAX,1) [4] |
0x41e327 VMOVUPD 0x60(%R11,%RAX,1),%YMM7 [5] |
0x41e32e VFMSUB132PD 0x60(%RBX,%RAX,1),%YMM7,%YMM6 [2] |
0x41e335 VADDPD 0x60(%R10,%RAX,1),%YMM6,%YMM4 [3] |
0x41e33c VDIVPD 0x60(%R8,%RAX,1),%YMM4,%YMM9 [1] |
0x41e343 VMOVUPD %YMM9,0x60(%RSI,%RAX,1) [4] |
0x41e349 SUB $-0x80,%RAX |
0x41e34d CMP %RDI,%RAX |
0x41e350 JNE 41e2af |
/home/eoseret/qaas_runs_CPU_9468/171-137-7698/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 248 - 248 |
-------------------------------------------------------------------------------- |
248: vel1 (j,k)=(vel1(j,k)*node_mass_pre(j,k)+mom_flux(j,k-1)-mom_flux(j,k))/node_mass_post(j,k) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 4.80 |
Bottlenecks | P0, |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source | advec_mom_kernel.f90:248-248 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 |
CQA cycles if no scalar integer | 32.00 |
CQA cycles if FP arith vectorized | 32.00 |
CQA cycles if fully vectorized | 32.00 |
Front-end cycles | 6.33 |
DIV/SQRT cycles | 4.00 |
P0 cycles | 4.00 |
P1 cycles | 6.67 |
P2 cycles | 6.67 |
P3 cycles | 2.00 |
P4 cycles | 4.00 |
P5 cycles | 1.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 0.00 |
P10 cycles | 6.67 |
P11 cycles | 32.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 32.26 - 32.28 |
Stall cycles (UFS) | 25.32 - 25.34 |
Nb insns | 27.00 |
Nb uops | 26.00 |
Nb loads | 20.00 |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 16.00 |
Nb FLOP div | 16.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 640.00 |
Bytes stored | 128.00 |
Stride 0 | 0.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 50.00 |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 4.80 |
Bottlenecks | P0, |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source | advec_mom_kernel.f90:248-248 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 |
CQA cycles if no scalar integer | 32.00 |
CQA cycles if FP arith vectorized | 32.00 |
CQA cycles if fully vectorized | 32.00 |
Front-end cycles | 6.33 |
DIV/SQRT cycles | 4.00 |
P0 cycles | 4.00 |
P1 cycles | 6.67 |
P2 cycles | 6.67 |
P3 cycles | 2.00 |
P4 cycles | 4.00 |
P5 cycles | 1.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 0.00 |
P10 cycles | 6.67 |
P11 cycles | 32.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 32.26 - 32.28 |
Stall cycles (UFS) | 25.32 - 25.34 |
Nb insns | 27.00 |
Nb uops | 26.00 |
Nb loads | 20.00 |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 16.00 |
Nb FLOP div | 16.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 640.00 |
Bytes stored | 128.00 |
Stride 0 | 0.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 50.00 |
Vector-efficiency ratio other | NA |
Path / |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source file and lines | advec_mom_kernel.f90:248-248 |
Module | exec |
nb instructions | 27 |
nb uops | 26 |
loop length | 167 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 16 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.33 cycles |
front end | 6.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.00 | 4.00 | 6.67 | 6.67 | 2.00 | 4.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.67 |
cycles | 4.00 | 4.00 | 6.67 | 6.67 | 2.00 | 4.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.67 |
Cycles executing div or sqrt instructions | 32.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 32.26-32.28 |
Stall cycles | 25.32-25.34 |
LB full (events) | 29.58-29.60 |
LM full (events) | 0.13-0.12 |
Front-end | 6.33 |
Dispatch | 6.67 |
DIV/SQRT | 32.00 |
Data deps. | 1.00 |
Overall L1 | 32.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | 50% |
div/sqrt | 50% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R11,%RAX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%RSI,%RAX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x20(%RSI,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x40(%RSI,%RAX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMSUB132PD (%RBX,%RAX,1),%YMM11,%YMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVUPD 0x60(%RSI,%RAX,1),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPD (%R10,%RAX,1),%YMM10,%YMM12 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD (%R8,%RAX,1),%YMM12,%YMM13 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
VMOVUPD %YMM13,(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x20(%R11,%RAX,1),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMSUB132PD 0x20(%RBX,%RAX,1),%YMM1,%YMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x20(%R10,%RAX,1),%YMM15,%YMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD 0x20(%R8,%RAX,1),%YMM5,%YMM14 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
VMOVUPD %YMM14,0x20(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x40(%R11,%RAX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMSUB132PD 0x40(%RBX,%RAX,1),%YMM8,%YMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x40(%R10,%RAX,1),%YMM3,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD 0x40(%R8,%RAX,1),%YMM2,%YMM0 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
VMOVUPD %YMM0,0x40(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x60(%R11,%RAX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMSUB132PD 0x60(%RBX,%RAX,1),%YMM7,%YMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x60(%R10,%RAX,1),%YMM6,%YMM4 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD 0x60(%R8,%RAX,1),%YMM4,%YMM9 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
VMOVUPD %YMM9,0x60(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 41e2af <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1cff> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source file and lines | advec_mom_kernel.f90:248-248 |
Module | exec |
nb instructions | 27 |
nb uops | 26 |
loop length | 167 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 16 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.33 cycles |
front end | 6.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.00 | 4.00 | 6.67 | 6.67 | 2.00 | 4.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.67 |
cycles | 4.00 | 4.00 | 6.67 | 6.67 | 2.00 | 4.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.67 |
Cycles executing div or sqrt instructions | 32.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 32.26-32.28 |
Stall cycles | 25.32-25.34 |
LB full (events) | 29.58-29.60 |
LM full (events) | 0.13-0.12 |
Front-end | 6.33 |
Dispatch | 6.67 |
DIV/SQRT | 32.00 |
Data deps. | 1.00 |
Overall L1 | 32.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | 50% |
div/sqrt | 50% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R11,%RAX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%RSI,%RAX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x20(%RSI,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x40(%RSI,%RAX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMSUB132PD (%RBX,%RAX,1),%YMM11,%YMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVUPD 0x60(%RSI,%RAX,1),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPD (%R10,%RAX,1),%YMM10,%YMM12 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD (%R8,%RAX,1),%YMM12,%YMM13 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
VMOVUPD %YMM13,(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x20(%R11,%RAX,1),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMSUB132PD 0x20(%RBX,%RAX,1),%YMM1,%YMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x20(%R10,%RAX,1),%YMM15,%YMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD 0x20(%R8,%RAX,1),%YMM5,%YMM14 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
VMOVUPD %YMM14,0x20(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x40(%R11,%RAX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMSUB132PD 0x40(%RBX,%RAX,1),%YMM8,%YMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x40(%R10,%RAX,1),%YMM3,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD 0x40(%R8,%RAX,1),%YMM2,%YMM0 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
VMOVUPD %YMM0,0x40(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x60(%R11,%RAX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMSUB132PD 0x60(%RBX,%RAX,1),%YMM7,%YMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x60(%R10,%RAX,1),%YMM6,%YMM4 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD 0x60(%R8,%RAX,1),%YMM4,%YMM9 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 8 |
VMOVUPD %YMM9,0x60(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 41e2af <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1cff> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |