Function: __pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0 | Module: exec | Source: pack_kernel.f90:202-207 | Coverage: 0.03% |
---|
Function: __pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0 | Module: exec | Source: pack_kernel.f90:202-207 | Coverage: 0.03% |
---|
/scratch_na/users/xoserete/qaas_runs/171-214-9740/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/pack_kernel.f90: 202 - 207 |
-------------------------------------------------------------------------------- |
202: !$OMP PARALLEL DO PRIVATE(index) |
203: DO k=y_min-depth,y_max+y_inc+depth |
204: !$OMP SIMD |
205: DO j=1,depth |
206: index= buffer_offset + j+(k+depth-1)*depth |
207: field(x_max+x_inc+j,k)=right_rcv_buffer(index) |
0x432de0 PUSH %RBP |
0x432de1 MOV %RSP,%RBP |
0x432de4 PUSH %R15 |
0x432de6 PUSH %R14 |
0x432de8 PUSH %R13 |
0x432dea PUSH %R12 |
0x432dec PUSH %RBX |
0x432ded AND $-0x20,%RSP |
0x432df1 SUB $0xc0,%RSP |
0x432df8 MOV 0x30(%RDI),%RDX |
0x432dfc MOV 0x54(%RDI),%EAX |
0x432dff MOV %RDI,0xb8(%RSP) |
0x432e07 MOV 0x28(%RDI),%RCX |
0x432e0b MOV 0x58(%RDI),%R15D |
0x432e0f MOV 0x48(%RDI),%R12 |
0x432e13 MOV 0x40(%RDI),%R13 |
0x432e17 MOV %RDX,0xb0(%RSP) |
0x432e1f MOV %RCX,0xa8(%RSP) |
0x432e27 MOV 0x20(%RDI),%R14 |
0x432e2b MOV %EAX,0xa4(%RSP) |
0x432e32 CALL 402080 <@plt_start@+0x60> |
0x432e37 MOV %EAX,%EBX |
0x432e39 CALL 402180 <@plt_start@+0x160> |
0x432e3e MOV 0xb8(%RSP),%R10 |
0x432e46 MOV %EAX,%ESI |
0x432e48 MOV 0x5c(%R10),%EAX |
0x432e4c INC %EAX |
0x432e4e SUB %R15D,%EAX |
0x432e51 CLTD |
0x432e52 IDIV %EBX |
0x432e54 CMP %EDX,%ESI |
0x432e56 JL 43323d |
0x432e5c IMUL %EAX,%ESI |
0x432e5f ADD %EDX,%ESI |
0x432e61 ADD %ESI,%EAX |
0x432e63 CMP %EAX,%ESI |
0x432e65 JGE 4331d3 |
0x432e6b ADD %R15D,%EAX |
0x432e6e MOV 0x8(%R10),%R8 |
0x432e72 CMP $0x1,%R14 |
0x432e76 LEA (%R15,%RSI,1),%EDI |
0x432e7a SETNE %R15B |
0x432e7e CMP $0x1,%R13 |
0x432e82 MOV 0x10(%R10),%R9 |
0x432e86 MOV (%R10),%R11 |
0x432e89 MOV (%R8),%EBX |
0x432e8c SETNE %CL |
0x432e8f MOV 0x38(%R10),%R8 |
0x432e93 MOV %EAX,0xa0(%RSP) |
0x432e9a OR %CL,%R15B |
0x432e9d MOV %R9,0x90(%RSP) |
0x432ea5 MOV 0x18(%R10),%R9 |
0x432ea9 MOV %EDI,0xb8(%RSP) |
0x432eb0 LEA -0x1(%RBX),%EAX |
0x432eb3 MOV %R11,0x88(%RSP) |
0x432ebb MOV %R15B,0x83(%RSP) |
0x432ec3 JNE 433246 |
0x432ec9 MOV 0xb8(%RSP),%R13D |
0x432ed1 MOV 0xa8(%RSP),%R11 |
0x432ed9 MOV %EBX,%R15D |
0x432edc MOV %EBX,%ECX |
0x432ede MOV 0xb0(%RSP),%RSI |
0x432ee6 AND $-0x4,%ECX |
0x432ee9 SHR $0x2,%R15D |
0x432eed MOV %EAX,0x84(%RSP) |
0x432ef4 MOVSXD %R13D,%R14 |
0x432ef7 LEA (%R13,%RAX,1),%EDI |
0x432efc SAL $0x5,%R15 |
0x432f00 XOR %EAX,%EAX |
0x432f02 IMUL %R11,%R14 |
0x432f06 MOV %ECX,0x78(%RSP) |
0x432f0a INC %ECX |
0x432f0c MOVSXD 0xa4(%RSP),%RDX |
0x432f14 IMUL %EBX,%EDI |
0x432f17 LEA 0x1(%R12),%R13 |
0x432f1c MOV %R15,0xb0(%RSP) |
0x432f24 MOV %RDX,0x98(%RSP) |
0x432f2c ADD %R14,%RSI |
0x432f2f TEST %EBX,%EBX |
0x432f31 MOV %ECX,0x60(%RSP) |
0x432f35 CMOVNS %EBX,%EAX |
0x432f38 INC %RDX |
0x432f3b MOV %R13,0x70(%RSP) |
0x432f40 MOV %RDX,0x68(%RSP) |
0x432f45 INC %EAX |
0x432f47 MOV %R10,0x50(%RSP) |
0x432f4c MOV %EAX,0x5c(%RSP) |
(228) 0x432f50 TEST %EBX,%EBX |
(228) 0x432f52 JLE 433193 |
(228) 0x432f58 MOV 0x88(%RSP),%R14 |
(228) 0x432f60 MOV 0x90(%RSP),%R10 |
(228) 0x432f68 MOV 0xa4(%RSP),%R11D |
(228) 0x432f70 CMPL $0x2,0x84(%RSP) |
(228) 0x432f78 MOV (%R14),%R15D |
(228) 0x432f7b MOV (%R10),%EAX |
(228) 0x432f7e LEA (%R11,%R15,1),%R14D |
(228) 0x432f82 JBE 433231 |
(228) 0x432f88 MOV 0x70(%RSP),%R10 |
(228) 0x432f8d MOVSXD %EAX,%R13 |
(228) 0x432f90 MOVSXD %EDI,%R11 |
(228) 0x432f93 MOV 0x68(%RSP),%RCX |
(228) 0x432f98 MOVSXD %R15D,%RDX |
(228) 0x432f9b ADD %R10,%R13 |
(228) 0x432f9e ADD %RCX,%RDX |
(228) 0x432fa1 ADD %R11,%R13 |
(228) 0x432fa4 MOV 0xb0(%RSP),%R11 |
(228) 0x432fac ADD %RSI,%RDX |
(228) 0x432faf LEA (%R9,%RDX,8),%R10 |
(228) 0x432fb3 LEA (%R8,%R13,8),%R13 |
(228) 0x432fb7 XOR %EDX,%EDX |
(228) 0x432fb9 SUB $0x20,%R11 |
(228) 0x432fbd SHR $0x5,%R11 |
(228) 0x432fc1 INC %R11 |
(228) 0x432fc4 AND $0x7,%R11D |
(228) 0x432fc8 JE 43307d |
(228) 0x432fce CMP $0x1,%R11 |
(228) 0x432fd2 JE 43305b |
(228) 0x432fd8 CMP $0x2,%R11 |
(228) 0x432fdc JE 43304a |
(228) 0x432fde CMP $0x3,%R11 |
(228) 0x432fe2 JE 433039 |
(228) 0x432fe4 CMP $0x4,%R11 |
(228) 0x432fe8 JE 433028 |
(228) 0x432fea CMP $0x5,%R11 |
(228) 0x432fee JE 433017 |
(228) 0x432ff0 CMP $0x6,%R11 |
(228) 0x432ff4 JE 433006 |
(228) 0x432ff6 VMOVUPD (%R13),%YMM15 |
(228) 0x432ffc MOV $0x20,%EDX |
(228) 0x433001 VMOVUPD %YMM15,(%R10) |
(228) 0x433006 VMOVUPD (%R13,%RDX,1),%YMM3 |
(228) 0x43300d VMOVUPD %YMM3,(%R10,%RDX,1) |
(228) 0x433013 ADD $0x20,%RDX |
(228) 0x433017 VMOVUPD (%R13,%RDX,1),%YMM2 |
(228) 0x43301e VMOVUPD %YMM2,(%R10,%RDX,1) |
(228) 0x433024 ADD $0x20,%RDX |
(228) 0x433028 VMOVUPD (%R13,%RDX,1),%YMM1 |
(228) 0x43302f VMOVUPD %YMM1,(%R10,%RDX,1) |
(228) 0x433035 ADD $0x20,%RDX |
(228) 0x433039 VMOVUPD (%R13,%RDX,1),%YMM0 |
(228) 0x433040 VMOVUPD %YMM0,(%R10,%RDX,1) |
(228) 0x433046 ADD $0x20,%RDX |
(228) 0x43304a VMOVUPD (%R13,%RDX,1),%YMM4 |
(228) 0x433051 VMOVUPD %YMM4,(%R10,%RDX,1) |
(228) 0x433057 ADD $0x20,%RDX |
(228) 0x43305b VMOVUPD (%R13,%RDX,1),%YMM5 |
(228) 0x433062 MOV 0xb0(%RSP),%RCX |
(228) 0x43306a VMOVUPD %YMM5,(%R10,%RDX,1) |
(228) 0x433070 ADD $0x20,%RDX |
(228) 0x433074 CMP %RCX,%RDX |
(228) 0x433077 JE 43311c |
(229) 0x43307d VMOVUPD (%R13,%RDX,1),%YMM6 |
(229) 0x433084 MOV 0xb0(%RSP),%R11 |
(229) 0x43308c VMOVUPD %YMM6,(%R10,%RDX,1) |
(229) 0x433092 VMOVUPD 0x20(%R13,%RDX,1),%YMM7 |
(229) 0x433099 VMOVUPD %YMM7,0x20(%R10,%RDX,1) |
(229) 0x4330a0 VMOVUPD 0x40(%R13,%RDX,1),%YMM8 |
(229) 0x4330a7 VMOVUPD %YMM8,0x40(%R10,%RDX,1) |
(229) 0x4330ae VMOVUPD 0x60(%R13,%RDX,1),%YMM9 |
(229) 0x4330b5 VMOVUPD %YMM9,0x60(%R10,%RDX,1) |
(229) 0x4330bc VMOVUPD 0x80(%R13,%RDX,1),%YMM10 |
(229) 0x4330c6 VMOVUPD %YMM10,0x80(%R10,%RDX,1) |
(229) 0x4330d0 VMOVUPD 0xa0(%R13,%RDX,1),%YMM11 |
(229) 0x4330da VMOVUPD %YMM11,0xa0(%R10,%RDX,1) |
(229) 0x4330e4 VMOVUPD 0xc0(%R13,%RDX,1),%YMM12 |
(229) 0x4330ee VMOVUPD %YMM12,0xc0(%R10,%RDX,1) |
(229) 0x4330f8 VMOVUPD 0xe0(%R13,%RDX,1),%YMM13 |
(229) 0x433102 VMOVUPD %YMM13,0xe0(%R10,%RDX,1) |
(229) 0x43310c ADD $0x100,%RDX |
(229) 0x433113 CMP %R11,%RDX |
(229) 0x433116 JNE 43307d |
(228) 0x43311c MOV 0x78(%RSP),%ECX |
(228) 0x433120 CMP %EBX,%ECX |
(228) 0x433122 JE 433193 |
(228) 0x433124 MOV 0x60(%RSP),%EDX |
(228) 0x433128 MOV %EBX,%R11D |
(228) 0x43312b SUB %ECX,%R11D |
(228) 0x43312e CMP $0x1,%R11D |
(228) 0x433132 JE 433175 |
(228) 0x433134 LEA (%R12,%RCX,1),%R13 |
(228) 0x433138 MOVSXD %EAX,%R10 |
(228) 0x43313b ADD %RSI,%RCX |
(228) 0x43313e ADD %R13,%R10 |
(228) 0x433141 MOVSXD %EDI,%R13 |
(228) 0x433144 LEA 0x1(%R13,%R10,1),%R10 |
(228) 0x433149 MOVSXD %R15D,%R13 |
(228) 0x43314c MOV 0x98(%RSP),%R15 |
(228) 0x433154 VMOVUPD (%R8,%R10,8),%XMM14 |
(228) 0x43315a ADD %R15,%RCX |
(228) 0x43315d LEA 0x1(%R13,%RCX,1),%RCX |
(228) 0x433162 VMOVUPD %XMM14,(%R9,%RCX,8) |
(228) 0x433168 TEST $0x1,%R11B |
(228) 0x43316c JE 433193 |
(228) 0x43316e AND $-0x2,%R11D |
(228) 0x433172 ADD %R11D,%EDX |
(228) 0x433175 ADD %EDX,%EAX |
(228) 0x433177 ADD %R14D,%EDX |
(228) 0x43317a ADD %EDI,%EAX |
(228) 0x43317c CLTQ |
(228) 0x43317e ADD %R12,%RAX |
(228) 0x433181 VMOVSD (%R8,%RAX,8),%XMM15 |
(228) 0x433187 MOVSXD %EDX,%RAX |
(228) 0x43318a ADD %RSI,%RAX |
(228) 0x43318d VMOVSD %XMM15,(%R9,%RAX,8) |
(228) 0x433193 INCL 0xb8(%RSP) |
(228) 0x43319a MOV 0xa8(%RSP),%RDX |
(228) 0x4331a2 ADD %EBX,%EDI |
(228) 0x4331a4 ADD %RDX,%RSI |
(228) 0x4331a7 MOV 0xb8(%RSP),%R14D |
(228) 0x4331af TEST %EBX,%EBX |
(228) 0x4331b1 JNS 433210 |
(228) 0x4331b3 CMP %R14D,0xa0(%RSP) |
(228) 0x4331bb JG 432f50 |
0x4331c1 MOV 0x50(%RSP),%R12 |
0x4331c6 VZEROUPPER |
0x4331c9 CMPB $0,0x83(%RSP) |
0x4331d1 JNE 4331f2 |
0x4331d3 LEA -0x28(%RBP),%RSP |
0x4331d7 POP %RBX |
0x4331d8 POP %R12 |
0x4331da POP %R13 |
0x4331dc POP %R14 |
0x4331de POP %R15 |
0x4331e0 POP %RBP |
0x4331e1 RET |
0x4331e2 MOV 0x50(%RSP),%R12 |
0x4331e7 VZEROUPPER |
0x4331ea MOV 0x5c(%RSP),%EBX |
0x4331ee MOV %EBX,0x58(%RSP) |
0x4331f2 MOV 0x58(%RSP),%R8D |
0x4331f7 MOV %R8D,0x50(%R12) |
0x4331fc LEA -0x28(%RBP),%RSP |
0x433200 POP %RBX |
0x433201 POP %R12 |
0x433203 POP %R13 |
0x433205 POP %R14 |
0x433207 POP %R15 |
0x433209 POP %RBP |
0x43320a RET |
0x43320b NOPL (%RAX,%RAX,1) |
(228) 0x433210 CMP %R14D,0xa0(%RSP) |
(228) 0x433218 JLE 4331e2 |
(228) 0x43321a MOV 0x5c(%RSP),%R11D |
(228) 0x43321f MOVB $0x1,0x83(%RSP) |
(228) 0x433227 MOV %R11D,0x58(%RSP) |
(228) 0x43322c JMP 432f50 |
(228) 0x433231 XOR %ECX,%ECX |
(228) 0x433233 MOV $0x1,%EDX |
(228) 0x433238 JMP 433128 |
0x43323d INC %EAX |
0x43323f XOR %EDX,%EDX |
0x433241 JMP 432e5c |
0x433246 MOV 0xb8(%RSP),%ESI |
0x43324d MOV 0xa8(%RSP),%RDI |
0x433255 MOV %EAX,0x44(%RSP) |
0x433259 MOV %EBX,%R15D |
0x43325c KXORB %K0,%K0,%K0 |
0x433260 SHR $0x2,%R15D |
0x433264 LEA (,%R13,8),%RCX |
0x43326c MOV %R10,0x18(%RSP) |
0x433271 ADD %ESI,%EAX |
0x433273 MOVSXD %ESI,%RDX |
0x433276 MOV 0xb0(%RSP),%RSI |
0x43327e MOV %R15D,0x84(%RSP) |
0x433286 IMUL %RDI,%RDX |
0x43328a MOV %R13,%RDI |
0x43328d MOV %RCX,0x50(%RSP) |
0x433292 MOV %R13,%R15 |
0x433295 IMUL %EBX,%EAX |
0x433298 SAL $0x4,%RDI |
0x43329c MOV %R14,%RCX |
0x43329f SAL $0x5,%R15 |
0x4332a3 SAL $0x4,%RCX |
0x4332a7 MOV %RDI,0x38(%RSP) |
0x4332ac XOR %EDI,%EDI |
0x4332ae ADD %RDX,%RSI |
0x4332b1 LEA (,%R14,8),%RDX |
0x4332b9 MOV %RCX,0x78(%RSP) |
0x4332be MOV %EAX,%R11D |
0x4332c1 MOV %R14,%RAX |
0x4332c4 MOV %RDX,0x60(%RSP) |
0x4332c9 MOV %EBX,%EDX |
0x4332cb SAL $0x5,%RAX |
0x4332cf AND $-0x4,%EDX |
0x4332d2 MOV %RAX,0x70(%RSP) |
0x4332d7 LEA (%R14,%R14,2),%RAX |
0x4332db SAL $0x3,%RAX |
0x4332df MOV %EDX,0x40(%RSP) |
0x4332e3 INC %EDX |
0x4332e5 TEST %EBX,%EBX |
0x4332e7 CMOVNS %EBX,%EDI |
0x4332ea MOV %RAX,0x68(%RSP) |
0x4332ef MOV %EDX,0x24(%RSP) |
0x4332f3 INC %EDI |
0x4332f5 MOV %EDI,0x5c(%RSP) |
0x4332f9 NOPL (%RAX) |
(226) 0x433300 TEST %EBX,%EBX |
(226) 0x433302 JLE 43363c |
(226) 0x433308 MOV 0x90(%RSP),%R10 |
(226) 0x433310 MOV 0x88(%RSP),%RDX |
(226) 0x433318 MOV 0xa4(%RSP),%ECX |
(226) 0x43331f MOVSXD (%R10),%RAX |
(226) 0x433322 ADD (%RDX),%ECX |
(226) 0x433324 CMPL $0x2,0x44(%RSP) |
(226) 0x433329 MOV %EAX,0xb0(%RSP) |
(226) 0x433330 MOV %ECX,0x98(%RSP) |
(226) 0x433337 JBE 43369e |
(226) 0x43333d MOVSXD %R11D,%RDI |
(226) 0x433340 MOVSXD %ECX,%RDX |
(226) 0x433343 MOV 0x38(%RSP),%RCX |
(226) 0x433348 LEA 0x1(%RAX,%RDI,1),%R10 |
(226) 0x43334d INC %RDX |
(226) 0x433350 IMUL %R13,%R10 |
(226) 0x433354 IMUL %R14,%RDX |
(226) 0x433358 ADD %R12,%R10 |
(226) 0x43335b LEA (%R8,%R10,8),%RDI |
(226) 0x43335f MOV 0x84(%RSP),%R10D |
(226) 0x433367 ADD %RSI,%RDX |
(226) 0x43336a LEA (%R9,%RDX,8),%RAX |
(226) 0x43336e MOV %RDI,0x48(%RSP) |
(226) 0x433373 LEA (%RDI,%RCX,1),%RDX |
(226) 0x433377 XOR %ECX,%ECX |
(226) 0x433379 AND $0x3,%R10D |
(226) 0x43337d JE 433477 |
(226) 0x433383 CMP $0x1,%R10D |
(226) 0x433387 JE 433422 |
(226) 0x43338d CMP $0x2,%R10D |
(226) 0x433391 JE 4333de |
(226) 0x433393 MOV 0x48(%RSP),%RCX |
(226) 0x433398 VMOVSD (%RDX),%XMM1 |
(226) 0x43339c ADD %R15,%RDI |
(226) 0x43339f MOV 0x78(%RSP),%R10 |
(226) 0x4333a4 VMOVSD (%RDX,%R13,8),%XMM0 |
(226) 0x4333aa ADD %R15,%RDX |
(226) 0x4333ad VMOVSD (%RCX),%XMM3 |
(226) 0x4333b1 VMOVSD (%RCX,%R13,8),%XMM2 |
(226) 0x4333b7 MOV 0x68(%RSP),%RCX |
(226) 0x4333bc VMOVSD %XMM3,(%RAX) |
(226) 0x4333c0 VMOVSD %XMM2,(%RAX,%R14,8) |
(226) 0x4333c6 VMOVSD %XMM1,(%RAX,%R10,1) |
(226) 0x4333cc MOV 0x70(%RSP),%R10 |
(226) 0x4333d1 VMOVSD %XMM0,(%RAX,%RCX,1) |
(226) 0x4333d6 MOV $0x1,%ECX |
(226) 0x4333db ADD %R10,%RAX |
(226) 0x4333de VMOVSD (%RDI),%XMM4 |
(226) 0x4333e2 VMOVSD (%RDI,%R13,8),%XMM5 |
(226) 0x4333e8 INC %ECX |
(226) 0x4333ea ADD %R15,%RDI |
(226) 0x4333ed VMOVSD (%RDX),%XMM6 |
(226) 0x4333f1 MOV 0x78(%RSP),%R10 |
(226) 0x4333f6 VMOVSD (%RDX,%R13,8),%XMM7 |
(226) 0x4333fc VMOVSD %XMM4,(%RAX) |
(226) 0x433400 ADD %R15,%RDX |
(226) 0x433403 VMOVSD %XMM5,(%RAX,%R14,8) |
(226) 0x433409 VMOVSD %XMM6,(%RAX,%R10,1) |
(226) 0x43340f MOV 0x68(%RSP),%R10 |
(226) 0x433414 VMOVSD %XMM7,(%RAX,%R10,1) |
(226) 0x43341a MOV 0x70(%RSP),%R10 |
(226) 0x43341f ADD %R10,%RAX |
(226) 0x433422 VMOVSD (%RDI),%XMM8 |
(226) 0x433426 VMOVSD (%RDI,%R13,8),%XMM9 |
(226) 0x43342c INC %ECX |
(226) 0x43342e ADD %R15,%RDI |
(226) 0x433431 VMOVSD (%RDX),%XMM10 |
(226) 0x433435 MOV 0x78(%RSP),%R10 |
(226) 0x43343a VMOVSD (%RDX,%R13,8),%XMM11 |
(226) 0x433440 VMOVSD %XMM8,(%RAX) |
(226) 0x433444 ADD %R15,%RDX |
(226) 0x433447 VMOVSD %XMM9,(%RAX,%R14,8) |
(226) 0x43344d VMOVSD %XMM10,(%RAX,%R10,1) |
(226) 0x433453 MOV 0x68(%RSP),%R10 |
(226) 0x433458 VMOVSD %XMM11,(%RAX,%R10,1) |
(226) 0x43345e MOV 0x70(%RSP),%R10 |
(226) 0x433463 ADD %R10,%RAX |
(226) 0x433466 MOV 0x84(%RSP),%R10D |
(226) 0x43346e CMP %R10D,%ECX |
(226) 0x433471 JE 433580 |
(226) 0x433477 MOV %R9,0x30(%RSP) |
(226) 0x43347c MOV 0x68(%RSP),%R10 |
(226) 0x433481 MOV %R8,0x48(%RSP) |
(226) 0x433486 MOV 0x70(%RSP),%R8 |
(226) 0x43348b MOV %RSI,0x28(%RSP) |
(226) 0x433490 MOV 0x78(%RSP),%RSI |
(227) 0x433495 VMOVSD (%RDI),%XMM12 |
(227) 0x433499 VMOVSD (%RDI,%R13,8),%XMM13 |
(227) 0x43349f ADD %R15,%RDI |
(227) 0x4334a2 ADD $0x4,%ECX |
(227) 0x4334a5 VMOVSD (%RDX),%XMM14 |
(227) 0x4334a9 VMOVSD (%RDX,%R13,8),%XMM15 |
(227) 0x4334af ADD %R15,%RDX |
(227) 0x4334b2 VMOVSD %XMM12,(%RAX) |
(227) 0x4334b6 VMOVSD %XMM13,(%RAX,%R14,8) |
(227) 0x4334bc VMOVSD %XMM14,(%RAX,%RSI,1) |
(227) 0x4334c1 VMOVSD %XMM15,(%RAX,%R10,1) |
(227) 0x4334c7 ADD %R8,%RAX |
(227) 0x4334ca VMOVSD (%RDI),%XMM3 |
(227) 0x4334ce VMOVSD (%RDI,%R13,8),%XMM2 |
(227) 0x4334d4 ADD %R15,%RDI |
(227) 0x4334d7 VMOVSD (%RDX),%XMM1 |
(227) 0x4334db VMOVSD (%RDX,%R13,8),%XMM0 |
(227) 0x4334e1 ADD %R15,%RDX |
(227) 0x4334e4 VMOVSD %XMM3,(%RAX) |
(227) 0x4334e8 VMOVSD %XMM2,(%RAX,%R14,8) |
(227) 0x4334ee VMOVSD %XMM1,(%RAX,%RSI,1) |
(227) 0x4334f3 VMOVSD %XMM0,(%RAX,%R10,1) |
(227) 0x4334f9 ADD %R8,%RAX |
(227) 0x4334fc VMOVSD (%RDI),%XMM4 |
(227) 0x433500 VMOVSD (%RDI,%R13,8),%XMM5 |
(227) 0x433506 ADD %R15,%RDI |
(227) 0x433509 VMOVSD (%RDX),%XMM6 |
(227) 0x43350d VMOVSD (%RDX,%R13,8),%XMM7 |
(227) 0x433513 ADD %R15,%RDX |
(227) 0x433516 VMOVSD %XMM4,(%RAX) |
(227) 0x43351a VMOVSD %XMM5,(%RAX,%R14,8) |
(227) 0x433520 VMOVSD %XMM6,(%RAX,%RSI,1) |
(227) 0x433525 VMOVSD %XMM7,(%RAX,%R10,1) |
(227) 0x43352b ADD %R8,%RAX |
(227) 0x43352e VMOVSD (%RDI),%XMM8 |
(227) 0x433532 VMOVSD (%RDI,%R13,8),%XMM9 |
(227) 0x433538 ADD %R15,%RDI |
(227) 0x43353b VMOVSD (%RDX),%XMM10 |
(227) 0x43353f VMOVSD (%RDX,%R13,8),%XMM11 |
(227) 0x433545 ADD %R15,%RDX |
(227) 0x433548 VMOVSD %XMM8,(%RAX) |
(227) 0x43354c VMOVSD %XMM9,(%RAX,%R14,8) |
(227) 0x433552 VMOVSD %XMM10,(%RAX,%RSI,1) |
(227) 0x433557 VMOVSD %XMM11,(%RAX,%R10,1) |
(227) 0x43355d MOV 0x84(%RSP),%R9D |
(227) 0x433565 ADD %R8,%RAX |
(227) 0x433568 CMP %R9D,%ECX |
(227) 0x43356b JNE 433495 |
(226) 0x433571 MOV 0x48(%RSP),%R8 |
(226) 0x433576 MOV 0x30(%RSP),%R9 |
(226) 0x43357b MOV 0x28(%RSP),%RSI |
(226) 0x433580 MOV 0x40(%RSP),%EDI |
(226) 0x433584 CMP %EDI,%EBX |
(226) 0x433586 JE 43363c |
(226) 0x43358c MOV 0x24(%RSP),%EAX |
(226) 0x433590 MOV %EDI,%ECX |
(226) 0x433592 MOV %EBX,%EDI |
(226) 0x433594 SUB %ECX,%EDI |
(226) 0x433596 CMP $0x1,%EDI |
(226) 0x433599 JE 433607 |
(226) 0x43359b MOVSXD 0xb0(%RSP),%RDX |
(226) 0x4335a3 MOVSXD %R11D,%R10 |
(226) 0x4335a6 LEA 0x1(%RDX,%R10,1),%RDX |
(226) 0x4335ab MOV %R13,%R10 |
(226) 0x4335ae IMUL %R13,%RDX |
(226) 0x4335b2 IMUL %RCX,%R10 |
(226) 0x4335b6 IMUL %R14,%RCX |
(226) 0x4335ba ADD %R12,%RDX |
(226) 0x4335bd ADD %R10,%RDX |
(226) 0x4335c0 LEA (%R8,%RDX,8),%R10 |
(226) 0x4335c4 MOVSXD 0x98(%RSP),%RDX |
(226) 0x4335cc VMOVSD (%R10),%XMM12 |
(226) 0x4335d1 INC %RDX |
(226) 0x4335d4 IMUL %R14,%RDX |
(226) 0x4335d8 ADD %RSI,%RDX |
(226) 0x4335db ADD %RCX,%RDX |
(226) 0x4335de MOV 0x50(%RSP),%RCX |
(226) 0x4335e3 LEA (%R9,%RDX,8),%RDX |
(226) 0x4335e7 VMOVSD (%R10,%RCX,1),%XMM13 |
(226) 0x4335ed MOV 0x60(%RSP),%R10 |
(226) 0x4335f2 VMOVSD %XMM12,(%RDX) |
(226) 0x4335f6 VMOVSD %XMM13,(%RDX,%R10,1) |
(226) 0x4335fc TEST $0x1,%DIL |
(226) 0x433600 JE 43363c |
(226) 0x433602 AND $-0x2,%EDI |
(226) 0x433605 ADD %EDI,%EAX |
(226) 0x433607 MOV 0xb0(%RSP),%EDI |
(226) 0x43360e MOV 0x98(%RSP),%ECX |
(226) 0x433615 ADD %EAX,%EDI |
(226) 0x433617 ADD %EAX,%ECX |
(226) 0x433619 ADD %R11D,%EDI |
(226) 0x43361c MOVSXD %ECX,%RAX |
(226) 0x43361f MOVSXD %EDI,%RDX |
(226) 0x433622 IMUL %R14,%RAX |
(226) 0x433626 IMUL %R13,%RDX |
(226) 0x43362a ADD %RSI,%RAX |
(226) 0x43362d ADD %R12,%RDX |
(226) 0x433630 VMOVSD (%R8,%RDX,8),%XMM14 |
(226) 0x433636 VMOVSD %XMM14,(%R9,%RAX,8) |
(226) 0x43363c INCL 0xb8(%RSP) |
(226) 0x433643 MOV 0xa8(%RSP),%RDI |
(226) 0x43364b ADD %EBX,%R11D |
(226) 0x43364e ADD %RDI,%RSI |
(226) 0x433651 MOV 0xb8(%RSP),%R10D |
(226) 0x433659 TEST %EBX,%EBX |
(226) 0x43365b JNS 43367e |
(226) 0x43365d CMP %R10D,0xa0(%RSP) |
(226) 0x433665 JG 433300 |
0x43366b MOV 0x18(%RSP),%R12 |
0x433670 KMOVB %K0,0x83(%RSP) |
0x433679 JMP 4331c9 |
(226) 0x43367e CMP %R10D,0xa0(%RSP) |
(226) 0x433686 JLE 4336aa |
(226) 0x433688 MOV 0x5c(%RSP),%EDX |
(226) 0x43368c KMOVB 0x83(%RSP),%K0 |
(226) 0x433695 MOV %EDX,0x58(%RSP) |
(226) 0x433699 JMP 433300 |
(226) 0x43369e XOR %ECX,%ECX |
(226) 0x4336a0 MOV $0x1,%EAX |
(226) 0x4336a5 JMP 433592 |
0x4336aa MOV 0x18(%RSP),%R12 |
0x4336af JMP 4331ea |
0x4336b4 NOPW %CS:(%RAX,%RAX,1) |
0x4336bf NOP |
Path / |
Source file and lines | pack_kernel.f90:202-207 |
Module | exec |
nb instructions | 168 |
nb uops | 175 |
loop length | 683 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 23 |
micro-operation queue | 29.17 cycles |
front end | 29.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.60 | 11.60 | 14.33 | 14.33 | 20.50 | 11.60 | 11.60 | 20.50 | 20.50 | 20.50 | 11.60 | 14.33 |
cycles | 11.60 | 14.27 | 14.33 | 14.33 | 20.50 | 11.60 | 11.60 | 20.50 | 20.50 | 20.50 | 11.60 | 14.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 28.47-28.50 |
Stall cycles | 0.00 |
Front-end | 29.17 |
Dispatch | 20.50 |
DIV/SQRT | 6.00 |
Overall L1 | 29.17 |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 9% |
load | 11% |
store | 9% |
mul | 12% |
add-sub | 8% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x54(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0xa4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x5c(%R10),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 43323d <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x45d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4331d3 <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x3f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x8(%R10),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R15,%RSI,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SETNE %R15B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP $0x1,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R10),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %CL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x38(%R10),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
OR %CL,%R15B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDI,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x1(%RBX),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15B,0x83(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 433246 <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x466> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xb8(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EBX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xb0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
AND $-0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x2,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EAX,0x84(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R13D,%R14 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA (%R13,%RAX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x5,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %R11,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %ECX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD 0xa4(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x1(%R12),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R14,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %EBX,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %ECX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMOVNS %EBX,%EAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CMPB $0,0x83(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 4331f2 <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x412> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV 0x50(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x5c(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8D,0x50(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 432e5c <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x7c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0xb8(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EBX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
KXORB %K0,%K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
SHR $0x2,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (,%R13,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %ESI,%RDX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0xb0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15D,0x84(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RDI,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x4,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R14,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x5,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x4,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RDI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (,%R14,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EBX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x5,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
AND $-0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RAX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R14,%R14,2),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %EBX,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %EBX,%EDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
KMOVB %K0,0x83(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
JMP 4331c9 <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x3e9> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x18(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4331ea <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x40a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | pack_kernel.f90:202-207 |
Module | exec |
nb instructions | 168 |
nb uops | 175 |
loop length | 683 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 23 |
micro-operation queue | 29.17 cycles |
front end | 29.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.60 | 11.60 | 14.33 | 14.33 | 20.50 | 11.60 | 11.60 | 20.50 | 20.50 | 20.50 | 11.60 | 14.33 |
cycles | 11.60 | 14.27 | 14.33 | 14.33 | 20.50 | 11.60 | 11.60 | 20.50 | 20.50 | 20.50 | 11.60 | 14.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 28.47-28.50 |
Stall cycles | 0.00 |
Front-end | 29.17 |
Dispatch | 20.50 |
DIV/SQRT | 6.00 |
Overall L1 | 29.17 |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 9% |
load | 11% |
store | 9% |
mul | 12% |
add-sub | 8% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x54(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0xa4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x5c(%R10),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 43323d <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x45d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4331d3 <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x3f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x8(%R10),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R15,%RSI,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SETNE %R15B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP $0x1,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R10),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %CL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x38(%R10),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
OR %CL,%R15B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDI,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x1(%RBX),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15B,0x83(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 433246 <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x466> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xb8(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EBX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xb0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
AND $-0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x2,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EAX,0x84(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R13D,%R14 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA (%R13,%RAX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x5,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %R11,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %ECX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD 0xa4(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x1(%R12),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R14,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %EBX,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %ECX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMOVNS %EBX,%EAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CMPB $0,0x83(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 4331f2 <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x412> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV 0x50(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x5c(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8D,0x50(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 432e5c <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x7c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0xb8(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EBX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
KXORB %K0,%K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
SHR $0x2,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (,%R13,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %ESI,%RDX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0xb0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15D,0x84(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RDI,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R13,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x4,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R14,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x5,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x4,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RDI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (,%R14,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EBX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x5,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
AND $-0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RAX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R14,%R14,2),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %EBX,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %EBX,%EDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
KMOVB %K0,0x83(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
JMP 4331c9 <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x3e9> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x18(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4331ea <__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0+0x40a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼__pack_kernel_module_MOD_clover_unpack_message_right._omp_fn.0.lto_priv.0– | 0.03 | 0.01 |
▼Loop 228 - pack_kernel.f90:202-207 - exec– | 0.03 | 0.02 |
○Loop 229 - pack_kernel.f90:207-207 - exec | 0 | 0 |
▼Loop 226 - pack_kernel.f90:206-207 - exec– | 0 | 0 |
○Loop 227 - pack_kernel.f90:207-207 - exec | 0 | 0 |