Function: calc_dt_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: calc_dt_kernel.f90:89-133 [...] | Coverage: 4.94% |
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Function: calc_dt_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: calc_dt_kernel.f90:89-133 [...] | Coverage: 4.94% |
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/scratch_na/users/xoserete/qaas_runs/171-214-9740/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 133 |
-------------------------------------------------------------------------------- |
89: !$OMP PARALLEL |
90: |
91: !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val) |
92: DO k=y_min,y_max |
93: !$OMP SIMD |
94: DO j=x_min,x_max |
95: |
96: dsx=celldx(j) |
97: dsy=celldy(k) |
98: |
99: cc=soundspeed(j,k)*soundspeed(j,k) |
100: cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k) |
101: cc=MAX(SQRT(cc),g_small) |
102: |
103: dtct=dtc_safe*MIN(dsx,dsy)/cc |
104: |
105: div=0.0 |
106: |
107: dv1=(xvel0(j ,k)+xvel0(j ,k+1))*xarea(j ,k) |
108: dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k) |
109: |
110: div=div+dv2-dv1 |
111: |
112: dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
113: |
114: dv1=(yvel0(j,k )+yvel0(j+1,k ))*yarea(j,k ) |
115: dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1) |
116: |
117: div=div+dv2-dv1 |
118: |
119: dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
120: |
121: div=div/(2.0_8*volume(j,k)) |
122: |
123: IF(div.LT.-g_small)THEN |
[...] |
129: dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt) |
130: |
131: ENDDO |
132: ENDDO |
133: !$OMP END DO |
0x43ec40 PUSH %RBP |
0x43ec41 MOV %RSP,%RBP |
0x43ec44 PUSH %R15 |
0x43ec46 PUSH %R14 |
0x43ec48 PUSH %R13 |
0x43ec4a PUSH %R12 |
0x43ec4c PUSH %RBX |
0x43ec4d AND $-0x40,%RSP |
0x43ec51 SUB $0x400,%RSP |
0x43ec58 MOV 0x90(%RBP),%ESI |
0x43ec5e MOV 0x88(%RBP),%EAX |
0x43ec64 SUB %ESI,%EAX |
0x43ec66 MOVL $0,0x4c(%RSP) |
0x43ec6e JS 43f94e |
0x43ec74 MOV %R8,0x90(%RSP) |
0x43ec7c MOV %RCX,%R12 |
0x43ec7f MOV %RDX,%R15 |
0x43ec82 MOV %R9,%R13 |
0x43ec85 MOV %RDI,0x50(%RSP) |
0x43ec8a MOV (%RDI),%ESI |
0x43ec8c MOVL $0,0x3c(%RSP) |
0x43ec94 MOV %EAX,0x38(%RSP) |
0x43ec98 MOVL $0x1,0x48(%RSP) |
0x43eca0 SUB $0x8,%RSP |
0x43eca4 LEA 0x50(%RSP),%RAX |
0x43eca9 LEA 0x54(%RSP),%RCX |
0x43ecae LEA 0x44(%RSP),%R8 |
0x43ecb3 LEA 0x40(%RSP),%R9 |
0x43ecb8 MOV $0x74d0b0,%EDI |
0x43ecbd MOV %ESI,0x48(%RSP) |
0x43ecc1 MOV $0x22,%EDX |
0x43ecc6 PUSH $0x1 |
0x43ecc8 PUSH $0x1 |
0x43ecca PUSH %RAX |
0x43eccb CALL 4044c0 <__kmpc_for_static_init_4@plt> |
0x43ecd0 ADD $0x20,%RSP |
0x43ecd4 MOV 0x3c(%RSP),%EAX |
0x43ecd8 MOV 0x38(%RSP),%ECX |
0x43ecdc MOV %RAX,0x58(%RSP) |
0x43ece1 SUB %EAX,%ECX |
0x43ece3 MOV %ECX,0x44(%RSP) |
0x43ece7 JAE 43ed00 |
0x43ece9 VMOVSD 0xcc017(%RIP),%XMM0 |
0x43ecf1 JMP 43f8c7 |
0x43ecf6 NOPW %CS:(%RAX,%RAX,1) |
0x43ed00 MOV 0x48(%RBP),%R9 |
0x43ed04 MOV 0x30(%RBP),%R11 |
0x43ed08 MOV 0x28(%RBP),%R10 |
0x43ed0c SAL $0x20,%R12 |
0x43ed10 MOV $-0x200000000,%RCX |
0x43ed1a LEA (%R12,%RCX,1),%RDI |
0x43ed1e MOV %RDI,%RAX |
0x43ed21 SAR $0x20,%RAX |
0x43ed25 MOV %RAX,0xa0(%RSP) |
0x43ed2d SAL $0x20,%R15 |
0x43ed31 ADD %R15,%RCX |
0x43ed34 MOV %RCX,%R14 |
0x43ed37 SAR $0x20,%R14 |
0x43ed3b TEST %RDI,%RDI |
0x43ed3e MOV $-0x1,%R8 |
0x43ed45 CMOVNS %RDI,%R8 |
0x43ed49 TEST %R8,%R8 |
0x43ed4c MOV $0x1,%ESI |
0x43ed51 CMOVG %RSI,%R8 |
0x43ed55 MOV $0x200000000,%RBX |
0x43ed5f MOV %RBX,%RAX |
0x43ed62 SUB %R12,%RAX |
0x43ed65 MOV $-0x1,%RDX |
0x43ed6c CMP %RAX,%RDI |
0x43ed6f CMOVG %RDI,%RAX |
0x43ed73 SHR $0x20,%RAX |
0x43ed77 IMUL %R8,%RAX |
0x43ed7b SAL $0x3,%RAX |
0x43ed7f MOV $0x8,%EDI |
0x43ed84 SUB %RAX,%RDI |
0x43ed87 MOV $0x1,%R8D |
0x43ed8d MOV %R14,0x120(%RSP) |
0x43ed95 SUB %R14,%R8 |
0x43ed98 MOV %R8,0xe8(%RSP) |
0x43eda0 TEST %RCX,%RCX |
0x43eda3 CMOVNS %RCX,%RDX |
0x43eda7 TEST %RDX,%RDX |
0x43edaa CMOVG %RSI,%RDX |
0x43edae MOV 0x20(%RBP),%RSI |
0x43edb2 SUB %R15,%RBX |
0x43edb5 CMP %RBX,%RCX |
0x43edb8 CMOVG %RCX,%RBX |
0x43edbc SHR $0x20,%RBX |
0x43edc0 IMUL %RDX,%RBX |
0x43edc4 MOV %R9,%RCX |
0x43edc7 SUB %RAX,%RCX |
0x43edca MOV %RCX,0xe0(%RSP) |
0x43edd2 SUB %RAX,%R11 |
0x43edd5 MOV %R11,0xd8(%RSP) |
0x43eddd SUB %RAX,%R10 |
0x43ede0 MOV %R10,0xd0(%RSP) |
0x43ede8 SUB %RAX,%RSI |
0x43edeb MOV %RSI,0xc8(%RSP) |
0x43edf3 MOV 0x18(%RBP),%RCX |
0x43edf7 SUB %RAX,%RCX |
0x43edfa MOV %RCX,0xc0(%RSP) |
0x43ee02 MOV 0x40(%RBP),%RCX |
0x43ee06 SUB %RAX,%RCX |
0x43ee09 MOV %RCX,0xb8(%RSP) |
0x43ee11 NEG %RBX |
0x43ee14 MOV %RBX,0xf8(%RSP) |
0x43ee1c MOV 0x50(%RBP),%RAX |
0x43ee20 MOV %R13,0x98(%RSP) |
0x43ee28 LEA (%R13,%RDI,1),%RCX |
0x43ee2d MOV %RCX,0xb0(%RSP) |
0x43ee35 ADD %RDI,%RAX |
0x43ee38 MOV %RAX,0xa8(%RSP) |
0x43ee40 ADD 0x10(%RBP),%RDI |
0x43ee44 MOV %RDI,0xf0(%RSP) |
0x43ee4c VMOVDDUP 0xcbeb2(%RIP),%XMM28 |
0x43ee56 VBROADCASTSD 0xcbe58(%RIP),%ZMM2 |
0x43ee60 VBROADCASTSD 0xcbe16(%RIP),%ZMM3 |
0x43ee6a VBROADCASTSD 0xcbe9c(%RIP),%ZMM4 |
0x43ee74 VBROADCASTSD 0xcbe9a(%RIP),%ZMM5 |
0x43ee7e MOV 0x90(%RBP),%EAX |
0x43ee84 MOV 0x58(%RSP),%RCX |
0x43ee89 LEA (%RCX,%RAX,1),%R15D |
0x43ee8d XOR %R12D,%R12D |
0x43ee90 JMP 43eee6 |
0x43ee92 NOPW %CS:(%RAX,%RAX,1) |
0x43eea1 NOPW %CS:(%RAX,%RAX,1) |
0x43eeb0 NOPW %CS:(%RAX,%RAX,1) |
0x43eebf NOP |
(322) 0x43eec0 VMOVDDUP %XMM28,%XMM28 |
(322) 0x43eec6 MOV 0x34(%RSP),%R15D |
(322) 0x43eecb MOV 0x60(%RSP),%R12 |
(322) 0x43eed0 LEA 0x1(%R12),%EAX |
(322) 0x43eed5 INC %R15D |
(322) 0x43eed8 CMP 0x44(%RSP),%R12D |
(322) 0x43eedd MOV %EAX,%R12D |
(322) 0x43eee0 JE 43f8c0 |
(322) 0x43eee6 MOV 0xa0(%RBP),%RAX |
(322) 0x43eeed MOVSXD (%RAX),%R11 |
(322) 0x43eef0 MOV 0x98(%RBP),%RAX |
(322) 0x43eef7 MOV (%RAX),%ESI |
(322) 0x43eef9 CMP %R11D,%ESI |
(322) 0x43eefc JS 43eed0 |
(322) 0x43eefe MOV %R15D,%EDX |
(322) 0x43ef01 MOV 0x90(%RBP),%EAX |
(322) 0x43ef07 MOV 0x58(%RSP),%RCX |
(322) 0x43ef0c ADD %ECX,%EAX |
(322) 0x43ef0e ADD %R12D,%EAX |
(322) 0x43ef11 MOVSXD %EAX,%RCX |
(322) 0x43ef14 SUB 0x120(%RSP),%RCX |
(322) 0x43ef1c MOV 0x38(%RBP),%RAX |
(322) 0x43ef20 VMOVSD (%RAX,%RCX,8),%XMM23 |
(322) 0x43ef27 MOV 0xa8(%RBP),%RAX |
(322) 0x43ef2e MOV (%RAX),%R15 |
(322) 0x43ef31 MOV 0xb0(%RBP),%RAX |
(322) 0x43ef38 MOV (%RAX),%R14 |
(322) 0x43ef3b MOV 0xb8(%RBP),%RAX |
(322) 0x43ef42 MOV (%RAX),%R10 |
(322) 0x43ef45 VMOVSD 0x315e21(%RIP),%XMM25 |
(322) 0x43ef4f MOV 0xc0(%RBP),%RAX |
(322) 0x43ef56 MOV (%RAX),%RBX |
(322) 0x43ef59 MOV 0xc8(%RBP),%RAX |
(322) 0x43ef60 MOV (%RAX),%R13 |
(322) 0x43ef63 VMOVSD 0x315dfb(%RIP),%XMM24 |
(322) 0x43ef6d MOV 0xd0(%RBP),%RAX |
(322) 0x43ef74 MOV (%RAX),%RDI |
(322) 0x43ef77 MOV 0xd8(%RBP),%RAX |
(322) 0x43ef7e MOV (%RAX),%R8 |
(322) 0x43ef81 MOV 0xe0(%RBP),%RAX |
(322) 0x43ef88 MOV (%RAX),%R9 |
(322) 0x43ef8b VMOVSD 0x315dcb(%RIP),%XMM26 |
(322) 0x43ef95 VMOVSD 0x315dbb(%RIP),%XMM0 |
(322) 0x43ef9d VXORPD 0xcbd51(%RIP){1to2},%XMM0,%XMM27 |
(322) 0x43efa7 SUB %R11D,%ESI |
(322) 0x43efaa INC %ESI |
(322) 0x43efac CMP $0x2,%ESI |
(322) 0x43efaf MOV $0x1,%EAX |
(322) 0x43efb4 CMOVL %EAX,%ESI |
(322) 0x43efb7 MOV %RSI,%RAX |
(322) 0x43efba AND $0x7ffffff8,%RSI |
(322) 0x43efc1 MOV %R10,0x80(%RSP) |
(322) 0x43efc9 MOV %RBX,0x138(%RSP) |
(322) 0x43efd1 MOV %R11,0x130(%RSP) |
(322) 0x43efd9 JE 43f400 |
(322) 0x43efdf MOV %RAX,0x128(%RSP) |
(322) 0x43efe7 MOV %RCX,0x110(%RSP) |
(322) 0x43efef MOV %R12,0x60(%RSP) |
(322) 0x43eff4 MOV %EDX,0x34(%RSP) |
(322) 0x43eff8 MOVSXD %EDX,%RAX |
(322) 0x43effb MOV 0xe8(%RSP),%RCX |
(322) 0x43f003 ADD %RAX,%RCX |
(322) 0x43f006 ADD 0xf8(%RSP),%RAX |
(322) 0x43f00e VBROADCASTSD %XMM28,%ZMM28 |
(322) 0x43f014 MOV %R8,%RDX |
(322) 0x43f017 IMUL %RCX,%RDX |
(322) 0x43f01b MOV %R15,0x70(%RSP) |
(322) 0x43f020 LEA (%RDX,%R11,8),%R12 |
(322) 0x43f024 MOV %RDI,0x68(%RSP) |
(322) 0x43f029 MOV 0xb0(%RSP),%RDI |
(322) 0x43f031 ADD %RDI,%R12 |
(322) 0x43f034 MOV %R8,0x108(%RSP) |
(322) 0x43f03c MOV %R8,%RDX |
(322) 0x43f03f IMUL %RAX,%RDX |
(322) 0x43f043 MOV %R14,0x78(%RSP) |
(322) 0x43f048 LEA (%RDX,%R11,8),%R15 |
(322) 0x43f04c ADD %RDI,%R15 |
(322) 0x43f04f MOV %R13,0x100(%RSP) |
(322) 0x43f057 IMUL %RAX,%R13 |
(322) 0x43f05b LEA (%R13,%R11,8),%R14 |
(322) 0x43f060 ADD 0xa8(%RSP),%R14 |
(322) 0x43f068 MOV %RBX,%RDX |
(322) 0x43f06b IMUL %RAX,%RDX |
(322) 0x43f06f LEA (%RDX,%R11,8),%R10 |
(322) 0x43f073 MOV 0xf0(%RSP),%RDI |
(322) 0x43f07b ADD %RDI,%R10 |
(322) 0x43f07e IMUL %RCX,%RBX |
(322) 0x43f082 LEA (%RBX,%R11,8),%RBX |
(322) 0x43f086 ADD %RDI,%RBX |
(322) 0x43f089 IMUL %R9,%RCX |
(322) 0x43f08d LEA (%RCX,%R11,8),%R8 |
(322) 0x43f091 MOV 0xe0(%RSP),%RDX |
(322) 0x43f099 ADD %RDX,%R8 |
(322) 0x43f09c MOV %R9,0x118(%RSP) |
(322) 0x43f0a4 IMUL %RAX,%R9 |
(322) 0x43f0a8 LEA (%R9,%R11,8),%R13 |
(322) 0x43f0ac ADD %RDX,%R13 |
(322) 0x43f0af MOV 0x68(%RSP),%RCX |
(322) 0x43f0b4 IMUL %RAX,%RCX |
(322) 0x43f0b8 LEA (%RCX,%R11,8),%R9 |
(322) 0x43f0bc ADD 0xd8(%RSP),%R9 |
(322) 0x43f0c4 MOV 0x80(%RSP),%RCX |
(322) 0x43f0cc IMUL %RAX,%RCX |
(322) 0x43f0d0 LEA (%RCX,%R11,8),%RDI |
(322) 0x43f0d4 ADD 0xd0(%RSP),%RDI |
(322) 0x43f0dc MOV 0x78(%RSP),%RCX |
(322) 0x43f0e1 IMUL %RAX,%RCX |
(322) 0x43f0e5 LEA (%RCX,%R11,8),%RDX |
(322) 0x43f0e9 ADD 0xc8(%RSP),%RDX |
(322) 0x43f0f1 IMUL 0x70(%RSP),%RAX |
(322) 0x43f0f7 LEA (%RAX,%R11,8),%RAX |
(322) 0x43f0fb ADD 0xc0(%RSP),%RAX |
(322) 0x43f103 MOV 0xb8(%RSP),%RCX |
(322) 0x43f10b LEA (%RCX,%R11,8),%R11 |
(322) 0x43f10f VBROADCASTSD %XMM23,%ZMM29 |
(322) 0x43f115 VBROADCASTSD %XMM25,%ZMM30 |
(322) 0x43f11b VBROADCASTSD %XMM24,%ZMM31 |
(322) 0x43f121 VBROADCASTSD %XMM26,%ZMM1 |
(322) 0x43f127 VBROADCASTSD %XMM27,%ZMM0 |
(322) 0x43f12d XOR %ECX,%ECX |
(322) 0x43f12f NOP |
(323) 0x43f130 VMOVUPD (%R11,%RCX,8),%ZMM6 |
(323) 0x43f137 VMINPD %ZMM29,%ZMM6,%ZMM6 |
(323) 0x43f13d VMOVUPD (%RDX,%RCX,8),%ZMM7 |
(323) 0x43f144 VADDPD %ZMM7,%ZMM7,%ZMM7 |
(323) 0x43f14a VDIVPD (%RDI,%RCX,8),%ZMM7,%ZMM7 |
(323) 0x43f151 VMULPD %ZMM6,%ZMM30,%ZMM6 |
(323) 0x43f157 VMOVUPD (%RAX,%RCX,8),%ZMM8 |
(323) 0x43f15e VFMADD231PD %ZMM8,%ZMM8,%ZMM7 |
(323) 0x43f164 VSQRTPD %ZMM7,%ZMM7 |
(323) 0x43f16a VMAXPD %ZMM2,%ZMM7,%ZMM7 |
(323) 0x43f170 VDIVPD %ZMM7,%ZMM6,%ZMM6 |
(323) 0x43f176 VMOVUPD -0x8(%RBX,%RCX,8),%ZMM7 |
(323) 0x43f181 VMOVUPD (%RBX,%RCX,8),%ZMM8 |
(323) 0x43f188 VADDPD -0x8(%R10,%RCX,8),%ZMM7,%ZMM7 |
(323) 0x43f193 VMULPD -0x8(%R14,%RCX,8),%ZMM7,%ZMM7 |
(323) 0x43f19e VADDPD (%R10,%RCX,8),%ZMM8,%ZMM8 |
(323) 0x43f1a5 VMULPD (%R14,%RCX,8),%ZMM8,%ZMM8 |
(323) 0x43f1ac VMOVUPD (%R9,%RCX,8),%ZMM9 |
(323) 0x43f1b3 VADDPD %ZMM9,%ZMM9,%ZMM10 |
(323) 0x43f1b9 VMULPD %ZMM31,%ZMM10,%ZMM11 |
(323) 0x43f1bf VANDPD %ZMM3,%ZMM7,%ZMM12 |
(323) 0x43f1c5 VANDPD %ZMM3,%ZMM8,%ZMM13 |
(323) 0x43f1cb VMULPD %ZMM2,%ZMM9,%ZMM9 |
(323) 0x43f1d1 VCMPPD $0x2,%ZMM13,%ZMM9,%K1 |
(323) 0x43f1d8 VBLENDMPD %ZMM13,%ZMM9,%ZMM13{%K1} |
(323) 0x43f1de VCMPPD $0x2,%ZMM12,%ZMM13,%K1 |
(323) 0x43f1e5 VMOVAPD %ZMM12,%ZMM13{%K1} |
(323) 0x43f1eb VDIVPD %ZMM13,%ZMM11,%ZMM11 |
(323) 0x43f1f1 VMOVUPD (%R15,%RCX,8),%ZMM12 |
(323) 0x43f1f8 VADDPD -0x8(%R15,%RCX,8),%ZMM12,%ZMM12 |
(323) 0x43f203 VMULPD (%R13,%RCX,8),%ZMM12,%ZMM12 |
(323) 0x43f20b VMOVUPD (%R12,%RCX,8),%ZMM13 |
(323) 0x43f212 VADDPD -0x8(%R12,%RCX,8),%ZMM13,%ZMM13 |
(323) 0x43f21d VMULPD (%R8,%RCX,8),%ZMM13,%ZMM13 |
(323) 0x43f224 VADDPD %ZMM12,%ZMM7,%ZMM7 |
(323) 0x43f22a VSUBPD %ZMM7,%ZMM8,%ZMM7 |
(323) 0x43f230 VADDPD %ZMM13,%ZMM7,%ZMM7 |
(323) 0x43f236 VMULPD %ZMM1,%ZMM10,%ZMM8 |
(323) 0x43f23c VANDPD %ZMM3,%ZMM12,%ZMM12 |
(323) 0x43f242 VANDPD %ZMM3,%ZMM13,%ZMM13 |
(323) 0x43f248 VCMPPD $0x2,%ZMM13,%ZMM9,%K1 |
(323) 0x43f24f VMOVAPD %ZMM13,%ZMM9{%K1} |
(323) 0x43f255 VCMPPD $0x2,%ZMM12,%ZMM9,%K1 |
(323) 0x43f25c VMOVAPD %ZMM12,%ZMM9{%K1} |
(323) 0x43f262 VDIVPD %ZMM9,%ZMM8,%ZMM8 |
(323) 0x43f268 VDIVPD %ZMM10,%ZMM7,%ZMM7 |
(323) 0x43f26e VMOVAPD %ZMM28,%ZMM9 |
(323) 0x43f274 VCMPPD $0x1,%ZMM4,%ZMM7,%K1 |
(323) 0x43f27b VMOVAPD %ZMM5,%ZMM28 |
(323) 0x43f281 VDIVPD %ZMM7,%ZMM0,%ZMM28{%K1} |
(323) 0x43f287 VCMPPD $0x2,%ZMM28,%ZMM8,%K1 |
(323) 0x43f28e VMOVAPD %ZMM8,%ZMM28{%K1} |
(323) 0x43f294 VCMPPD $0x2,%ZMM28,%ZMM11,%K1 |
(323) 0x43f29b VMOVAPD %ZMM11,%ZMM28{%K1} |
(323) 0x43f2a1 VCMPPD $0x2,%ZMM28,%ZMM6,%K1 |
(323) 0x43f2a8 VMOVAPD %ZMM6,%ZMM28{%K1} |
(323) 0x43f2ae VCMPPD $0x2,%ZMM28,%ZMM9,%K1 |
(323) 0x43f2b5 VMOVAPD %ZMM9,%ZMM28{%K1} |
(323) 0x43f2bb ADD $0x8,%RCX |
(323) 0x43f2bf CMP %RSI,%RCX |
(323) 0x43f2c2 JB 43f130 |
(322) 0x43f2c8 VMOVAPD %XMM28,%XMM0 |
(322) 0x43f2ce VSHUFPD $0x1,%XMM28,%XMM28,%XMM1 |
(322) 0x43f2d5 VMINSD %XMM28,%XMM1,%XMM6 |
(322) 0x43f2db VCMPSD $0x3,%XMM28,%XMM28,%K1 |
(322) 0x43f2e2 VMOVSD %XMM1,%XMM6,%XMM6{%K1} |
(322) 0x43f2e8 VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(322) 0x43f2ef VMOVAPD %YMM28,%YMM0 |
(322) 0x43f2f5 VEXTRACTF32X4 $0x1,%YMM28,%XMM0 |
(322) 0x43f2fc VMINSD %XMM6,%XMM0,%XMM1 |
(322) 0x43f300 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(322) 0x43f306 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(322) 0x43f30d VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(322) 0x43f312 VMINSD %XMM1,%XMM0,%XMM1 |
(322) 0x43f316 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(322) 0x43f31c VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(322) 0x43f323 VEXTRACTF32X4 $0x2,%ZMM28,%XMM0 |
(322) 0x43f32a VMINSD %XMM1,%XMM0,%XMM1 |
(322) 0x43f32e VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(322) 0x43f334 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(322) 0x43f33b VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(322) 0x43f340 VMINSD %XMM1,%XMM0,%XMM1 |
(322) 0x43f344 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(322) 0x43f34a VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(322) 0x43f351 VEXTRACTF32X4 $0x3,%ZMM28,%XMM0 |
(322) 0x43f358 VMINSD %XMM1,%XMM0,%XMM1 |
(322) 0x43f35c VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(322) 0x43f362 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(322) 0x43f369 VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(322) 0x43f36e VMINSD %XMM1,%XMM0,%XMM28 |
(322) 0x43f374 VMOVSD %XMM0,%XMM28,%XMM28{%K1} |
(322) 0x43f37a MOV 0x128(%RSP),%RAX |
(322) 0x43f382 CMP %RAX,%RSI |
(322) 0x43f385 JE 43eec0 |
(322) 0x43f38b VPBROADCASTQ %RAX,%ZMM0 |
(322) 0x43f391 MOV 0x34(%RSP),%R15D |
(322) 0x43f396 MOV 0x60(%RSP),%R12 |
(322) 0x43f39b MOV 0x78(%RSP),%R14 |
(322) 0x43f3a0 MOV 0x70(%RSP),%R11 |
(322) 0x43f3a5 MOV 0x118(%RSP),%R13 |
(322) 0x43f3ad MOV 0x110(%RSP),%RCX |
(322) 0x43f3b5 MOV 0x108(%RSP),%R8 |
(322) 0x43f3bd MOV 0x68(%RSP),%RDI |
(322) 0x43f3c2 MOV 0x100(%RSP),%RAX |
(322) 0x43f3ca JMP 43f414 |
0x43f3cc NOPW %CS:(%RAX,%RAX,1) |
0x43f3db NOPW %CS:(%RAX,%RAX,1) |
0x43f3ea NOPW %CS:(%RAX,%RAX,1) |
0x43f3f9 NOPL (%RAX) |
(322) 0x43f400 VPBROADCASTQ %RAX,%ZMM0 |
(322) 0x43f406 XOR %ESI,%ESI |
(322) 0x43f408 MOV %R15,%R11 |
(322) 0x43f40b MOV %R13,%RAX |
(322) 0x43f40e MOV %R9,%R13 |
(322) 0x43f411 MOV %EDX,%R15D |
(322) 0x43f414 VBROADCASTSD %XMM28,%ZMM28 |
(322) 0x43f41a VPBROADCASTQ %RSI,%ZMM1 |
(322) 0x43f420 VPSUBQ %ZMM1,%ZMM0,%ZMM0 |
(322) 0x43f426 VPCMPNLEUQ 0xca8cf(%RIP),%ZMM0,%K1 |
(322) 0x43f431 KORTESTB %K1,%K1 |
(322) 0x43f435 JE 43f7c0 |
(322) 0x43f43b ADD 0x130(%RSP),%RSI |
(322) 0x43f443 SUB 0xa0(%RSP),%RSI |
(322) 0x43f44b MOV %RAX,%R10 |
(322) 0x43f44e LEA 0x1(%RCX),%RDX |
(322) 0x43f452 MOV %R8,%RAX |
(322) 0x43f455 MOV %RCX,%R9 |
(322) 0x43f458 MOV 0x138(%RSP),%RCX |
(322) 0x43f460 MOV %RCX,%RBX |
(322) 0x43f463 IMUL %RDX,%RBX |
(322) 0x43f467 MOV %RDX,%R8 |
(322) 0x43f46a MOV 0x10(%RBP),%RDX |
(322) 0x43f46e ADD %RDX,%RBX |
(322) 0x43f471 VMOVUPD (%RBX,%RSI,8),%ZMM0{%K1}{z} |
(322) 0x43f478 VMOVUPD 0x8(%RBX,%RSI,8),%ZMM1{%K1}{z} |
(322) 0x43f483 IMUL %R9,%RCX |
(322) 0x43f487 ADD %RDX,%RCX |
(322) 0x43f48a VMOVUPD (%RCX,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f491 VMOVUPD 0x8(%RCX,%RSI,8),%ZMM7{%K1}{z} |
(322) 0x43f49c IMUL %R9,%R10 |
(322) 0x43f4a0 ADD 0x50(%RBP),%R10 |
(322) 0x43f4a4 VMOVUPD (%R10,%RSI,8),%ZMM8{%K1}{z} |
(322) 0x43f4ab VMOVUPD 0x8(%R10,%RSI,8),%ZMM9{%K1}{z} |
(322) 0x43f4b6 IMUL %R9,%RDI |
(322) 0x43f4ba ADD 0x30(%RBP),%RDI |
(322) 0x43f4be VMOVUPD (%RDI,%RSI,8),%ZMM10{%K1}{z} |
(322) 0x43f4c5 MOV %RAX,%RCX |
(322) 0x43f4c8 IMUL %R9,%RCX |
(322) 0x43f4cc MOV 0x98(%RSP),%RDX |
(322) 0x43f4d4 ADD %RDX,%RCX |
(322) 0x43f4d7 VMOVUPD 0x8(%RCX,%RSI,8),%ZMM11{%K1}{z} |
(322) 0x43f4e2 VMOVUPD (%RCX,%RSI,8),%ZMM12{%K1}{z} |
(322) 0x43f4e9 IMUL %R9,%R11 |
(322) 0x43f4ed IMUL %R9,%R14 |
(322) 0x43f4f1 MOV 0x80(%RSP),%RDI |
(322) 0x43f4f9 IMUL %R9,%RDI |
(322) 0x43f4fd VMOVAPD 0x2c0(%RSP),%ZMM13 |
(322) 0x43f505 VMOVAPD %ZMM0,%ZMM13{%K1} |
(322) 0x43f50b IMUL %R13,%R9 |
(322) 0x43f50f MOV 0x48(%RBP),%RCX |
(322) 0x43f513 ADD %RCX,%R9 |
(322) 0x43f516 VMOVUPD (%R9,%RSI,8),%ZMM0{%K1}{z} |
(322) 0x43f51d VMOVAPD 0x280(%RSP),%ZMM29 |
(322) 0x43f525 VMOVAPD %ZMM6,%ZMM29{%K1} |
(322) 0x43f52b VMOVAPD 0x240(%RSP),%ZMM30 |
(322) 0x43f533 VMOVAPD %ZMM8,%ZMM30{%K1} |
(322) 0x43f539 IMUL %R8,%RAX |
(322) 0x43f53d ADD %RDX,%RAX |
(322) 0x43f540 VMOVUPD 0x8(%RAX,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f54b VMOVUPD (%RAX,%RSI,8),%ZMM8{%K1}{z} |
(322) 0x43f552 VMOVAPD 0x200(%RSP),%ZMM31 |
(322) 0x43f55a VMOVAPD %ZMM1,%ZMM31{%K1} |
(322) 0x43f560 IMUL %R8,%R13 |
(322) 0x43f564 VMOVAPD 0x1c0(%RSP),%ZMM14 |
(322) 0x43f56c VMOVAPD %ZMM7,%ZMM14{%K1} |
(322) 0x43f572 ADD %RCX,%R13 |
(322) 0x43f575 VMOVUPD (%R13,%RSI,8),%ZMM1{%K1}{z} |
(322) 0x43f57d VMOVAPD 0x180(%RSP),%ZMM16 |
(322) 0x43f585 VMOVAPD %ZMM9,%ZMM16{%K1} |
(322) 0x43f58b VMOVAPD %ZMM10,%ZMM15{%K1} |
(322) 0x43f591 VMOVAPD %ZMM13,0x2c0(%RSP) |
(322) 0x43f599 VMOVAPD %ZMM29,0x280(%RSP) |
(322) 0x43f5a1 VADDPD %ZMM29,%ZMM13,%ZMM7 |
(322) 0x43f5a7 VMOVAPD %ZMM30,0x240(%RSP) |
(322) 0x43f5af VMULPD %ZMM7,%ZMM30,%ZMM7 |
(322) 0x43f5b5 VMOVAPD 0x140(%RSP),%ZMM13 |
(322) 0x43f5bd VMOVAPD %ZMM11,%ZMM13{%K1} |
(322) 0x43f5c3 VMOVAPD %ZMM31,0x200(%RSP) |
(322) 0x43f5cb VMOVAPD %ZMM14,0x1c0(%RSP) |
(322) 0x43f5d3 VADDPD %ZMM14,%ZMM31,%ZMM9 |
(322) 0x43f5d9 VMOVAPD %ZMM16,0x180(%RSP) |
(322) 0x43f5e1 VMULPD %ZMM16,%ZMM9,%ZMM9 |
(322) 0x43f5e7 VMOVAPD %ZMM12,%ZMM17{%K1} |
(322) 0x43f5ed VADDPD %ZMM15,%ZMM15,%ZMM10 |
(322) 0x43f5f3 VMOVAPD %ZMM0,%ZMM18{%K1} |
(322) 0x43f5f9 VMOVAPD %ZMM13,0x140(%RSP) |
(322) 0x43f601 VADDPD %ZMM17,%ZMM13,%ZMM0 |
(322) 0x43f607 VMULPD %ZMM0,%ZMM18,%ZMM11 |
(322) 0x43f60d VMOVAPD %ZMM6,%ZMM19{%K1} |
(322) 0x43f613 VMOVAPD %ZMM8,%ZMM20{%K1} |
(322) 0x43f619 VADDPD %ZMM20,%ZMM19,%ZMM0 |
(322) 0x43f61f VMOVAPD %ZMM1,%ZMM21{%K1} |
(322) 0x43f625 VMULPD %ZMM21,%ZMM0,%ZMM1 |
(322) 0x43f62b VADDPD %ZMM11,%ZMM7,%ZMM0 |
(322) 0x43f631 VSUBPD %ZMM0,%ZMM9,%ZMM0 |
(322) 0x43f637 VADDPD %ZMM1,%ZMM0,%ZMM0 |
(322) 0x43f63d VDIVPD %ZMM10,%ZMM0,%ZMM6 |
(322) 0x43f643 VBROADCASTSD %XMM27,%ZMM8 |
(322) 0x43f649 VCMPPD $0x1,%ZMM4,%ZMM6,%K2 |
(322) 0x43f650 VMOVAPD %ZMM5,%ZMM0 |
(322) 0x43f656 VDIVPD %ZMM6,%ZMM8,%ZMM0{%K2} |
(322) 0x43f65c MOV 0x40(%RBP),%RAX |
(322) 0x43f660 VMOVUPD (%RAX,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f667 VMOVAPD %ZMM6,%ZMM22{%K1} |
(322) 0x43f66d ADD 0x18(%RBP),%R11 |
(322) 0x43f671 VMOVUPD (%R11,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f678 VMOVAPD 0x380(%RSP),%ZMM8 |
(322) 0x43f680 VMOVAPD %ZMM6,%ZMM8{%K1} |
(322) 0x43f686 ADD 0x20(%RBP),%R14 |
(322) 0x43f68a VMOVUPD (%R14,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f691 VMOVAPD 0x340(%RSP),%ZMM12 |
(322) 0x43f699 VMOVAPD %ZMM6,%ZMM12{%K1} |
(322) 0x43f69f MOV %RDI,%RAX |
(322) 0x43f6a2 ADD 0x28(%RBP),%RAX |
(322) 0x43f6a6 VMOVUPD (%RAX,%RSI,8),%ZMM6{%K1}{z} |
(322) 0x43f6ad VMOVAPD 0x300(%RSP),%ZMM13 |
(322) 0x43f6b5 VMOVAPD %ZMM6,%ZMM13{%K1} |
(322) 0x43f6bb VMOVAPD %ZMM12,0x340(%RSP) |
(322) 0x43f6c3 VADDPD %ZMM12,%ZMM12,%ZMM6 |
(322) 0x43f6c9 VMOVAPD %ZMM13,0x300(%RSP) |
(322) 0x43f6d1 VDIVPD %ZMM13,%ZMM6,%ZMM6 |
(322) 0x43f6d7 VMOVAPD %ZMM8,0x380(%RSP) |
(322) 0x43f6df VFMADD231PD %ZMM8,%ZMM8,%ZMM6 |
(322) 0x43f6e5 VSQRTPD %ZMM6,%ZMM6 |
(322) 0x43f6eb VBROADCASTSD %XMM23,%ZMM8 |
(322) 0x43f6f1 VMINPD %ZMM8,%ZMM22,%ZMM8 |
(322) 0x43f6f7 VBROADCASTSD %XMM25,%ZMM12 |
(322) 0x43f6fd VMULPD %ZMM8,%ZMM12,%ZMM8 |
(322) 0x43f703 VMAXPD %ZMM2,%ZMM6,%ZMM6 |
(322) 0x43f709 VDIVPD %ZMM6,%ZMM8,%ZMM6 |
(322) 0x43f70f VANDPD %ZMM3,%ZMM7,%ZMM7 |
(322) 0x43f715 VANDPD %ZMM3,%ZMM9,%ZMM8 |
(322) 0x43f71b VMULPD %ZMM2,%ZMM15,%ZMM9 |
(322) 0x43f721 VCMPPD $0x2,%ZMM8,%ZMM9,%K2 |
(322) 0x43f728 VBLENDMPD %ZMM8,%ZMM9,%ZMM8{%K2} |
(322) 0x43f72e VCMPPD $0x2,%ZMM7,%ZMM8,%K2 |
(322) 0x43f735 VMOVAPD %ZMM7,%ZMM8{%K2} |
(322) 0x43f73b VBROADCASTSD %XMM24,%ZMM7 |
(322) 0x43f741 VMULPD %ZMM7,%ZMM10,%ZMM7 |
(322) 0x43f747 VDIVPD %ZMM8,%ZMM7,%ZMM7 |
(322) 0x43f74d VBROADCASTSD %XMM26,%ZMM8 |
(322) 0x43f753 VMULPD %ZMM8,%ZMM10,%ZMM8 |
(322) 0x43f759 VANDPD %ZMM3,%ZMM1,%ZMM1 |
(322) 0x43f75f VCMPPD $0x2,%ZMM1,%ZMM9,%K2 |
(322) 0x43f766 VMOVAPD %ZMM1,%ZMM9{%K2} |
(322) 0x43f76c VANDPD %ZMM3,%ZMM11,%ZMM1 |
(322) 0x43f772 VCMPPD $0x2,%ZMM1,%ZMM9,%K2 |
(322) 0x43f779 VMOVAPD %ZMM1,%ZMM9{%K2} |
(322) 0x43f77f VDIVPD %ZMM9,%ZMM8,%ZMM1 |
(322) 0x43f785 VCMPPD $0x2,%ZMM0,%ZMM1,%K2 |
(322) 0x43f78c VMOVAPD %ZMM1,%ZMM0{%K2} |
(322) 0x43f792 VCMPPD $0x2,%ZMM0,%ZMM7,%K2 |
(322) 0x43f799 VMOVAPD %ZMM7,%ZMM0{%K2} |
(322) 0x43f79f VCMPPD $0x2,%ZMM0,%ZMM6,%K2 |
(322) 0x43f7a6 VMOVAPD %ZMM6,%ZMM0{%K2} |
(322) 0x43f7ac VCMPPD $0x2,%ZMM0,%ZMM28,%K2 |
(322) 0x43f7b3 VMOVAPD %ZMM28,%ZMM0{%K2} |
(322) 0x43f7b9 JMP 43f7c4 |
0x43f7bb NOPL (%RAX,%RAX,1) |
(322) 0x43f7c0 VPXOR %XMM0,%XMM0,%XMM0 |
(322) 0x43f7c4 VMOVAPD %ZMM0,%ZMM28{%K1} |
(322) 0x43f7ca VEXTRACTF32X4 $0x3,%ZMM28,%XMM0 |
(322) 0x43f7d1 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(322) 0x43f7d6 VEXTRACTF32X4 $0x2,%ZMM28,%XMM6 |
(322) 0x43f7dd VSHUFPD $0x1,%XMM6,%XMM6,%XMM7 |
(322) 0x43f7e2 VMOVAPD %YMM28,%YMM8 |
(322) 0x43f7e8 VEXTRACTF32X4 $0x1,%YMM28,%XMM8 |
(322) 0x43f7ef VSHUFPD $0x1,%XMM8,%XMM8,%XMM9 |
(322) 0x43f7f5 VMOVAPD %XMM28,%XMM10 |
(322) 0x43f7fb VSHUFPD $0x1,%XMM28,%XMM28,%XMM11 |
(322) 0x43f802 VMINSD %XMM28,%XMM11,%XMM12 |
(322) 0x43f808 VCMPSD $0x3,%XMM28,%XMM28,%K1 |
(322) 0x43f80f VMOVSD %XMM11,%XMM12,%XMM12{%K1} |
(322) 0x43f815 VCMPSD $0x3,%XMM12,%XMM12,%K1 |
(322) 0x43f81c VMINSD %XMM12,%XMM8,%XMM10 |
(322) 0x43f821 VMOVSD %XMM8,%XMM10,%XMM10{%K1} |
(322) 0x43f827 VCMPSD $0x3,%XMM10,%XMM10,%K1 |
(322) 0x43f82e VMINSD %XMM10,%XMM9,%XMM8 |
(322) 0x43f833 VMOVSD %XMM9,%XMM8,%XMM8{%K1} |
(322) 0x43f839 VCMPSD $0x3,%XMM8,%XMM8,%K1 |
(322) 0x43f840 VMINSD %XMM8,%XMM6,%XMM8 |
(322) 0x43f845 VMOVSD %XMM6,%XMM8,%XMM8{%K1} |
(322) 0x43f84b VCMPSD $0x3,%XMM8,%XMM8,%K1 |
(322) 0x43f852 VMINSD %XMM8,%XMM7,%XMM6 |
(322) 0x43f857 VMOVSD %XMM7,%XMM6,%XMM6{%K1} |
(322) 0x43f85d VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(322) 0x43f864 VMINSD %XMM6,%XMM0,%XMM6 |
(322) 0x43f868 VMOVSD %XMM0,%XMM6,%XMM6{%K1} |
(322) 0x43f86e VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(322) 0x43f875 VMINSD %XMM6,%XMM1,%XMM0 |
(322) 0x43f879 VMOVSD %XMM1,%XMM0,%XMM0{%K1} |
(322) 0x43f87f VMOVDDUP %XMM0,%XMM28 |
(322) 0x43f885 JMP 43eed0 |
0x43f88a NOPW %CS:(%RAX,%RAX,1) |
0x43f899 NOPW %CS:(%RAX,%RAX,1) |
0x43f8a8 NOPW %CS:(%RAX,%RAX,1) |
0x43f8b7 NOPW (%RAX,%RAX,1) |
0x43f8c0 VSHUFPD $0x1,%XMM28,%XMM28,%XMM0 |
0x43f8c7 VMOVSD %XMM0,0x88(%RSP) |
0x43f8d0 MOV $0x74d0d0,%EDI |
0x43f8d5 MOV 0x40(%RSP),%ESI |
0x43f8d9 VZEROUPPER |
0x43f8dc CALL 4040b0 <__kmpc_for_static_fini@plt> |
0x43f8e1 MOV 0x50(%RSP),%RBX |
0x43f8e6 MOV (%RBX),%ESI |
0x43f8e8 SUB $0x8,%RSP |
0x43f8ec LEA 0x90(%RSP),%R8 |
0x43f8f4 MOV $0x74d0f0,%EDI |
0x43f8f9 MOV $0x43f970,%R9D |
0x43f8ff MOV $0x1,%EDX |
0x43f904 MOV $0x8,%ECX |
0x43f909 PUSH $0x75433c |
0x43f90e CALL 4046a0 <__kmpc_reduce@plt> |
0x43f913 MOV %RBX,%RDI |
0x43f916 ADD $0x10,%RSP |
0x43f91a CMP $0x1,%EAX |
0x43f91d MOV 0x90(%RSP),%RAX |
0x43f925 JNE 43f94e |
0x43f927 VMOVSD 0x88(%RSP),%XMM0 |
0x43f930 VMINSD (%RAX),%XMM0,%XMM0 |
0x43f934 VMOVSD %XMM0,(%RAX) |
0x43f938 MOV (%RDI),%ESI |
0x43f93a MOV $0x74d110,%EDI |
0x43f93f MOV $0x75433c,%EDX |
0x43f944 CALL 404820 <__kmpc_end_reduce@plt> |
0x43f949 MOV 0x50(%RSP),%RDI |
0x43f94e MOV (%RDI),%ESI |
0x43f950 MOV $0x74d130,%EDI |
0x43f955 CALL 404580 <__kmpc_barrier@plt> |
0x43f95a LEA -0x28(%RBP),%RSP |
0x43f95e POP %RBX |
0x43f95f POP %R12 |
0x43f961 POP %R13 |
0x43f963 POP %R14 |
0x43f965 POP %R15 |
0x43f967 POP %RBP |
0x43f968 RET |
0x43f969 NOPL (%RAX) |
Path / |
Source file and lines | calc_dt_kernel.f90:89-133 |
Module | exec |
nb instructions | 178 |
nb uops | 184 |
loop length | 927 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 4 |
nb stack references | 36 |
micro-operation queue | 30.67 cycles |
front end | 30.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.90 | 12.80 | 12.33 | 12.33 | 20.00 | 12.80 | 12.70 | 20.00 | 20.00 | 20.00 | 12.80 | 12.33 |
cycles | 12.90 | 12.80 | 12.33 | 12.33 | 20.00 | 12.80 | 12.70 | 20.00 | 20.00 | 20.00 | 12.80 | 12.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 29.87 |
Stall cycles | 0.00 |
Front-end | 30.67 |
Dispatch | 20.00 |
Overall L1 | 30.67 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 9% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 6% |
all | 10% |
load | 8% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 14% |
all | 11% |
load | 10% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x400,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVL $0,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 43f94e <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xd0e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x50(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x54(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x44(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x40(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74d0b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4044c0 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x3c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 43ed00 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0xcc017(%RIP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 43f8c7 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc87> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x20,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $-0x200000000,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
LEA (%R12,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x20,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $-0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNS %RDI,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RSI,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x200000000,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV %RBX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R12,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RDI,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %R8,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0x8,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R14,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVG %RSI,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R15,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RCX,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RDX,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R9,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NEG %RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R13,%RDI,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0x10(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDI,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDDUP 0xcbeb2(%RIP),%XMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD 0xcbe58(%RIP),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcbe16(%RIP),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcbe9c(%RIP),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcbe9a(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV 0x90(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%RAX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43eee6 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x2a6> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VSHUFPD $0x1,%XMM28,%XMM28,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x74d0d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x40(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4040b0 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x50(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x90(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74d0f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x43f970,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x75433c | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4046a0 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 43f94e <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xd0e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0x88(%RSP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMINSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74d110,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x75433c,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404820 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x50(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74d130,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404580 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | calc_dt_kernel.f90:89-133 |
Module | exec |
nb instructions | 178 |
nb uops | 184 |
loop length | 927 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 4 |
nb stack references | 36 |
micro-operation queue | 30.67 cycles |
front end | 30.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.90 | 12.80 | 12.33 | 12.33 | 20.00 | 12.80 | 12.70 | 20.00 | 20.00 | 20.00 | 12.80 | 12.33 |
cycles | 12.90 | 12.80 | 12.33 | 12.33 | 20.00 | 12.80 | 12.70 | 20.00 | 20.00 | 20.00 | 12.80 | 12.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 29.87 |
Stall cycles | 0.00 |
Front-end | 30.67 |
Dispatch | 20.00 |
Overall L1 | 30.67 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 9% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 6% |
all | 10% |
load | 8% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 14% |
all | 11% |
load | 10% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x400,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVL $0,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 43f94e <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xd0e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x50(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x54(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x44(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x40(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74d0b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4044c0 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x3c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 43ed00 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0xcc017(%RIP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 43f8c7 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc87> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x48(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x20,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $-0x200000000,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
LEA (%R12,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x20,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
TEST %RDI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $-0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNS %RDI,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RSI,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x200000000,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV %RBX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R12,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RDI,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %R8,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0x8,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R14,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVG %RSI,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R15,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RCX,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RDX,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R9,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NEG %RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R13,%RDI,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0x10(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDI,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDDUP 0xcbeb2(%RIP),%XMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD 0xcbe58(%RIP),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcbe16(%RIP),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcbe9c(%RIP),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xcbe9a(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV 0x90(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%RAX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43eee6 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x2a6> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VSHUFPD $0x1,%XMM28,%XMM28,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x74d0d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x40(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4040b0 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x50(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x90(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74d0f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x43f970,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x75433c | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4046a0 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x90(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 43f94e <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xd0e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0x88(%RSP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMINSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74d110,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x75433c,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404820 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x50(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74d130,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404580 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼calc_dt_kernel_.DIR.OMP.PARALLEL.2– | 4.94 | 1.54 |
▼Loop 322 - calc_dt_kernel.f90:92-129 - exec– | 0 | 0 |
○Loop 323 - calc_dt_kernel.f90:94-129 - exec | 4.94 | 1.51 |