Function: __pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0 | Module: exec | Source: pack_kernel.f90:108-113 | Coverage: 0.03% |
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Function: __pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0 | Module: exec | Source: pack_kernel.f90:108-113 | Coverage: 0.03% |
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/scratch_na/users/xoserete/qaas_runs/171-214-9740/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/pack_kernel.f90: 108 - 113 |
-------------------------------------------------------------------------------- |
108: !$OMP PARALLEL DO PRIVATE(index) |
109: DO k=y_min-depth,y_max+y_inc+depth |
110: !$OMP SIMD |
111: DO j=1,depth |
112: index= buffer_offset + j+(k+depth-1)*depth |
113: field(x_min-j,k)=left_rcv_buffer(index) |
0x434000 PUSH %RBP |
0x434001 MOV %RSP,%RBP |
0x434004 PUSH %R15 |
0x434006 PUSH %R14 |
0x434008 MOV %RDI,%R14 |
0x43400b PUSH %R13 |
0x43400d PUSH %R12 |
0x43400f PUSH %RBX |
0x434010 AND $-0x20,%RSP |
0x434014 SUB $0xa0,%RSP |
0x43401b MOV 0x28(%RDI),%RDX |
0x43401f MOV 0x30(%RDI),%RAX |
0x434023 MOV 0x20(%RDI),%RCX |
0x434027 MOV 0x54(%RDI),%R12D |
0x43402b MOV 0x48(%RDI),%RBX |
0x43402f MOV 0x40(%RDI),%R13 |
0x434033 MOV %RDX,0x88(%RSP) |
0x43403b MOV %RCX,0x90(%RSP) |
0x434043 MOV %RAX,0x68(%RSP) |
0x434048 CALL 402080 <@plt_start@+0x60> |
0x43404d MOV %EAX,%R15D |
0x434050 CALL 402180 <@plt_start@+0x160> |
0x434055 MOV %EAX,%ESI |
0x434057 MOV 0x58(%R14),%EAX |
0x43405b INC %EAX |
0x43405d SUB %R12D,%EAX |
0x434060 CLTD |
0x434061 IDIV %R15D |
0x434064 CMP %EDX,%ESI |
0x434066 JL 434479 |
0x43406c IMUL %EAX,%ESI |
0x43406f ADD %EDX,%ESI |
0x434071 ADD %ESI,%EAX |
0x434073 CMP %EAX,%ESI |
0x434075 JGE 434405 |
0x43407b ADD %R12D,%EAX |
0x43407e CMPQ $0x1,0x90(%RSP) |
0x434087 LEA (%R12,%RSI,1),%EDI |
0x43408b MOV 0x8(%R14),%R8 |
0x43408f SETNE %R12B |
0x434093 CMP $0x1,%R13 |
0x434097 MOV 0x10(%R14),%R9 |
0x43409b MOV (%R14),%R10 |
0x43409e SETNE %CL |
0x4340a1 MOV (%R8),%R11D |
0x4340a4 MOV 0x38(%R14),%R8 |
0x4340a8 MOV %EDI,0x9c(%RSP) |
0x4340af OR %CL,%R12B |
0x4340b2 MOV %R9,0x78(%RSP) |
0x4340b7 MOV 0x18(%R14),%R9 |
0x4340bb MOV %EAX,0x84(%RSP) |
0x4340c2 MOV %R10,0x70(%RSP) |
0x4340c7 MOV %R12B,0x83(%RSP) |
0x4340cf JNE 434482 |
0x4340d5 MOV 0x88(%RSP),%RAX |
0x4340dd MOVSXD %EDI,%RSI |
0x4340e0 LEA -0x1(%R11),%R13D |
0x4340e4 MOV 0x68(%RSP),%RDX |
0x4340e9 LEA (%RSI,%R13,1),%EDI |
0x4340ed MOV %R11D,%R12D |
0x4340f0 MOV %R11D,%R15D |
0x4340f3 XOR %R10D,%R10D |
0x4340f6 IMUL %RAX,%RSI |
0x4340fa AND $-0x4,%R15D |
0x4340fe SHR $0x2,%R12D |
0x434102 LEA 0x1(%RBX),%RCX |
0x434106 SAL $0x5,%R12 |
0x43410a IMUL %R11D,%EDI |
0x43410e MOV %R15D,0x98(%RSP) |
0x434116 INC %R15D |
0x434119 MOV %R13D,0x90(%RSP) |
0x434121 ADD %RDX,%RSI |
0x434124 TEST %R11D,%R11D |
0x434127 MOV %R12,0x68(%RSP) |
0x43412c CMOVNS %R11D,%R10D |
0x434130 MOV %R15D,0x58(%RSP) |
0x434135 MOV %RCX,0x60(%RSP) |
0x43413a INC %R10D |
0x43413d MOV %R14,0x48(%RSP) |
0x434142 MOV %R10D,0x54(%RSP) |
0x434147 NOPW (%RAX,%RAX,1) |
(236) 0x434150 TEST %R11D,%R11D |
(236) 0x434153 JLE 4343c3 |
(236) 0x434159 MOV 0x78(%RSP),%R14 |
(236) 0x43415e MOV 0x70(%RSP),%R13 |
(236) 0x434163 CMPL $0x2,0x90(%RSP) |
(236) 0x43416b MOV (%R14),%EAX |
(236) 0x43416e MOV (%R13),%EDX |
(236) 0x434172 JBE 43446c |
(236) 0x434178 MOV 0x60(%RSP),%R10 |
(236) 0x43417d MOV 0x68(%RSP),%R12 |
(236) 0x434182 MOVSXD %EAX,%R15 |
(236) 0x434185 MOVSXD %EDI,%R14 |
(236) 0x434188 MOVSXD %EDX,%R13 |
(236) 0x43418b ADD %R10,%R15 |
(236) 0x43418e ADD %RSI,%R13 |
(236) 0x434191 ADD %R14,%R15 |
(236) 0x434194 LEA -0x20(%R12),%R14 |
(236) 0x434199 LEA -0x20(%R9,%R13,8),%R10 |
(236) 0x43419e SHR $0x5,%R14 |
(236) 0x4341a2 LEA (%R8,%R15,8),%RCX |
(236) 0x4341a6 INC %R14 |
(236) 0x4341a9 LEA (%R12,%RCX,1),%R15 |
(236) 0x4341ad AND $0x7,%R14D |
(236) 0x4341b1 JE 434295 |
(236) 0x4341b7 CMP $0x1,%R14 |
(236) 0x4341bb JE 434274 |
(236) 0x4341c1 CMP $0x2,%R14 |
(236) 0x4341c5 JE 43425c |
(236) 0x4341cb CMP $0x3,%R14 |
(236) 0x4341cf JE 434244 |
(236) 0x4341d1 CMP $0x4,%R14 |
(236) 0x4341d5 JE 43422c |
(236) 0x4341d7 CMP $0x5,%R14 |
(236) 0x4341db JE 434214 |
(236) 0x4341dd CMP $0x6,%R14 |
(236) 0x4341e1 JE 4341fc |
(236) 0x4341e3 VXORPS %XMM15,%XMM15,%XMM15 |
(236) 0x4341e8 VPERMPD $0x1b,(%RCX),%YMM15 |
(236) 0x4341ee SUB $0x20,%R10 |
(236) 0x4341f2 ADD $0x20,%RCX |
(236) 0x4341f6 VMOVUPD %YMM15,0x20(%R10) |
(236) 0x4341fc VXORPS %XMM3,%XMM3,%XMM3 |
(236) 0x434200 VPERMPD $0x1b,(%RCX),%YMM3 |
(236) 0x434206 SUB $0x20,%R10 |
(236) 0x43420a ADD $0x20,%RCX |
(236) 0x43420e VMOVUPD %YMM3,0x20(%R10) |
(236) 0x434214 VXORPS %XMM2,%XMM2,%XMM2 |
(236) 0x434218 VPERMPD $0x1b,(%RCX),%YMM2 |
(236) 0x43421e SUB $0x20,%R10 |
(236) 0x434222 ADD $0x20,%RCX |
(236) 0x434226 VMOVUPD %YMM2,0x20(%R10) |
(236) 0x43422c VXORPS %XMM1,%XMM1,%XMM1 |
(236) 0x434230 VPERMPD $0x1b,(%RCX),%YMM1 |
(236) 0x434236 SUB $0x20,%R10 |
(236) 0x43423a ADD $0x20,%RCX |
(236) 0x43423e VMOVUPD %YMM1,0x20(%R10) |
(236) 0x434244 VXORPS %XMM0,%XMM0,%XMM0 |
(236) 0x434248 VPERMPD $0x1b,(%RCX),%YMM0 |
(236) 0x43424e SUB $0x20,%R10 |
(236) 0x434252 ADD $0x20,%RCX |
(236) 0x434256 VMOVUPD %YMM0,0x20(%R10) |
(236) 0x43425c VXORPS %XMM4,%XMM4,%XMM4 |
(236) 0x434260 VPERMPD $0x1b,(%RCX),%YMM4 |
(236) 0x434266 SUB $0x20,%R10 |
(236) 0x43426a ADD $0x20,%RCX |
(236) 0x43426e VMOVUPD %YMM4,0x20(%R10) |
(236) 0x434274 VXORPS %XMM5,%XMM5,%XMM5 |
(236) 0x434278 VPERMPD $0x1b,(%RCX),%YMM5 |
(236) 0x43427e ADD $0x20,%RCX |
(236) 0x434282 SUB $0x20,%R10 |
(236) 0x434286 VMOVUPD %YMM5,0x20(%R10) |
(236) 0x43428c CMP %RCX,%R15 |
(236) 0x43428f JE 434351 |
(237) 0x434295 VXORPS %XMM6,%XMM6,%XMM6 |
(237) 0x434299 VPERMPD $0x1b,(%RCX),%YMM6 |
(237) 0x43429f ADD $0x100,%RCX |
(237) 0x4342a6 SUB $0x100,%R10 |
(237) 0x4342ad VMOVUPD %YMM6,0x100(%R10) |
(237) 0x4342b6 VXORPS %XMM7,%XMM7,%XMM7 |
(237) 0x4342ba VPERMPD $0x1b,-0xe0(%RCX),%YMM7 |
(237) 0x4342c4 VMOVUPD %YMM7,0xe0(%R10) |
(237) 0x4342cd VXORPS %XMM8,%XMM8,%XMM8 |
(237) 0x4342d2 VPERMPD $0x1b,-0xc0(%RCX),%YMM8 |
(237) 0x4342dc VMOVUPD %YMM8,0xc0(%R10) |
(237) 0x4342e5 VXORPS %XMM9,%XMM9,%XMM9 |
(237) 0x4342ea VPERMPD $0x1b,-0xa0(%RCX),%YMM9 |
(237) 0x4342f4 VMOVUPD %YMM9,0xa0(%R10) |
(237) 0x4342fd VXORPS %XMM10,%XMM10,%XMM10 |
(237) 0x434302 VPERMPD $0x1b,-0x80(%RCX),%YMM10 |
(237) 0x434309 VMOVUPD %YMM10,0x80(%R10) |
(237) 0x434312 VXORPS %XMM11,%XMM11,%XMM11 |
(237) 0x434317 VPERMPD $0x1b,-0x60(%RCX),%YMM11 |
(237) 0x43431e VMOVUPD %YMM11,0x60(%R10) |
(237) 0x434324 VXORPS %XMM12,%XMM12,%XMM12 |
(237) 0x434329 VPERMPD $0x1b,-0x40(%RCX),%YMM12 |
(237) 0x434330 VMOVUPD %YMM12,0x40(%R10) |
(237) 0x434336 VXORPS %XMM13,%XMM13,%XMM13 |
(237) 0x43433b VPERMPD $0x1b,-0x20(%RCX),%YMM13 |
(237) 0x434342 VMOVUPD %YMM13,0x20(%R10) |
(237) 0x434348 CMP %RCX,%R15 |
(237) 0x43434b JNE 434295 |
(236) 0x434351 MOV 0x98(%RSP),%ECX |
(236) 0x434358 CMP %R11D,%ECX |
(236) 0x43435b JE 4343c3 |
(236) 0x43435d MOV %ECX,%R12D |
(236) 0x434360 MOV 0x58(%RSP),%ECX |
(236) 0x434364 MOV %R11D,%R13D |
(236) 0x434367 SUB %R12D,%R13D |
(236) 0x43436a CMP $0x1,%R13D |
(236) 0x43436e JE 4343a6 |
(236) 0x434370 MOVSXD %EAX,%R10 |
(236) 0x434373 LEA (%RBX,%R12,1),%R15 |
(236) 0x434377 MOVSXD %EDI,%R14 |
(236) 0x43437a ADD %R15,%R10 |
(236) 0x43437d LEA 0x1(%R14,%R10,1),%R10 |
(236) 0x434382 MOVSXD %EDX,%R14 |
(236) 0x434385 VPERMILPD $0x1,(%R8,%R10,8),%XMM14 |
(236) 0x43438c ADD %RSI,%R14 |
(236) 0x43438f SUB %R12,%R14 |
(236) 0x434392 VMOVUPD %XMM14,-0x10(%R9,%R14,8) |
(236) 0x434399 TEST $0x1,%R13B |
(236) 0x43439d JE 4343c3 |
(236) 0x43439f AND $-0x2,%R13D |
(236) 0x4343a3 ADD %R13D,%ECX |
(236) 0x4343a6 ADD %ECX,%EAX |
(236) 0x4343a8 SUB %ECX,%EDX |
(236) 0x4343aa ADD %EDI,%EAX |
(236) 0x4343ac CLTQ |
(236) 0x4343ae ADD %RBX,%RAX |
(236) 0x4343b1 VMOVSD (%R8,%RAX,8),%XMM15 |
(236) 0x4343b7 MOVSXD %EDX,%RAX |
(236) 0x4343ba ADD %RSI,%RAX |
(236) 0x4343bd VMOVSD %XMM15,(%R9,%RAX,8) |
(236) 0x4343c3 INCL 0x9c(%RSP) |
(236) 0x4343ca ADD %R11D,%EDI |
(236) 0x4343cd MOV 0x9c(%RSP),%R12D |
(236) 0x4343d5 TEST %R11D,%R11D |
(236) 0x4343d8 JNS 434440 |
(236) 0x4343da MOV 0x88(%RSP),%RDX |
(236) 0x4343e2 ADD %RDX,%RSI |
(236) 0x4343e5 CMP %R12D,0x84(%RSP) |
(236) 0x4343ed JG 434150 |
0x4343f3 MOV 0x48(%RSP),%RBX |
0x4343f8 VZEROUPPER |
0x4343fb CMPB $0,0x83(%RSP) |
0x434403 JNE 434426 |
0x434405 LEA -0x28(%RBP),%RSP |
0x434409 POP %RBX |
0x43440a POP %R12 |
0x43440c POP %R13 |
0x43440e POP %R14 |
0x434410 POP %R15 |
0x434412 POP %RBP |
0x434413 RET |
0x434414 MOV 0x48(%RSP),%RBX |
0x434419 VZEROUPPER |
0x43441c MOV 0x54(%RSP),%R9D |
0x434421 MOV %R9D,0x50(%RSP) |
0x434426 MOV 0x50(%RSP),%R11D |
0x43442b MOV %R11D,0x50(%RBX) |
0x43442f LEA -0x28(%RBP),%RSP |
0x434433 POP %RBX |
0x434434 POP %R12 |
0x434436 POP %R13 |
0x434438 POP %R14 |
0x43443a POP %R15 |
0x43443c POP %RBP |
0x43443d RET |
0x43443e XCHG %AX,%AX |
(236) 0x434440 MOV 0x88(%RSP),%RCX |
(236) 0x434448 ADD %RCX,%RSI |
(236) 0x43444b CMP %R12D,0x84(%RSP) |
(236) 0x434453 JLE 434414 |
(236) 0x434455 MOV 0x54(%RSP),%R13D |
(236) 0x43445a MOVB $0x1,0x83(%RSP) |
(236) 0x434462 MOV %R13D,0x50(%RSP) |
(236) 0x434467 JMP 434150 |
(236) 0x43446c XOR %R12D,%R12D |
(236) 0x43446f MOV $0x1,%ECX |
(236) 0x434474 JMP 434364 |
0x434479 INC %EAX |
0x43447b XOR %EDX,%EDX |
0x43447d JMP 43406c |
0x434482 MOV 0x88(%RSP),%RSI |
0x43448a MOVSXD %EDI,%RAX |
0x43448d MOV 0x68(%RSP),%R12 |
0x434492 LEA -0x1(%R11),%R15D |
0x434496 KXORB %K0,%K0,%K0 |
0x43449a MOV %R15D,0x2c(%RSP) |
0x43449f ADD %EDI,%R15D |
0x4344a2 MOV %R11D,%EDX |
0x4344a5 LEA (,%R13,8),%RDI |
0x4344ad IMUL %RSI,%RAX |
0x4344b1 MOV 0x90(%RSP),%RSI |
0x4344b9 SHR $0x2,%EDX |
0x4344bc MOV %RDI,0x30(%RSP) |
0x4344c1 IMUL %R11D,%R15D |
0x4344c5 MOV %EDX,0x60(%RSP) |
0x4344c9 MOV %R13,%RCX |
0x4344cc LEA (,%RSI,4),%RDX |
0x4344d4 SAL $0x4,%RCX |
0x4344d8 MOV %R11D,0x68(%RSP) |
0x4344dd ADD %RAX,%R12 |
0x4344e0 MOV %RSI,%RAX |
0x4344e3 SUB %RDX,%RSI |
0x4344e6 MOV %RCX,0x20(%RSP) |
0x4344eb NEG %RAX |
0x4344ee MOV %R15D,0x98(%RSP) |
0x4344f6 MOV %R13,%R15 |
0x4344f9 SAL $0x3,%RSI |
0x4344fd MOV %RAX,%R10 |
0x434500 LEA (,%RAX,8),%RDI |
0x434508 SAL $0x4,%RAX |
0x43450c MOV %RSI,0x38(%RSP) |
0x434511 MOV %RAX,0x40(%RSP) |
0x434516 SAL $0x5,%R10 |
0x43451a MOV %R11D,%EAX |
0x43451d SAL $0x5,%R15 |
0x434521 AND $-0x4,%EAX |
0x434524 MOV %R10,0x48(%RSP) |
0x434529 XOR %R10D,%R10D |
0x43452c MOV %EAX,0x28(%RSP) |
0x434530 INC %EAX |
0x434532 TEST %R11D,%R11D |
0x434535 CMOVNS %R11D,%R10D |
0x434539 MOV %EAX,0xc(%RSP) |
0x43453d MOV %RDI,%R11 |
0x434540 MOV %R15,0x58(%RSP) |
0x434545 INC %R10D |
0x434548 MOV %R14,(%RSP) |
0x43454c MOV %R12,%R14 |
0x43454f MOV %R10D,0x54(%RSP) |
0x434554 NOPL (%RAX) |
(234) 0x434558 MOV 0x68(%RSP),%R12D |
(234) 0x43455d TEST %R12D,%R12D |
(234) 0x434560 JLE 4348a1 |
(234) 0x434566 MOV 0x78(%RSP),%R15 |
(234) 0x43456b MOV 0x70(%RSP),%RDI |
(234) 0x434570 CMPL $0x2,0x2c(%RSP) |
(234) 0x434575 MOV (%R15),%EAX |
(234) 0x434578 MOV (%RDI),%EDX |
(234) 0x43457a JBE 434951 |
(234) 0x434580 MOVSXD 0x98(%RSP),%RSI |
(234) 0x434588 MOV 0x90(%RSP),%RDI |
(234) 0x434590 MOVSXD %EDX,%R15 |
(234) 0x434593 MOVSXD %EAX,%R10 |
(234) 0x434596 DEC %R15 |
(234) 0x434599 IMUL %RDI,%R15 |
(234) 0x43459d LEA 0x1(%R10,%RSI,1),%R12 |
(234) 0x4345a2 MOV 0x20(%RSP),%RSI |
(234) 0x4345a7 XOR %EDI,%EDI |
(234) 0x4345a9 IMUL %R13,%R12 |
(234) 0x4345ad ADD %R14,%R15 |
(234) 0x4345b0 ADD %RBX,%R12 |
(234) 0x4345b3 LEA (%R9,%R15,8),%RCX |
(234) 0x4345b7 MOV 0x60(%RSP),%R15D |
(234) 0x4345bc LEA (%R8,%R12,8),%R12 |
(234) 0x4345c0 MOV %R12,%R10 |
(234) 0x4345c3 LEA (%R12,%RSI,1),%RSI |
(234) 0x4345c7 AND $0x3,%R15D |
(234) 0x4345cb JE 43492b |
(234) 0x4345d1 CMP $0x1,%R15D |
(234) 0x4345d5 JE 434678 |
(234) 0x4345db CMP $0x2,%R15D |
(234) 0x4345df JE 43462e |
(234) 0x4345e1 VMOVSD (%R12),%XMM3 |
(234) 0x4345e7 VMOVSD (%R12,%R13,8),%XMM2 |
(234) 0x4345ed VMOVSD (%RSI),%XMM1 |
(234) 0x4345f1 MOV 0x40(%RSP),%R12 |
(234) 0x4345f6 VMOVSD (%RSI,%R13,8),%XMM0 |
(234) 0x4345fc MOV 0x38(%RSP),%RDI |
(234) 0x434601 VMOVSD %XMM3,(%RCX) |
(234) 0x434605 MOV 0x48(%RSP),%R15 |
(234) 0x43460a VMOVSD %XMM2,(%RCX,%R11,1) |
(234) 0x434610 VMOVSD %XMM1,(%RCX,%R12,1) |
(234) 0x434616 MOV 0x58(%RSP),%R12 |
(234) 0x43461b VMOVSD %XMM0,(%RCX,%RDI,1) |
(234) 0x434620 MOV $0x1,%EDI |
(234) 0x434625 ADD %R15,%RCX |
(234) 0x434628 ADD %R12,%R10 |
(234) 0x43462b ADD %R12,%RSI |
(234) 0x43462e VMOVSD (%R10),%XMM4 |
(234) 0x434633 VMOVSD (%R10,%R13,8),%XMM5 |
(234) 0x434639 INC %EDI |
(234) 0x43463b VMOVSD (%RSI),%XMM6 |
(234) 0x43463f VMOVSD (%RSI,%R13,8),%XMM7 |
(234) 0x434645 MOV 0x40(%RSP),%R12 |
(234) 0x43464a MOV 0x38(%RSP),%R15 |
(234) 0x43464f VMOVSD %XMM4,(%RCX) |
(234) 0x434653 VMOVSD %XMM5,(%RCX,%R11,1) |
(234) 0x434659 VMOVSD %XMM6,(%RCX,%R12,1) |
(234) 0x43465f MOV 0x58(%RSP),%R12 |
(234) 0x434664 VMOVSD %XMM7,(%RCX,%R15,1) |
(234) 0x43466a MOV 0x48(%RSP),%R15 |
(234) 0x43466f ADD %R12,%R10 |
(234) 0x434672 ADD %R12,%RSI |
(234) 0x434675 ADD %R15,%RCX |
(234) 0x434678 VMOVSD (%R10),%XMM8 |
(234) 0x43467d VMOVSD (%R10,%R13,8),%XMM9 |
(234) 0x434683 INC %EDI |
(234) 0x434685 VMOVSD (%RSI),%XMM10 |
(234) 0x434689 VMOVSD (%RSI,%R13,8),%XMM11 |
(234) 0x43468f MOV 0x40(%RSP),%R12 |
(234) 0x434694 MOV 0x38(%RSP),%R15 |
(234) 0x434699 VMOVSD %XMM8,(%RCX) |
(234) 0x43469d VMOVSD %XMM9,(%RCX,%R11,1) |
(234) 0x4346a3 VMOVSD %XMM10,(%RCX,%R12,1) |
(234) 0x4346a9 MOV 0x58(%RSP),%R12 |
(234) 0x4346ae VMOVSD %XMM11,(%RCX,%R15,1) |
(234) 0x4346b4 MOV 0x48(%RSP),%R15 |
(234) 0x4346b9 ADD %R12,%R10 |
(234) 0x4346bc ADD %R12,%RSI |
(234) 0x4346bf ADD %R15,%RCX |
(234) 0x4346c2 MOV 0x60(%RSP),%R15D |
(234) 0x4346c7 CMP %R15D,%EDI |
(234) 0x4346ca JE 4347de |
(234) 0x4346d0 MOV %R8,0x10(%RSP) |
(234) 0x4346d5 MOV %R12,%R15 |
(234) 0x4346d8 MOV 0x38(%RSP),%R12 |
(234) 0x4346dd MOV %EAX,0x1c(%RSP) |
(234) 0x4346e1 MOV 0x48(%RSP),%RAX |
(234) 0x4346e6 MOV %EDX,0x18(%RSP) |
(234) 0x4346ea MOV 0x40(%RSP),%RDX |
(235) 0x4346ef VMOVSD (%R10),%XMM12 |
(235) 0x4346f4 VMOVSD (%R10,%R13,8),%XMM13 |
(235) 0x4346fa ADD %R15,%R10 |
(235) 0x4346fd ADD $0x4,%EDI |
(235) 0x434700 VMOVSD (%RSI),%XMM14 |
(235) 0x434704 VMOVSD (%RSI,%R13,8),%XMM15 |
(235) 0x43470a ADD %R15,%RSI |
(235) 0x43470d VMOVSD %XMM12,(%RCX) |
(235) 0x434711 VMOVSD %XMM13,(%RCX,%R11,1) |
(235) 0x434717 VMOVSD %XMM14,(%RCX,%RDX,1) |
(235) 0x43471c VMOVSD %XMM15,(%RCX,%R12,1) |
(235) 0x434722 ADD %RAX,%RCX |
(235) 0x434725 VMOVSD (%R10),%XMM3 |
(235) 0x43472a VMOVSD (%R10,%R13,8),%XMM2 |
(235) 0x434730 ADD %R15,%R10 |
(235) 0x434733 VMOVSD (%RSI),%XMM1 |
(235) 0x434737 VMOVSD (%RSI,%R13,8),%XMM0 |
(235) 0x43473d ADD %R15,%RSI |
(235) 0x434740 VMOVSD %XMM3,(%RCX) |
(235) 0x434744 VMOVSD %XMM2,(%RCX,%R11,1) |
(235) 0x43474a VMOVSD %XMM1,(%RCX,%RDX,1) |
(235) 0x43474f VMOVSD %XMM0,(%RCX,%R12,1) |
(235) 0x434755 ADD %RAX,%RCX |
(235) 0x434758 VMOVSD (%R10),%XMM4 |
(235) 0x43475d VMOVSD (%R10,%R13,8),%XMM5 |
(235) 0x434763 ADD %R15,%R10 |
(235) 0x434766 VMOVSD (%RSI),%XMM6 |
(235) 0x43476a VMOVSD (%RSI,%R13,8),%XMM7 |
(235) 0x434770 ADD %R15,%RSI |
(235) 0x434773 VMOVSD %XMM4,(%RCX) |
(235) 0x434777 VMOVSD %XMM5,(%RCX,%R11,1) |
(235) 0x43477d VMOVSD %XMM6,(%RCX,%RDX,1) |
(235) 0x434782 VMOVSD %XMM7,(%RCX,%R12,1) |
(235) 0x434788 ADD %RAX,%RCX |
(235) 0x43478b VMOVSD (%R10),%XMM8 |
(235) 0x434790 VMOVSD (%R10,%R13,8),%XMM9 |
(235) 0x434796 ADD %R15,%R10 |
(235) 0x434799 VMOVSD (%RSI),%XMM10 |
(235) 0x43479d VMOVSD (%RSI,%R13,8),%XMM11 |
(235) 0x4347a3 ADD %R15,%RSI |
(235) 0x4347a6 VMOVSD %XMM8,(%RCX) |
(235) 0x4347aa VMOVSD %XMM9,(%RCX,%R11,1) |
(235) 0x4347b0 VMOVSD %XMM10,(%RCX,%RDX,1) |
(235) 0x4347b5 VMOVSD %XMM11,(%RCX,%R12,1) |
(235) 0x4347bb MOV 0x60(%RSP),%R8D |
(235) 0x4347c0 ADD %RAX,%RCX |
(235) 0x4347c3 CMP %R8D,%EDI |
(235) 0x4347c6 JNE 4346ef |
(234) 0x4347cc MOV 0x1c(%RSP),%EAX |
(234) 0x4347d0 MOV 0x10(%RSP),%R8 |
(234) 0x4347d5 MOV %R15,0x58(%RSP) |
(234) 0x4347da MOV 0x18(%RSP),%EDX |
(234) 0x4347de MOV 0x28(%RSP),%EDI |
(234) 0x4347e2 CMP %EDI,0x68(%RSP) |
(234) 0x4347e6 JE 4348a1 |
(234) 0x4347ec MOV 0xc(%RSP),%ECX |
(234) 0x4347f0 MOV 0x68(%RSP),%R10D |
(234) 0x4347f5 SUB %EDI,%R10D |
(234) 0x4347f8 CMP $0x1,%R10D |
(234) 0x4347fc JE 43486b |
(234) 0x4347fe MOVSXD 0x98(%RSP),%R15 |
(234) 0x434806 MOVSXD %EAX,%RSI |
(234) 0x434809 MOV %R13,%R12 |
(234) 0x43480c IMUL %RDI,%R12 |
(234) 0x434810 IMUL %R11,%RDI |
(234) 0x434814 LEA 0x1(%RSI,%R15,1),%RSI |
(234) 0x434819 MOV 0x90(%RSP),%R15 |
(234) 0x434821 IMUL %R13,%RSI |
(234) 0x434825 ADD %RBX,%RSI |
(234) 0x434828 ADD %R12,%RSI |
(234) 0x43482b LEA (%R8,%RSI,8),%R12 |
(234) 0x43482f MOVSXD %EDX,%RSI |
(234) 0x434832 DEC %RSI |
(234) 0x434835 VMOVSD (%R12),%XMM12 |
(234) 0x43483b IMUL %R15,%RSI |
(234) 0x43483f ADD %R14,%RSI |
(234) 0x434842 LEA (%RDI,%RSI,8),%RSI |
(234) 0x434846 MOV 0x30(%RSP),%RDI |
(234) 0x43484b ADD %R9,%RSI |
(234) 0x43484e VMOVSD (%R12,%RDI,1),%XMM13 |
(234) 0x434854 VMOVSD %XMM12,(%RSI) |
(234) 0x434858 VMOVSD %XMM13,(%RSI,%R11,1) |
(234) 0x43485e TEST $0x1,%R10B |
(234) 0x434862 JE 4348a1 |
(234) 0x434864 AND $-0x2,%R10D |
(234) 0x434868 ADD %R10D,%ECX |
(234) 0x43486b MOV 0x98(%RSP),%R10D |
(234) 0x434873 ADD %ECX,%EAX |
(234) 0x434875 SUB %ECX,%EDX |
(234) 0x434877 MOVSXD %EDX,%RCX |
(234) 0x43487a ADD %R10D,%EAX |
(234) 0x43487d CLTQ |
(234) 0x43487f IMUL %R13,%RAX |
(234) 0x434883 ADD %RBX,%RAX |
(234) 0x434886 VMOVSD (%R8,%RAX,8),%XMM14 |
(234) 0x43488c MOV 0x90(%RSP),%RAX |
(234) 0x434894 IMUL %RAX,%RCX |
(234) 0x434898 ADD %R14,%RCX |
(234) 0x43489b VMOVSD %XMM14,(%R9,%RCX,8) |
(234) 0x4348a1 MOV 0x68(%RSP),%EDX |
(234) 0x4348a5 TEST %EDX,%EDX |
(234) 0x4348a7 JNS 4348ea |
(234) 0x4348a9 INCL 0x9c(%RSP) |
(234) 0x4348b0 MOV 0x88(%RSP),%R15 |
(234) 0x4348b8 ADD %EDX,0x98(%RSP) |
(234) 0x4348bf ADD %R15,%R14 |
(234) 0x4348c2 MOV 0x9c(%RSP),%R12D |
(234) 0x4348ca CMP %R12D,0x84(%RSP) |
(234) 0x4348d2 JG 434558 |
0x4348d8 MOV (%RSP),%RBX |
0x4348dc KMOVB %K0,0x83(%RSP) |
0x4348e5 JMP 4343fb |
(234) 0x4348ea INCL 0x9c(%RSP) |
(234) 0x4348f1 MOV 0x88(%RSP),%RDI |
(234) 0x4348f9 ADD %EDX,0x98(%RSP) |
(234) 0x434900 ADD %RDI,%R14 |
(234) 0x434903 MOV 0x9c(%RSP),%R10D |
(234) 0x43490b CMP %R10D,0x84(%RSP) |
(234) 0x434913 JLE 43495d |
(234) 0x434915 MOV 0x54(%RSP),%ECX |
(234) 0x434919 KMOVB 0x83(%RSP),%K0 |
(234) 0x434922 MOV %ECX,0x50(%RSP) |
(234) 0x434926 JMP 434558 |
(234) 0x43492b MOV 0x58(%RSP),%R15 |
(234) 0x434930 MOV 0x38(%RSP),%R12 |
(234) 0x434935 MOV %EAX,0x1c(%RSP) |
(234) 0x434939 MOV %EDX,0x18(%RSP) |
(234) 0x43493d MOV 0x48(%RSP),%RAX |
(234) 0x434942 MOV %R8,0x10(%RSP) |
(234) 0x434947 MOV 0x40(%RSP),%RDX |
(234) 0x43494c JMP 4346ef |
(234) 0x434951 XOR %EDI,%EDI |
(234) 0x434953 MOV $0x1,%ECX |
(234) 0x434958 JMP 4347f0 |
0x43495d MOV (%RSP),%RBX |
0x434961 JMP 43441c |
0x434966 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | pack_kernel.f90:108-113 |
Module | exec |
nb instructions | 167 |
nb uops | 174 |
loop length | 673 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 23 |
micro-operation queue | 29.00 cycles |
front end | 29.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.20 | 12.20 | 13.33 | 13.33 | 20.00 | 12.20 | 12.20 | 20.00 | 20.00 | 20.00 | 12.20 | 13.33 |
cycles | 12.20 | 14.87 | 13.33 | 13.33 | 20.00 | 12.20 | 12.20 | 20.00 | 20.00 | 20.00 | 12.20 | 13.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 28.27-28.32 |
Stall cycles | 0.00 |
Front-end | 29.00 |
Dispatch | 20.00 |
DIV/SQRT | 6.00 |
Overall L1 | 29.00 |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 9% |
load | 10% |
store | 9% |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xa0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x28(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x54(%RDI),%R12D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x58(%R14),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R15D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 434479 <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x479> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 434405 <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x405> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMPQ $0x1,0x90(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA (%R12,%RSI,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x8(%R14),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %R12B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP $0x1,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %CL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV (%R8),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%R14),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDI,0x9c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
OR %CL,%R12B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x84(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12B,0x83(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 434482 <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x482> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x88(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA -0x1(%R11),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x68(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RSI,%R13,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %R10D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x4,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x2,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x1(%RBX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x5,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %R11D,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15D,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R13D,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %R11D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %R12,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMOVNS %R11D,%R10D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CMPB $0,0x83(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 434426 <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x426> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x54(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x50(%RBX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43406c <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x6c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x88(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x68(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R11),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
KXORB %K0,%K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %R15D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDI,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%R13,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RSI,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x90(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SHR $0x2,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RDI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %R11D,%R15D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%RSI,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x4,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RAX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NEG %RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%RAX,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x4,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x5,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x5,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
AND $-0x4,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R10D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %R11D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %R11D,%R10D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R15,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
KMOVB %K0,0x83(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
JMP 4343fb <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x3fb> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV (%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 43441c <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x41c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | pack_kernel.f90:108-113 |
Module | exec |
nb instructions | 167 |
nb uops | 174 |
loop length | 673 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 23 |
micro-operation queue | 29.00 cycles |
front end | 29.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.20 | 12.20 | 13.33 | 13.33 | 20.00 | 12.20 | 12.20 | 20.00 | 20.00 | 20.00 | 12.20 | 13.33 |
cycles | 12.20 | 14.87 | 13.33 | 13.33 | 20.00 | 12.20 | 12.20 | 20.00 | 20.00 | 20.00 | 12.20 | 13.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 28.27-28.32 |
Stall cycles | 0.00 |
Front-end | 29.00 |
Dispatch | 20.00 |
DIV/SQRT | 6.00 |
Overall L1 | 29.00 |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 9% |
load | 10% |
store | 9% |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xa0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x28(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x54(%RDI),%R12D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x58(%R14),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R15D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 434479 <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x479> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 434405 <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x405> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMPQ $0x1,0x90(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA (%R12,%RSI,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x8(%R14),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %R12B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP $0x1,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %CL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV (%R8),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%R14),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDI,0x9c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
OR %CL,%R12B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x84(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12B,0x83(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 434482 <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x482> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x88(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA -0x1(%R11),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x68(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RSI,%R13,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %R10D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RAX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x4,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x2,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x1(%RBX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x5,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %R11D,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15D,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R13D,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %R11D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %R12,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMOVNS %R11D,%R10D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CMPB $0,0x83(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 434426 <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x426> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x54(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x50(%RBX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43406c <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x6c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x88(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x68(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R11),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
KXORB %K0,%K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %R15D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDI,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%R13,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %RSI,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x90(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SHR $0x2,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RDI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %R11D,%R15D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%RSI,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x4,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RAX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NEG %RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%RAX,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x4,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x5,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x5,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
AND $-0x4,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R10D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %R11D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %R11D,%R10D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R15,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
KMOVB %K0,0x83(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
JMP 4343fb <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x3fb> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV (%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 43441c <__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0+0x41c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼__pack_kernel_module_MOD_clover_unpack_message_left._omp_fn.0.lto_priv.0– | 0.03 | 0.01 |
▼Loop 236 - pack_kernel.f90:108-113 - exec– | 0.03 | 0.02 |
○Loop 237 - pack_kernel.f90:113-113 - exec | 0 | 0 |
▼Loop 234 - pack_kernel.f90:112-113 - exec– | 0 | 0 |
○Loop 235 - pack_kernel.f90:113-113 - exec | 0 | 0 |