Loop Id: 68 | Module: exec | Source: advec_cell_kernel.f90:90-91 | Coverage: 1.52% |
---|
Loop Id: 68 | Module: exec | Source: advec_cell_kernel.f90:90-91 | Coverage: 1.52% |
---|
0x41b69c VMOVUPD (%R12,%RAX,1),%ZMM13 [2] |
0x41b6a3 VMOVUPD (%RCX,%RAX,1),%ZMM1 [3] |
0x41b6aa VADDPD (%RDX,%RAX,1),%ZMM13,%ZMM2 [1] |
0x41b6b1 VADDPD (%R11,%RAX,1),%ZMM1,%ZMM5 [6] |
0x41b6b8 VSUBPD %ZMM5,%ZMM2,%ZMM6 |
0x41b6be VADDPD (%R10,%RAX,1),%ZMM6,%ZMM4 [5] |
0x41b6c5 VMOVUPD %ZMM4,(%R9,%RAX,1) [4] |
0x41b6cc VMOVUPD (%RCX,%RAX,1),%ZMM8 [3] |
0x41b6d3 VSUBPD (%RDX,%RAX,1),%ZMM8,%ZMM9 [1] |
0x41b6da VADDPD %ZMM4,%ZMM9,%ZMM11 |
0x41b6e0 VMOVUPD %ZMM11,(%R8,%RAX,1) [7] |
0x41b6e7 VMOVUPD 0x40(%R12,%RAX,1),%ZMM7 [2] |
0x41b6ef VMOVUPD 0x40(%RCX,%RAX,1),%ZMM15 [3] |
0x41b6f7 VADDPD 0x40(%RAX,%RDX,1),%ZMM7,%ZMM10 [9] |
0x41b6ff VADDPD 0x40(%R11,%RAX,1),%ZMM15,%ZMM12 [6] |
0x41b707 VSUBPD %ZMM12,%ZMM10,%ZMM3 |
0x41b70d VADDPD 0x40(%R10,%RAX,1),%ZMM3,%ZMM14 [5] |
0x41b715 VMOVUPD %ZMM14,0x40(%R9,%RAX,1) [4] |
0x41b71d VMOVUPD 0x40(%RCX,%RAX,1),%ZMM0 [3] |
0x41b725 VSUBPD 0x40(%RAX,%RDX,1),%ZMM0,%ZMM13 [9] |
0x41b72d VADDPD %ZMM14,%ZMM13,%ZMM2 |
0x41b733 VMOVUPD %ZMM2,0x40(%R8,%RAX,1) [7] |
0x41b73b VMOVUPD 0x80(%R12,%RAX,1),%ZMM1 [2] |
0x41b743 VMOVUPD 0x80(%RCX,%RAX,1),%ZMM6 [3] |
0x41b74b VADDPD 0x80(%RAX,%RDX,1),%ZMM1,%ZMM5 [9] |
0x41b753 VADDPD 0x80(%R11,%RAX,1),%ZMM6,%ZMM4 [6] |
0x41b75b VSUBPD %ZMM4,%ZMM5,%ZMM8 |
0x41b761 VADDPD 0x80(%R10,%RAX,1),%ZMM8,%ZMM9 [5] |
0x41b769 VMOVUPD %ZMM9,0x80(%R9,%RAX,1) [4] |
0x41b771 VMOVUPD 0x80(%RCX,%RAX,1),%ZMM11 [3] |
0x41b779 VSUBPD 0x80(%RAX,%RDX,1),%ZMM11,%ZMM7 [9] |
0x41b781 VADDPD %ZMM9,%ZMM7,%ZMM10 |
0x41b787 VMOVUPD %ZMM10,0x80(%R8,%RAX,1) [7] |
0x41b78f VMOVUPD 0xc0(%R12,%RAX,1),%ZMM15 [2] |
0x41b797 VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM3 [3] |
0x41b79f VADDPD 0xc0(%RAX,%RDX,1),%ZMM15,%ZMM12 [9] |
0x41b7a7 VADDPD 0xc0(%R11,%RAX,1),%ZMM3,%ZMM14 [6] |
0x41b7af VSUBPD %ZMM14,%ZMM12,%ZMM0 |
0x41b7b5 VADDPD 0xc0(%R10,%RAX,1),%ZMM0,%ZMM13 [5] |
0x41b7bd VMOVUPD %ZMM13,0xc0(%R9,%RAX,1) [4] |
0x41b7c5 VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM2 [3] |
0x41b7cd VSUBPD 0xc0(%RAX,%RDX,1),%ZMM2,%ZMM1 [9] |
0x41b7d5 VADDPD %ZMM13,%ZMM1,%ZMM5 |
0x41b7db VMOVUPD %ZMM5,0xc0(%R8,%RAX,1) [7] |
0x41b7e3 ADD $0x100,%RAX |
0x41b7e9 CMP %RAX,0xd0(%RSP) [8] |
0x41b7f1 JNE 41b69c |
/scratch_na/users/xoserete/qaas_runs/171-415-7919/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 90 - 91 |
-------------------------------------------------------------------------------- |
90: pre_vol(j,k)=volume(j,k)+(vol_flux_x(j+1,k )-vol_flux_x(j,k)+vol_flux_y(j ,k+1)-vol_flux_y(j,k)) |
91: post_vol(j,k)=pre_vol(j,k)-(vol_flux_x(j+1,k )-vol_flux_x(j,k)) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.16 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.84 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.16 |
Bottlenecks | P0, P1, P5, |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source | advec_cell_kernel.f90:90-91 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.00 |
CQA cycles if no scalar integer | 12.00 |
CQA cycles if FP arith vectorized | 12.00 |
CQA cycles if fully vectorized | 12.00 |
Front-end cycles | 10.33 |
DIV/SQRT cycles | 12.00 |
P0 cycles | 12.00 |
P1 cycles | 9.67 |
P2 cycles | 9.67 |
P3 cycles | 4.00 |
P4 cycles | 12.00 |
P5 cycles | 1.00 |
P6 cycles | 4.00 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 0.40 |
P10 cycles | 9.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 12.25 |
Stall cycles (UFS) | 1.25 |
Nb insns | 47.00 |
Nb uops | 46.00 |
Nb loads | 29.00 |
Nb stores | 8.00 |
Nb stack references | 1.00 |
FLOP/cycle | 16.00 |
Nb FLOP add-sub | 192.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 192.67 |
Bytes prefetched | 0.00 |
Bytes loaded | 1800.00 |
Bytes stored | 512.00 |
Stride 0 | 1.00 |
Stride 1 | 5.00 |
Stride n | 3.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.16 |
Bottlenecks | P0, P1, P5, |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source | advec_cell_kernel.f90:90-91 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.00 |
CQA cycles if no scalar integer | 12.00 |
CQA cycles if FP arith vectorized | 12.00 |
CQA cycles if fully vectorized | 12.00 |
Front-end cycles | 10.33 |
DIV/SQRT cycles | 12.00 |
P0 cycles | 12.00 |
P1 cycles | 9.67 |
P2 cycles | 9.67 |
P3 cycles | 4.00 |
P4 cycles | 12.00 |
P5 cycles | 1.00 |
P6 cycles | 4.00 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 0.40 |
P10 cycles | 9.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 12.25 |
Stall cycles (UFS) | 1.25 |
Nb insns | 47.00 |
Nb uops | 46.00 |
Nb loads | 29.00 |
Nb stores | 8.00 |
Nb stack references | 1.00 |
FLOP/cycle | 16.00 |
Nb FLOP add-sub | 192.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 192.67 |
Bytes prefetched | 0.00 |
Bytes loaded | 1800.00 |
Bytes stored | 512.00 |
Stride 0 | 1.00 |
Stride 1 | 5.00 |
Stride n | 3.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source file and lines | advec_cell_kernel.f90:90-91 |
Module | exec |
nb instructions | 47 |
nb uops | 46 |
loop length | 347 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 1 |
micro-operation queue | 10.33 cycles |
front end | 10.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.00 | 0.60 | 9.67 | 9.67 | 4.00 | 12.00 | 1.00 | 4.00 | 4.00 | 4.00 | 0.40 | 9.67 |
cycles | 12.00 | 12.00 | 9.67 | 9.67 | 4.00 | 12.00 | 1.00 | 4.00 | 4.00 | 4.00 | 0.40 | 9.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 12.25 |
Stall cycles | 1.25 |
LB full (events) | 2.24 |
Front-end | 10.33 |
Dispatch | 12.00 |
Data deps. | 1.00 |
Overall L1 | 12.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R12,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD (%RCX,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VADDPD (%RDX,%RAX,1),%ZMM13,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD (%R11,%RAX,1),%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD %ZMM5,%ZMM2,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD (%R10,%RAX,1),%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM4,(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD (%RCX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VSUBPD (%RDX,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD %ZMM4,%ZMM9,%ZMM11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD %ZMM11,(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%R12,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x40(%RCX,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VADDPD 0x40(%RAX,%RDX,1),%ZMM7,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD 0x40(%R11,%RAX,1),%ZMM15,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD %ZMM12,%ZMM10,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD 0x40(%R10,%RAX,1),%ZMM3,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM14,0x40(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%RCX,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VSUBPD 0x40(%RAX,%RDX,1),%ZMM0,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD %ZMM14,%ZMM13,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD %ZMM2,0x40(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%R12,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x80(%RCX,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VADDPD 0x80(%RAX,%RDX,1),%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD 0x80(%R11,%RAX,1),%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD %ZMM4,%ZMM5,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD 0x80(%R10,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM9,0x80(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%RCX,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VSUBPD 0x80(%RAX,%RDX,1),%ZMM11,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD %ZMM9,%ZMM7,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD %ZMM10,0x80(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%R12,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VADDPD 0xc0(%RAX,%RDX,1),%ZMM15,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD 0xc0(%R11,%RAX,1),%ZMM3,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD %ZMM14,%ZMM12,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD 0xc0(%R10,%RAX,1),%ZMM0,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM13,0xc0(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VSUBPD 0xc0(%RAX,%RDX,1),%ZMM2,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD %ZMM13,%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD %ZMM5,0xc0(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x100,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RAX,0xd0(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 41b69c <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x31ec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source file and lines | advec_cell_kernel.f90:90-91 |
Module | exec |
nb instructions | 47 |
nb uops | 46 |
loop length | 347 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 1 |
micro-operation queue | 10.33 cycles |
front end | 10.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.00 | 0.60 | 9.67 | 9.67 | 4.00 | 12.00 | 1.00 | 4.00 | 4.00 | 4.00 | 0.40 | 9.67 |
cycles | 12.00 | 12.00 | 9.67 | 9.67 | 4.00 | 12.00 | 1.00 | 4.00 | 4.00 | 4.00 | 0.40 | 9.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 12.25 |
Stall cycles | 1.25 |
LB full (events) | 2.24 |
Front-end | 10.33 |
Dispatch | 12.00 |
Data deps. | 1.00 |
Overall L1 | 12.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R12,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD (%RCX,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VADDPD (%RDX,%RAX,1),%ZMM13,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD (%R11,%RAX,1),%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD %ZMM5,%ZMM2,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD (%R10,%RAX,1),%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM4,(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD (%RCX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VSUBPD (%RDX,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD %ZMM4,%ZMM9,%ZMM11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD %ZMM11,(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%R12,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x40(%RCX,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VADDPD 0x40(%RAX,%RDX,1),%ZMM7,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD 0x40(%R11,%RAX,1),%ZMM15,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD %ZMM12,%ZMM10,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD 0x40(%R10,%RAX,1),%ZMM3,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM14,0x40(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%RCX,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VSUBPD 0x40(%RAX,%RDX,1),%ZMM0,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD %ZMM14,%ZMM13,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD %ZMM2,0x40(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%R12,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x80(%RCX,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VADDPD 0x80(%RAX,%RDX,1),%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD 0x80(%R11,%RAX,1),%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD %ZMM4,%ZMM5,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD 0x80(%R10,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM9,0x80(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%RCX,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VSUBPD 0x80(%RAX,%RDX,1),%ZMM11,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD %ZMM9,%ZMM7,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD %ZMM10,0x80(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%R12,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VADDPD 0xc0(%RAX,%RDX,1),%ZMM15,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD 0xc0(%R11,%RAX,1),%ZMM3,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VSUBPD %ZMM14,%ZMM12,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD 0xc0(%R10,%RAX,1),%ZMM0,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VMOVUPD %ZMM13,0xc0(%R9,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VSUBPD 0xc0(%RAX,%RDX,1),%ZMM2,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VADDPD %ZMM13,%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD %ZMM5,0xc0(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x100,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RAX,0xd0(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 41b69c <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x31ec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |