Loop Id: 181 | Module: exec | Source: advec_mom_kernel.f90:81-241 [...] | Coverage: 4.86% |
---|
Loop Id: 181 | Module: exec | Source: advec_mom_kernel.f90:81-241 [...] | Coverage: 4.86% |
---|
0x434980 VCMPPD $0x1,%ZMM31,%ZMM16,%K2 |
0x434987 VCMPPD $0x1,%ZMM30,%ZMM16,%K3 |
0x43498e VPBLENDMD %ZMM22,%ZMM21,%ZMM5{%K1} |
0x434994 MOV 0x90(%RSP),%RAX [1] |
0x43499c VMOVSD (%RAX,%R10,8),%XMM8 [8] |
0x4349a2 VANDPD %ZMM11,%ZMM4,%ZMM4 |
0x4349a8 VANDPD %ZMM11,%ZMM14,%ZMM13 |
0x4349ae VANDPD %ZMM11,%ZMM9,%ZMM14 |
0x4349b4 VANDPD %ZMM11,%ZMM7,%ZMM18 |
0x4349ba VBROADCASTSD 0xd1d54(%RIP),%ZMM0 [12] |
0x4349c4 VSUBPD %ZMM28,%ZMM0,%ZMM19 |
0x4349ca VSUBPD %ZMM29,%ZMM0,%ZMM10 |
0x4349d0 VMULPD %ZMM10,%ZMM18,%ZMM10 |
0x4349d6 VMULPD %ZMM19,%ZMM14,%ZMM19 |
0x4349dc VMOVSD 0xcfbfc(%RIP),%XMM0 [12] |
0x4349e4 VDIVSD %XMM8,%XMM0,%XMM0 |
0x4349e9 VBROADCASTSD %XMM0,%ZMM0 |
0x4349ef VMINPD %ZMM14,%ZMM13,%ZMM17 |
0x4349f5 VFMADD213PD %ZMM13,%ZMM28,%ZMM13 |
0x4349fb VMINPD %ZMM18,%ZMM4,%ZMM14 |
0x434a01 VFMADD213PD %ZMM4,%ZMM29,%ZMM4 |
0x434a07 VEXTRACTI64X4 $0x1,%ZMM5,%YMM18 |
0x434a0e VPMOVSXDQ %YMM5,%ZMM5 |
0x434a14 VPMOVSXDQ %YMM18,%ZMM18 |
0x434a1a VPSUBQ %ZMM1,%ZMM18,%ZMM18 |
0x434a20 VPSUBQ %ZMM1,%ZMM5,%ZMM5 |
0x434a26 VXORPD %XMM6,%XMM6,%XMM6 |
0x434a2a VGATHERQPD (%RAX,%ZMM5,8),%ZMM6{%K3} [13] |
0x434a31 VXORPD %XMM5,%XMM5,%XMM5 |
0x434a35 VGATHERQPD (%RAX,%ZMM18,8),%ZMM5{%K2} [3] |
0x434a3c VDIVPD %ZMM6,%ZMM13,%ZMM6 |
0x434a42 VDIVPD %ZMM5,%ZMM4,%ZMM4 |
0x434a48 VFMADD231PD %ZMM19,%ZMM0,%ZMM6 |
0x434a4e VFMADD231PD %ZMM10,%ZMM0,%ZMM4 |
0x434a54 VMULSD 0xd1ccc(%RIP),%XMM8,%XMM0 [12] |
0x434a5c VBROADCASTSD %XMM0,%ZMM0 |
0x434a62 VMULPD %ZMM4,%ZMM0,%ZMM4 |
0x434a68 VMULPD %ZMM6,%ZMM0,%ZMM0 |
0x434a6e VMINPD %ZMM14,%ZMM4,%ZMM14 |
0x434a74 VMINPD %ZMM17,%ZMM0,%ZMM13 |
0x434a7a VFPCLASSPD $0x56,%ZMM9,%K1 |
0x434a81 VFPCLASSPD $0x56,%ZMM7,%K2 |
0x434a88 VBROADCASTSD 0xd1c8e(%RIP),%ZMM0 [12] |
0x434a92 VXORPD %ZMM0,%ZMM14,%ZMM14{%K2} |
0x434a98 VXORPD %ZMM0,%ZMM13,%ZMM13{%K1} |
0x434a9e VCMPPD $0x1,%ZMM30,%ZMM16,%K1 |
0x434aa5 VCMPPD $0x1,%ZMM31,%ZMM16,%K2 |
0x434aac VMOVAPD %ZMM14,%ZMM0{%K2}{z} |
0x434ab2 VMOVAPD %ZMM13,%ZMM4{%K1}{z} |
0x434ab8 VBROADCASTSD 0xcfb1e(%RIP),%ZMM6 [12] |
0x434ac2 VSUBPD %ZMM29,%ZMM6,%ZMM5 |
0x434ac8 VSUBPD %ZMM28,%ZMM6,%ZMM6 |
0x434ace VFMADD213PD %ZMM26,%ZMM4,%ZMM6 |
0x434ad4 VFMADD213PD %ZMM27,%ZMM0,%ZMM5 |
0x434ada VMULPD %ZMM25,%ZMM5,%ZMM0 |
0x434ae0 VMULPD %ZMM24,%ZMM6,%ZMM4 |
0x434ae6 VMOVUPD %ZMM4,(%R9,%RBX,8) [4] |
0x434aed VMOVUPD %ZMM0,0x40(%R9,%RBX,8) [4] |
0x434af5 ADD $0x10,%RBX |
0x434af9 CMP %RCX,%RBX |
0x434afc JG 434d80 |
0x434b02 LEA (%RDI,%RBX,1),%RAX |
0x434b06 VMOVUPD (%RSI,%RBX,8),%ZMM24 [5] |
0x434b0d VMOVUPD 0x40(%RSI,%RBX,8),%ZMM25 [5] |
0x434b15 VFPCLASSPD $0x50,%ZMM24,%K0 |
0x434b1c VFPCLASSPD $0x50,%ZMM25,%K1 |
0x434b23 KUNPCKBW %K0,%K1,%K1 |
0x434b27 VPBLENDMD %ZMM22,%ZMM23,%ZMM4{%K1} |
0x434b2d VEXTRACTI64X4 $0x1,%ZMM4,%YMM7 |
0x434b34 VPMOVSXDQ %YMM7,%ZMM7 |
0x434b3a VPSUBQ %ZMM1,%ZMM7,%ZMM9 |
0x434b40 VPXOR %XMM7,%XMM7,%XMM7 |
0x434b44 VPMULLQ %ZMM9,%ZMM2,%ZMM7 |
0x434b4a VPMOVSXDQ %YMM4,%ZMM4 |
0x434b50 VPSUBQ %ZMM1,%ZMM4,%ZMM4 |
0x434b56 VPXOR %XMM13,%XMM13,%XMM13 |
0x434b5b VPMULLQ %ZMM4,%ZMM2,%ZMM13 |
0x434b61 VPBROADCASTQ %RAX,%ZMM14 |
0x434b67 VPSUBQ 0x2c0(%RSP),%ZMM14,%ZMM14 [1] |
0x434b6f VPSLLQ $0x3,%ZMM14,%ZMM14 |
0x434b76 VPADDQ 0xd2580(%RIP),%ZMM14,%ZMM26 [12] |
0x434b80 VPADDQ %ZMM26,%ZMM12,%ZMM27 |
0x434b86 VPADDQ %ZMM13,%ZMM27,%ZMM13 |
0x434b8c VXORPD %XMM28,%XMM28,%XMM28 |
0x434b92 KXNORW %K0,%K0,%K2 |
0x434b96 VGATHERQPD (,%ZMM13,1),%ZMM28{%K2} [2] |
0x434ba1 VPADDQ 0xd2515(%RIP),%ZMM14,%ZMM13 [12] |
0x434bab VPADDQ %ZMM13,%ZMM12,%ZMM14 |
0x434bb1 VPADDQ %ZMM7,%ZMM14,%ZMM14 |
0x434bb7 VPXOR %XMM7,%XMM7,%XMM7 |
0x434bbb KXNORW %K0,%K0,%K2 |
0x434bbf VGATHERQPD (,%ZMM14,1),%ZMM7{%K2} [7] |
0x434bca VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
0x434bd0 VPADDQ %ZMM26,%ZMM15,%ZMM14 |
0x434bd6 VPADDQ %ZMM4,%ZMM14,%ZMM4 |
0x434bdc VPXORD %XMM26,%XMM26,%XMM26 |
0x434be2 KXNORW %K0,%K0,%K2 |
0x434be6 VGATHERQPD (,%ZMM4,1),%ZMM26{%K2} [9] |
0x434bf1 VPXOR %XMM4,%XMM4,%XMM4 |
0x434bf5 VPMULLQ %ZMM9,%ZMM3,%ZMM4 |
0x434bfb VPADDQ %ZMM13,%ZMM15,%ZMM9 |
0x434c01 VPADDQ %ZMM4,%ZMM9,%ZMM4 |
0x434c07 VPXORD %XMM27,%XMM27,%XMM27 |
0x434c0d KXNORW %K0,%K0,%K2 |
0x434c11 VGATHERQPD (,%ZMM4,1),%ZMM27{%K2} [15] |
0x434c1c VPBLENDMD %ZMM20,%ZMM21,%ZMM4{%K1} |
0x434c22 VEXTRACTI64X4 $0x1,%ZMM4,%YMM13 |
0x434c29 VPMOVSXDQ %YMM13,%ZMM13 |
0x434c2f VPMOVSXDQ %YMM4,%ZMM4 |
0x434c35 VPSUBQ %ZMM1,%ZMM4,%ZMM4 |
0x434c3b VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
0x434c41 VPADDQ %ZMM4,%ZMM14,%ZMM4 |
0x434c47 VXORPD %XMM30,%XMM30,%XMM30 |
0x434c4d KXNORW %K0,%K0,%K2 |
0x434c51 VGATHERQPD (,%ZMM4,1),%ZMM30{%K2} [14] |
0x434c5c VPSUBQ %ZMM1,%ZMM13,%ZMM4 |
0x434c62 VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
0x434c68 VPADDQ %ZMM4,%ZMM9,%ZMM4 |
0x434c6e VXORPD %XMM31,%XMM31,%XMM31 |
0x434c74 KXNORW %K0,%K0,%K2 |
0x434c78 VGATHERQPD (,%ZMM4,1),%ZMM31{%K2} [10] |
0x434c83 VPBLENDMD %ZMM23,%ZMM22,%ZMM4{%K1} |
0x434c89 VANDPD %ZMM11,%ZMM24,%ZMM29 |
0x434c8f VANDPD %ZMM11,%ZMM25,%ZMM5 |
0x434c95 VPXOR %XMM13,%XMM13,%XMM13 |
0x434c9a VDIVPD %ZMM28,%ZMM29,%ZMM28 |
0x434ca0 VEXTRACTI64X4 $0x1,%ZMM4,%YMM29 |
0x434ca7 VPMOVSXDQ %YMM29,%ZMM29 |
0x434cad VPMOVSXDQ %YMM4,%ZMM4 |
0x434cb3 VPSUBQ %ZMM1,%ZMM4,%ZMM4 |
0x434cb9 VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
0x434cbf VPADDQ %ZMM4,%ZMM14,%ZMM4 |
0x434cc5 VXORPD %XMM8,%XMM8,%XMM8 |
0x434cca KXNORW %K0,%K0,%K2 |
0x434cce VGATHERQPD (,%ZMM4,1),%ZMM8{%K2} [11] |
0x434cd9 VPSUBQ %ZMM1,%ZMM29,%ZMM4 |
0x434cdf VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
0x434ce5 VPADDQ %ZMM4,%ZMM9,%ZMM4 |
0x434ceb VPXOR %XMM9,%XMM9,%XMM9 |
0x434cf0 KXNORW %K0,%K0,%K2 |
0x434cf4 VGATHERQPD (,%ZMM4,1),%ZMM9{%K2} [6] |
0x434cff VDIVPD %ZMM7,%ZMM5,%ZMM29 |
0x434d05 VSUBPD %ZMM31,%ZMM27,%ZMM4 |
0x434d0b VSUBPD %ZMM30,%ZMM26,%ZMM14 |
0x434d11 VSUBPD %ZMM27,%ZMM9,%ZMM7 |
0x434d17 VSUBPD %ZMM26,%ZMM8,%ZMM9 |
0x434d1d VMULPD %ZMM14,%ZMM9,%ZMM30 |
0x434d23 VMULPD %ZMM4,%ZMM7,%ZMM31 |
0x434d29 VCMPPD $0x1,%ZMM31,%ZMM13,%K0 |
0x434d30 VCMPPD $0x1,%ZMM30,%ZMM13,%K2 |
0x434d37 KORTESTB %K0,%K2 |
0x434d3b JNE 434980 |
0x434d41 VXORPD %XMM14,%XMM14,%XMM14 |
0x434d46 JMP 434a9e |
/scratch_na/users/xoserete/qaas_runs/171-415-7919/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 81 - 241 |
-------------------------------------------------------------------------------- |
81: IF(mom_sweep.EQ.1)THEN ! x 1 |
[...] |
215: IF(node_flux(j,k).LT.0.0)THEN |
[...] |
227: sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor)) |
228: width=celldy(k) |
229: vdiffuw=vel1(j,donor)-vel1(j,upwind) |
230: vdiffdw=vel1(j,downwind)-vel1(j,donor) |
231: limiter=0.0 |
232: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
233: auw=ABS(vdiffuw) |
234: adw=ABS(vdiffdw) |
235: wind=1.0_8 |
236: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
237: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw) |
238: ENDIF |
239: advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter |
240: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
241: ENDDO |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.08 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.03 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | NA |
Bottlenecks | |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241 |
Source loop unroll info | unrolled by 16 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | main |
Unroll factor | 16 |
CQA cycles | 70.75 |
CQA cycles if no scalar integer | 65.75 |
CQA cycles if FP arith vectorized | 70.56 |
CQA cycles if fully vectorized | 68.94 |
Front-end cycles | 34.08 |
DIV/SQRT cycles | 70.75 |
P0 cycles | 8.75 |
P1 cycles | 27.00 |
P2 cycles | 27.00 |
P3 cycles | 1.00 |
P4 cycles | 70.75 |
P5 cycles | 2.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.00 |
P10 cycles | 27.00 |
P11 cycles | 50.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 72.53 - 128.00 |
Stall cycles (UFS) | 43.57 - 98.90 |
Nb insns | 130.50 |
Nb uops | 204.50 |
Nb loads | 18.00 |
Nb stores | 2.00 |
Nb stack references | 1.50 |
FLOP/cycle | 2.73 |
Nb FLOP add-sub | 56.00 |
Nb FLOP mul | 48.50 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 24.50 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 15.11 |
Bytes prefetched | 0.00 |
Bytes loaded | 928.00 |
Bytes stored | 128.00 |
Stride 0 | 2.00 |
Stride 1 | 2.00 |
Stride n | 1.50 |
Stride unknown | 0.00 |
Stride indirect | 3.00 |
Vectorization ratio all | 95.25 |
Vectorization ratio load | 82.14 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 97.06 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 90.00 |
Vectorization ratio other | 93.60 |
Vector-efficiency ratio all | 82.11 |
Vector-efficiency ratio load | 84.38 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 97.43 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 91.25 |
Vector-efficiency ratio other | 67.29 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.09 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.02 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | NA |
Bottlenecks | P0, P5, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241 |
Source loop unroll info | unrolled by 16 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | main |
Unroll factor | 16 |
CQA cycles | 59.50 |
CQA cycles if no scalar integer | 54.50 |
CQA cycles if FP arith vectorized | 59.50 |
CQA cycles if fully vectorized | 58.50 |
Front-end cycles | 29.50 |
DIV/SQRT cycles | 59.50 |
P0 cycles | 6.00 |
P1 cycles | 23.33 |
P2 cycles | 23.33 |
P3 cycles | 1.00 |
P4 cycles | 59.50 |
P5 cycles | 2.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.00 |
P10 cycles | 23.33 |
P11 cycles | 32.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 61.21 - 119.71 |
Stall cycles (UFS) | 36.50 - 94.83 |
Nb insns | 109.00 |
Nb uops | 177.00 |
Nb loads | 14.00 |
Nb stores | 2.00 |
Nb stack references | 1.00 |
FLOP/cycle | 2.15 |
Nb FLOP add-sub | 48.00 |
Nb FLOP mul | 32.00 |
Nb FLOP fma | 16.00 |
Nb FLOP div | 16.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 16.27 |
Bytes prefetched | 0.00 |
Bytes loaded | 840.00 |
Bytes stored | 128.00 |
Stride 0 | 2.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 3.00 |
Vectorization ratio all | 97.85 |
Vectorization ratio load | 92.86 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 95.65 |
Vector-efficiency ratio all | 82.80 |
Vector-efficiency ratio load | 93.75 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 65.22 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.06 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.03 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | NA |
Bottlenecks | P0, P5, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241 |
Source loop unroll info | unrolled by 16 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | main |
Unroll factor | 16 |
CQA cycles | 82.00 |
CQA cycles if no scalar integer | 77.00 |
CQA cycles if FP arith vectorized | 81.63 |
CQA cycles if fully vectorized | 79.38 |
Front-end cycles | 38.67 |
DIV/SQRT cycles | 82.00 |
P0 cycles | 11.50 |
P1 cycles | 30.67 |
P2 cycles | 30.67 |
P3 cycles | 1.00 |
P4 cycles | 82.00 |
P5 cycles | 2.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.00 |
P10 cycles | 30.67 |
P11 cycles | 68.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 83.84 - 136.29 |
Stall cycles (UFS) | 50.63 - 102.97 |
Nb insns | 152.00 |
Nb uops | 232.00 |
Nb loads | 22.00 |
Nb stores | 2.00 |
Nb stack references | 2.00 |
FLOP/cycle | 3.15 |
Nb FLOP add-sub | 64.00 |
Nb FLOP mul | 65.00 |
Nb FLOP fma | 48.00 |
Nb FLOP div | 33.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 13.95 |
Bytes prefetched | 0.00 |
Bytes loaded | 1016.00 |
Bytes stored | 128.00 |
Stride 0 | 2.00 |
Stride 1 | 2.00 |
Stride n | 3.00 |
Stride unknown | 0.00 |
Stride indirect | 3.00 |
Vectorization ratio all | 92.65 |
Vectorization ratio load | 71.43 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 94.12 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 80.00 |
Vectorization ratio other | 91.55 |
Vector-efficiency ratio all | 81.43 |
Vector-efficiency ratio load | 75.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 94.85 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 82.50 |
Vector-efficiency ratio other | 69.37 |
Path / |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-241 |
Module | exec |
nb instructions | 130.50 |
nb uops | 204.50 |
loop length | 823 |
used x86 registers | 7.50 |
used mmx registers | 0 |
used xmm registers | 12 |
used ymm registers | 5 |
used zmm registers | 30 |
nb stack references | 1.50 |
ADD-SUB / MUL ratio | 1.19 |
micro-operation queue | 34.08 cycles |
front end | 34.08 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 70.75 | 2.50 | 27.00 | 27.00 | 1.00 | 70.75 | 2.00 | 1.00 | 1.00 | 1.00 | 1.00 | 27.00 |
cycles | 70.75 | 8.75 | 27.00 | 27.00 | 1.00 | 70.75 | 2.00 | 1.00 | 1.00 | 1.00 | 1.00 | 27.00 |
Cycles executing div or sqrt instructions | 50.00 |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 72.53-128.00 |
Stall cycles | 43.57-98.90 |
RS full (events) | 71.18-0.66 |
Front-end | 34.08 |
Dispatch | 70.75 |
DIV/SQRT | 50.00 |
Data deps. | 0.00 |
Overall L1 | 70.75 |
all | 98% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 95% |
all | 93% |
load | 78% |
store | 100% |
mul | 94% |
add-sub | 100% |
fma | 100% |
div/sqrt | 90% |
other | 92% |
all | 95% |
load | 82% |
store | 100% |
mul | 97% |
add-sub | 100% |
fma | 100% |
div/sqrt | 90% |
other | 93% |
all | 77% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 49% |
all | 86% |
load | 81% |
store | 100% |
mul | 95% |
add-sub | 100% |
fma | 100% |
div/sqrt | 91% |
other | 80% |
all | 82% |
load | 84% |
store | 100% |
mul | 97% |
add-sub | 100% |
fma | 100% |
div/sqrt | 91% |
other | 67% |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-241 |
Module | exec |
nb instructions | 109 |
nb uops | 177 |
loop length | 685 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 11 |
used ymm registers | 4 |
used zmm registers | 28 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 1.50 |
micro-operation queue | 29.50 cycles |
front end | 29.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 59.50 | 2.00 | 23.33 | 23.33 | 1.00 | 59.50 | 2.00 | 1.00 | 1.00 | 1.00 | 1.00 | 23.33 |
cycles | 59.50 | 6.00 | 23.33 | 23.33 | 1.00 | 59.50 | 2.00 | 1.00 | 1.00 | 1.00 | 1.00 | 23.33 |
Cycles executing div or sqrt instructions | 32.00 |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 61.21-119.71 |
Stall cycles | 36.50-94.83 |
RS full (events) | 59.97-0.64 |
Front-end | 29.50 |
Dispatch | 59.50 |
DIV/SQRT | 32.00 |
Data deps. | 0.00 |
Overall L1 | 59.50 |
all | 98% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 95% |
all | 97% |
load | 90% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 95% |
all | 97% |
load | 92% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 95% |
all | 77% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 48% |
all | 88% |
load | 92% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 80% |
all | 82% |
load | 93% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 65% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VCMPPD $0x1,%ZMM30,%ZMM16,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPD $0x1,%ZMM31,%ZMM16,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM14,%ZMM0{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %ZMM13,%ZMM4{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VBROADCASTSD 0xcfb1e(%RIP),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VSUBPD %ZMM29,%ZMM6,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPD %ZMM28,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213PD %ZMM26,%ZMM4,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD %ZMM27,%ZMM0,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM25,%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM24,%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM4,(%R9,%RBX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD %ZMM0,0x40(%R9,%RBX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x10,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JG 434d80 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x30a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RDI,%RBX,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVUPD (%RSI,%RBX,8),%ZMM24 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x40(%RSI,%RBX,8),%ZMM25 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFPCLASSPD $0x50,%ZMM24,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFPCLASSPD $0x50,%ZMM25,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KUNPCKBW %K0,%K1,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VPBLENDMD %ZMM22,%ZMM23,%ZMM4{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VEXTRACTI64X4 $0x1,%ZMM4,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM7,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM1,%ZMM7,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPXOR %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM9,%ZMM2,%ZMM7 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPMOVSXDQ %YMM4,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM1,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPXOR %XMM13,%XMM13,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM4,%ZMM2,%ZMM13 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPBROADCASTQ %RAX,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ 0x2c0(%RSP),%ZMM14,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.67 |
VPSLLQ $0x3,%ZMM14,%ZMM14 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 1 |
VPADDQ 0xd2580(%RIP),%ZMM14,%ZMM26 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VPADDQ %ZMM26,%ZMM12,%ZMM27 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM13,%ZMM27,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM28,%XMM28,%XMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM13,1),%ZMM28{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPADDQ 0xd2515(%RIP),%ZMM14,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VPADDQ %ZMM13,%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM7,%ZMM14,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPXOR %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM14,1),%ZMM7{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPMULLQ %ZMM4,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM26,%ZMM15,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM4,%ZMM14,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPXORD %XMM26,%XMM26,%XMM26 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM26{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPXOR %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM9,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM13,%ZMM15,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM4,%ZMM9,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPXORD %XMM27,%XMM27,%XMM27 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM27{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPBLENDMD %ZMM20,%ZMM21,%ZMM4{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VEXTRACTI64X4 $0x1,%ZMM4,%YMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM13,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM4,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM1,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPMULLQ %ZMM4,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM4,%ZMM14,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM30,%XMM30,%XMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM30{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPSUBQ %ZMM1,%ZMM13,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPMULLQ %ZMM4,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM4,%ZMM9,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM31,%XMM31,%XMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM31{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPBLENDMD %ZMM23,%ZMM22,%ZMM4{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VANDPD %ZMM11,%ZMM24,%ZMM29 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VANDPD %ZMM11,%ZMM25,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPXOR %XMM13,%XMM13,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VDIVPD %ZMM28,%ZMM29,%ZMM28 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VEXTRACTI64X4 $0x1,%ZMM4,%YMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM29,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM4,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM1,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPMULLQ %ZMM4,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM4,%ZMM14,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM8{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPSUBQ %ZMM1,%ZMM29,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPMULLQ %ZMM4,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM4,%ZMM9,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPXOR %XMM9,%XMM9,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM9{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VDIVPD %ZMM7,%ZMM5,%ZMM29 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VSUBPD %ZMM31,%ZMM27,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPD %ZMM30,%ZMM26,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPD %ZMM27,%ZMM9,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPD %ZMM26,%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %ZMM14,%ZMM9,%ZMM30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM4,%ZMM7,%ZMM31 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%ZMM31,%ZMM13,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPD $0x1,%ZMM30,%ZMM13,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KORTESTB %K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JNE 434980 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2ca0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM14,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 434a9e <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2dbe> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-241 |
Module | exec |
nb instructions | 152 |
nb uops | 232 |
loop length | 961 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 13 |
used ymm registers | 6 |
used zmm registers | 32 |
nb stack references | 2 |
ADD-SUB / MUL ratio | 0.89 |
micro-operation queue | 38.67 cycles |
front end | 38.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 82.00 | 3.00 | 30.67 | 30.67 | 1.00 | 82.00 | 2.00 | 1.00 | 1.00 | 1.00 | 1.00 | 30.67 |
cycles | 82.00 | 11.50 | 30.67 | 30.67 | 1.00 | 82.00 | 2.00 | 1.00 | 1.00 | 1.00 | 1.00 | 30.67 |
Cycles executing div or sqrt instructions | 68.00 |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 83.84-136.29 |
Stall cycles | 50.63-102.98 |
RS full (events) | 82.39-0.68 |
Front-end | 38.67 |
Dispatch | 82.00 |
DIV/SQRT | 68.00 |
Data deps. | 0.00 |
Overall L1 | 82.00 |
all | 98% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 96% |
all | 88% |
load | 66% |
store | 100% |
mul | 88% |
add-sub | 100% |
fma | 100% |
div/sqrt | 80% |
other | 88% |
all | 92% |
load | 71% |
store | 100% |
mul | 94% |
add-sub | 100% |
fma | 100% |
div/sqrt | 80% |
other | 91% |
all | 77% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 50% |
all | 84% |
load | 70% |
store | 100% |
mul | 90% |
add-sub | 100% |
fma | 100% |
div/sqrt | 82% |
other | 80% |
all | 81% |
load | 75% |
store | 100% |
mul | 94% |
add-sub | 100% |
fma | 100% |
div/sqrt | 82% |
other | 69% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VCMPPD $0x1,%ZMM31,%ZMM16,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPD $0x1,%ZMM30,%ZMM16,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBLENDMD %ZMM22,%ZMM21,%ZMM5{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%R10,8),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %ZMM11,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VANDPD %ZMM11,%ZMM14,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VANDPD %ZMM11,%ZMM9,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VANDPD %ZMM11,%ZMM7,%ZMM18 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD 0xd1d54(%RIP),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VSUBPD %ZMM28,%ZMM0,%ZMM19 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPD %ZMM29,%ZMM0,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %ZMM10,%ZMM18,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM19,%ZMM14,%ZMM19 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0xcfbfc(%RIP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VDIVSD %XMM8,%XMM0,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
VBROADCASTSD %XMM0,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMINPD %ZMM14,%ZMM13,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD %ZMM13,%ZMM28,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMINPD %ZMM18,%ZMM4,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD %ZMM4,%ZMM29,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VEXTRACTI64X4 $0x1,%ZMM5,%YMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM5,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM18,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM1,%ZMM18,%ZMM18 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPSUBQ %ZMM1,%ZMM5,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%RAX,%ZMM5,8),%ZMM6{%K3} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%RAX,%ZMM18,8),%ZMM5{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VDIVPD %ZMM6,%ZMM13,%ZMM6 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VDIVPD %ZMM5,%ZMM4,%ZMM4 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VFMADD231PD %ZMM19,%ZMM0,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %ZMM10,%ZMM0,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD 0xd1ccc(%RIP),%XMM8,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM0,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPD %ZMM4,%ZMM0,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM6,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMINPD %ZMM14,%ZMM4,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMINPD %ZMM17,%ZMM0,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFPCLASSPD $0x56,%ZMM9,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFPCLASSPD $0x56,%ZMM7,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD 0xd1c8e(%RIP),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VXORPD %ZMM0,%ZMM14,%ZMM14{%K2} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VXORPD %ZMM0,%ZMM13,%ZMM13{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VCMPPD $0x1,%ZMM30,%ZMM16,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPD $0x1,%ZMM31,%ZMM16,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM14,%ZMM0{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %ZMM13,%ZMM4{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VBROADCASTSD 0xcfb1e(%RIP),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VSUBPD %ZMM29,%ZMM6,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPD %ZMM28,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213PD %ZMM26,%ZMM4,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD %ZMM27,%ZMM0,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM25,%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM24,%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM4,(%R9,%RBX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD %ZMM0,0x40(%R9,%RBX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x10,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JG 434d80 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x30a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RDI,%RBX,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVUPD (%RSI,%RBX,8),%ZMM24 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x40(%RSI,%RBX,8),%ZMM25 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFPCLASSPD $0x50,%ZMM24,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFPCLASSPD $0x50,%ZMM25,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KUNPCKBW %K0,%K1,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VPBLENDMD %ZMM22,%ZMM23,%ZMM4{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VEXTRACTI64X4 $0x1,%ZMM4,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM7,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM1,%ZMM7,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPXOR %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM9,%ZMM2,%ZMM7 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPMOVSXDQ %YMM4,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM1,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPXOR %XMM13,%XMM13,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM4,%ZMM2,%ZMM13 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPBROADCASTQ %RAX,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ 0x2c0(%RSP),%ZMM14,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.67 |
VPSLLQ $0x3,%ZMM14,%ZMM14 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 1 |
VPADDQ 0xd2580(%RIP),%ZMM14,%ZMM26 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VPADDQ %ZMM26,%ZMM12,%ZMM27 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM13,%ZMM27,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM28,%XMM28,%XMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM13,1),%ZMM28{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPADDQ 0xd2515(%RIP),%ZMM14,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VPADDQ %ZMM13,%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM7,%ZMM14,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPXOR %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM14,1),%ZMM7{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPMULLQ %ZMM4,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM26,%ZMM15,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM4,%ZMM14,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPXORD %XMM26,%XMM26,%XMM26 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM26{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPXOR %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM9,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM13,%ZMM15,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM4,%ZMM9,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPXORD %XMM27,%XMM27,%XMM27 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM27{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPBLENDMD %ZMM20,%ZMM21,%ZMM4{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VEXTRACTI64X4 $0x1,%ZMM4,%YMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM13,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM4,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM1,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPMULLQ %ZMM4,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM4,%ZMM14,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM30,%XMM30,%XMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM30{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPSUBQ %ZMM1,%ZMM13,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPMULLQ %ZMM4,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM4,%ZMM9,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM31,%XMM31,%XMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM31{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPBLENDMD %ZMM23,%ZMM22,%ZMM4{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VANDPD %ZMM11,%ZMM24,%ZMM29 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VANDPD %ZMM11,%ZMM25,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPXOR %XMM13,%XMM13,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VDIVPD %ZMM28,%ZMM29,%ZMM28 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VEXTRACTI64X4 $0x1,%ZMM4,%YMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM29,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM4,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM1,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPMULLQ %ZMM4,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM4,%ZMM14,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM8{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPSUBQ %ZMM1,%ZMM29,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPMULLQ %ZMM4,%ZMM3,%ZMM4 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPADDQ %ZMM4,%ZMM9,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPXOR %XMM9,%XMM9,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD (,%ZMM4,1),%ZMM9{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VDIVPD %ZMM7,%ZMM5,%ZMM29 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VSUBPD %ZMM31,%ZMM27,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPD %ZMM30,%ZMM26,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPD %ZMM27,%ZMM9,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPD %ZMM26,%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %ZMM14,%ZMM9,%ZMM30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM4,%ZMM7,%ZMM31 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%ZMM31,%ZMM13,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPD $0x1,%ZMM30,%ZMM13,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KORTESTB %K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JNE 434980 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2ca0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |