Function: __generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0 | Module: exec | Source: generate_chunk_kernel.f90:85-161 | Coverage: 0.04% |
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Function: __generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0 | Module: exec | Source: generate_chunk_kernel.f90:85-161 | Coverage: 0.04% |
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/scratch_na/users/xoserete/qaas_runs/171-415-7919/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 85 - 161 |
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85: !$OMP PARALLEL SHARED(x_cent,y_cent) |
86: !$OMP DO |
87: DO k=y_min-2,y_max+2 |
88: !$OMP SIMD |
89: DO j=x_min-2,x_max+2 |
90: energy0(j,k)=state_energy(1) |
91: ENDDO |
92: ENDDO |
93: !$OMP END DO |
94: !$OMP DO |
95: DO k=y_min-2,y_max+2 |
96: !$OMP SIMD |
97: DO j=x_min-2,x_max+2 |
98: density0(j,k)=state_density(1) |
99: ENDDO |
100: ENDDO |
101: !$OMP END DO |
102: !$OMP DO |
103: DO k=y_min-2,y_max+2 |
104: !$OMP SIMD |
105: DO j=x_min-2,x_max+2 |
106: xvel0(j,k)=state_xvel(1) |
107: ENDDO |
108: ENDDO |
109: !$OMP END DO |
110: !$OMP DO |
111: DO k=y_min-2,y_max+2 |
112: !$OMP SIMD |
113: DO j=x_min-2,x_max+2 |
114: yvel0(j,k)=state_yvel(1) |
115: ENDDO |
116: ENDDO |
117: !$OMP END DO |
118: |
119: DO state=2,number_of_states |
120: |
121: ! Could the velocity setting be thread unsafe? |
122: x_cent=state_xmin(state) |
123: y_cent=state_ymin(state) |
124: |
125: !$OMP DO PRIVATE(radius,jt,kt) |
126: DO k=y_min-2,y_max+2 |
127: !$OMP SIMD |
128: DO j=x_min-2,x_max+2 |
129: IF(state_geometry(state).EQ.g_rect ) THEN |
130: IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN |
131: IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN |
132: energy0(j,k)=state_energy(state) |
133: density0(j,k)=state_density(state) |
134: DO kt=k,k+1 |
135: DO jt=j,j+1 |
136: xvel0(jt,kt)=state_xvel(state) |
137: yvel0(jt,kt)=state_yvel(state) |
138: ENDDO |
139: ENDDO |
140: ENDIF |
141: ENDIF |
142: ELSEIF(state_geometry(state).EQ.g_circ ) THEN |
143: radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent)) |
144: IF(radius.LE.state_radius(state))THEN |
145: energy0(j,k)=state_energy(state) |
146: density0(j,k)=state_density(state) |
147: DO kt=k,k+1 |
148: DO jt=j,j+1 |
149: xvel0(jt,kt)=state_xvel(state) |
150: yvel0(jt,kt)=state_yvel(state) |
151: ENDDO |
152: ENDDO |
153: ENDIF |
154: ELSEIF(state_geometry(state).EQ.g_point) THEN |
155: IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN |
156: energy0(j,k)=state_energy(state) |
157: density0(j,k)=state_density(state) |
158: DO kt=k,k+1 |
159: DO jt=j,j+1 |
160: xvel0(jt,kt)=state_xvel(state) |
161: yvel0(jt,kt)=state_yvel(state) |
0x433de0 PUSH %RBP |
0x433de1 MOV %RSP,%RBP |
0x433de4 PUSH %R15 |
0x433de6 PUSH %R14 |
0x433de8 PUSH %R13 |
0x433dea PUSH %R12 |
0x433dec MOV %RDI,%R12 |
0x433def PUSH %RBX |
0x433df0 AND $-0x40,%RSP |
0x433df4 SUB $0x180,%RSP |
0x433dfb MOV 0x128(%RDI),%RAX |
0x433e02 MOV 0x120(%RDI),%RDX |
0x433e09 MOV 0x118(%RDI),%RCX |
0x433e10 MOV 0x108(%RDI),%RSI |
0x433e17 MOV 0x100(%RDI),%R8 |
0x433e1e MOV 0xf8(%RDI),%R9 |
0x433e25 MOV %RAX,0x48(%RSP) |
0x433e2a MOV 0xf0(%RDI),%R10 |
0x433e31 MOV 0xe8(%RDI),%R11 |
0x433e38 MOV %RDX,0x140(%RSP) |
0x433e40 MOV 0xe0(%RDI),%R13 |
0x433e47 MOV 0xd0(%RDI),%RDX |
0x433e4e MOV %RCX,0x40(%RSP) |
0x433e53 MOV 0xd8(%RDI),%RAX |
0x433e5a MOV 0x110(%RDI),%RBX |
0x433e61 MOV %RSI,0x38(%RSP) |
0x433e66 MOV 0x10(%RDI),%RDI |
0x433e6a MOV %RDX,0x20(%RSP) |
0x433e6f MOV %R8,0x118(%RSP) |
0x433e77 MOV %R9,0x30(%RSP) |
0x433e7c MOV %R10,0xf8(%RSP) |
0x433e84 MOV %R11,0x120(%RSP) |
0x433e8c MOV %R13,0x100(%RSP) |
0x433e94 MOV %RAX,0x110(%RSP) |
0x433e9c MOV %RBX,0x138(%RSP) |
0x433ea4 MOV (%RDI),%EBX |
0x433ea6 CALL 402080 <@plt_start@+0x60> |
0x433eab MOV %EAX,%R13D |
0x433eae MOV %EAX,0xc8(%RSP) |
0x433eb5 SUB $0x2,%EBX |
0x433eb8 CALL 402180 <@plt_start@+0x160> |
0x433ebd MOV 0x18(%R12),%RSI |
0x433ec2 MOV %EAX,0xdc(%RSP) |
0x433ec9 MOV %EAX,%ECX |
0x433ecb MOV (%RSI),%EAX |
0x433ecd ADD $0x3,%EAX |
0x433ed0 SUB %EBX,%EAX |
0x433ed2 CLTD |
0x433ed3 IDIV %R13D |
0x433ed6 CMP %EDX,%ECX |
0x433ed8 JL 435535 |
0x433ede MOV 0xdc(%RSP),%EDI |
0x433ee5 IMUL %EAX,%EDI |
0x433ee8 ADD %EDX,%EDI |
0x433eea ADD %EDI,%EAX |
0x433eec CMP %EAX,%EDI |
0x433eee JGE 434236 |
0x433ef4 ADD %EBX,%EAX |
0x433ef6 ADD %EBX,%EDI |
0x433ef8 MOV 0xf8(%RSP),%RBX |
0x433f00 MOV (%R12),%R8 |
0x433f04 MOV 0x8(%R12),%R11 |
0x433f09 MOV 0x30(%RSP),%RDX |
0x433f0e MOV %EAX,0x170(%RSP) |
0x433f15 LEA (,%RBX,8),%RSI |
0x433f1d MOVSXD (%R8),%R9 |
0x433f20 MOV 0x70(%R12),%RAX |
0x433f25 MOV %R14D,0xd0(%RSP) |
0x433f2d MOV %RSI,0x160(%RSP) |
0x433f35 MOVSXD %EDI,%RSI |
0x433f38 MOV (%R11),%ECX |
0x433f3b IMUL %RBX,%RSI |
0x433f3f MOV %R9,%R13 |
0x433f42 LEA -0x2(%R9),%R10D |
0x433f46 MOV %R9,0xe0(%RSP) |
0x433f4e LEA 0x3(%RCX),%R8D |
0x433f52 ADD %RDX,%R9 |
0x433f55 SUB %R13D,%ECX |
0x433f58 MOV %R10D,0x178(%RSP) |
0x433f60 MOV %ECX,%R13D |
0x433f63 MOV %ECX,0x150(%RSP) |
0x433f6a MOV 0x48(%R12),%R11 |
0x433f6f ADD %RSI,%R9 |
0x433f72 ADD %RDX,%RSI |
0x433f75 LEA 0x5(%RCX),%EDX |
0x433f78 MOV %EDX,%ECX |
0x433f7a MOV %EDX,%EBX |
0x433f7c LEA -0x10(%R11,%R9,8),%R9 |
0x433f81 SHR $0x3,%ECX |
0x433f84 AND $-0x8,%EBX |
0x433f87 SAL $0x6,%RCX |
0x433f8b MOV %EBX,0x134(%RSP) |
0x433f92 CMP %R8D,%R10D |
0x433f95 MOV %RCX,0xe8(%RSP) |
0x433f9d LEA (%RBX,%R10,1),%ECX |
0x433fa1 MOV %R13D,%EBX |
0x433fa4 LEA 0x5(%R10,%R13,1),%R13D |
0x433fa9 CMOVGE %R10D,%R13D |
0x433fad LEA 0x4(%RBX),%R10D |
0x433fb1 AND $0x7,%EDX |
0x433fb4 MOV %ECX,0x128(%RSP) |
0x433fbb MOV %R10D,0x158(%RSP) |
0x433fc3 XOR %ECX,%ECX |
0x433fc5 MOV %R13D,0x168(%RSP) |
0x433fcd MOV 0xe8(%RSP),%RBX |
0x433fd5 MOV %ECX,%R14D |
0x433fd8 MOV %R12,0xe8(%RSP) |
0x433fe0 MOV 0xe0(%RSP),%R12 |
0x433fe8 MOV %EDX,0x148(%RSP) |
0x433fef MOV $0x1,%EDX |
0x433ff4 KMOVB %EDX,%K1 |
0x433ff8 NOPL (%RAX,%RAX,1) |
(237) 0x434000 CMP %R8D,0x178(%RSP) |
(237) 0x434008 JGE 4341d3 |
(237) 0x43400e CMPL $0x6,0x158(%RSP) |
(237) 0x434016 JBE 43551e |
(237) 0x43401c LEA -0x40(%RBX),%R10 |
(237) 0x434020 LEA (%RBX,%R9,1),%R13 |
(237) 0x434024 MOV %R9,%RDX |
(237) 0x434027 SHR $0x6,%R10 |
(237) 0x43402b INC %R10 |
(237) 0x43402e AND $0x7,%R10D |
(237) 0x434032 JE 4340cb |
(237) 0x434038 CMP $0x1,%R10 |
(237) 0x43403c JE 4340b5 |
(237) 0x43403e CMP $0x2,%R10 |
(237) 0x434042 JE 4340a4 |
(237) 0x434044 CMP $0x3,%R10 |
(237) 0x434048 JE 434093 |
(237) 0x43404a CMP $0x4,%R10 |
(237) 0x43404e JE 434082 |
(237) 0x434050 CMP $0x5,%R10 |
(237) 0x434054 JE 434071 |
(237) 0x434056 CMP $0x6,%R10 |
(237) 0x43405a JNE 4354df |
(237) 0x434060 VBROADCASTSD (%RAX),%ZMM1 |
(237) 0x434066 ADD $0x40,%RDX |
(237) 0x43406a VMOVUPD %ZMM1,-0x40(%RDX) |
(237) 0x434071 VBROADCASTSD (%RAX),%ZMM2 |
(237) 0x434077 ADD $0x40,%RDX |
(237) 0x43407b VMOVUPD %ZMM2,-0x40(%RDX) |
(237) 0x434082 VBROADCASTSD (%RAX),%ZMM3 |
(237) 0x434088 ADD $0x40,%RDX |
(237) 0x43408c VMOVUPD %ZMM3,-0x40(%RDX) |
(237) 0x434093 VBROADCASTSD (%RAX),%ZMM4 |
(237) 0x434099 ADD $0x40,%RDX |
(237) 0x43409d VMOVUPD %ZMM4,-0x40(%RDX) |
(237) 0x4340a4 VBROADCASTSD (%RAX),%ZMM5 |
(237) 0x4340aa ADD $0x40,%RDX |
(237) 0x4340ae VMOVUPD %ZMM5,-0x40(%RDX) |
(237) 0x4340b5 VBROADCASTSD (%RAX),%ZMM6 |
(237) 0x4340bb ADD $0x40,%RDX |
(237) 0x4340bf VMOVUPD %ZMM6,-0x40(%RDX) |
(237) 0x4340c6 CMP %R13,%RDX |
(237) 0x4340c9 JE 43413f |
(238) 0x4340cb VBROADCASTSD (%RAX),%ZMM7 |
(238) 0x4340d1 ADD $0x200,%RDX |
(238) 0x4340d8 VMOVUPD %ZMM7,-0x200(%RDX) |
(238) 0x4340df VBROADCASTSD (%RAX),%ZMM8 |
(238) 0x4340e5 VMOVUPD %ZMM8,-0x1c0(%RDX) |
(238) 0x4340ec VBROADCASTSD (%RAX),%ZMM9 |
(238) 0x4340f2 VMOVUPD %ZMM9,-0x180(%RDX) |
(238) 0x4340f9 VBROADCASTSD (%RAX),%ZMM10 |
(238) 0x4340ff VMOVUPD %ZMM10,-0x140(%RDX) |
(238) 0x434106 VBROADCASTSD (%RAX),%ZMM11 |
(238) 0x43410c VMOVUPD %ZMM11,-0x100(%RDX) |
(238) 0x434113 VBROADCASTSD (%RAX),%ZMM12 |
(238) 0x434119 VMOVUPD %ZMM12,-0xc0(%RDX) |
(238) 0x434120 VBROADCASTSD (%RAX),%ZMM13 |
(238) 0x434126 VMOVUPD %ZMM13,-0x80(%RDX) |
(238) 0x43412d VBROADCASTSD (%RAX),%ZMM14 |
(238) 0x434133 VMOVUPD %ZMM14,-0x40(%RDX) |
(238) 0x43413a CMP %R13,%RDX |
(238) 0x43413d JNE 4340cb |
(237) 0x43413f MOV 0x148(%RSP),%ECX |
(237) 0x434146 TEST %ECX,%ECX |
(237) 0x434148 JE 4341d3 |
(237) 0x43414e MOV 0x134(%RSP),%ECX |
(237) 0x434155 MOV 0x128(%RSP),%EDX |
(237) 0x43415c MOV 0x150(%RSP),%R13D |
(237) 0x434164 SUB %ECX,%R13D |
(237) 0x434167 LEA 0x5(%R13),%R10D |
(237) 0x43416b ADD $0x4,%R13D |
(237) 0x43416f CMP $0x2,%R13D |
(237) 0x434173 JBE 434196 |
(237) 0x434175 VBROADCASTSD (%RAX),%YMM15 |
(237) 0x43417a LEA (%R12,%RSI,1),%R13 |
(237) 0x43417e ADD %R13,%RCX |
(237) 0x434181 VMOVUPD %YMM15,-0x10(%R11,%RCX,8) |
(237) 0x434188 MOV %R10D,%ECX |
(237) 0x43418b AND $-0x4,%ECX |
(237) 0x43418e ADD %ECX,%EDX |
(237) 0x434190 AND $0x3,%R10D |
(237) 0x434194 JE 4341d3 |
(237) 0x434196 VMOVSD (%RAX),%XMM0 |
(237) 0x43419a MOVSXD %EDX,%R10 |
(237) 0x43419d LEA 0x1(%RDX),%R13D |
(237) 0x4341a1 ADD %RSI,%R10 |
(237) 0x4341a4 VMOVSD %XMM0,(%R11,%R10,8) |
(237) 0x4341aa CMP %R13D,%R8D |
(237) 0x4341ad JLE 4341d3 |
(237) 0x4341af MOVSXD %R13D,%RCX |
(237) 0x4341b2 ADD $0x2,%EDX |
(237) 0x4341b5 ADD %RSI,%RCX |
(237) 0x4341b8 VMOVSD %XMM0,(%R11,%RCX,8) |
(237) 0x4341be CMP %EDX,%R8D |
(237) 0x4341c1 JLE 4341d3 |
(237) 0x4341c3 VMOVSD (%RAX),%XMM1 |
(237) 0x4341c7 MOVSXD %EDX,%RDX |
(237) 0x4341ca ADD %RSI,%RDX |
(237) 0x4341cd VMOVSD %XMM1,(%R11,%RDX,8) |
(237) 0x4341d3 MOV 0x168(%RSP),%R10D |
(237) 0x4341db MOV 0x160(%RSP),%RCX |
(237) 0x4341e3 KMOVB %K1,%R13D |
(237) 0x4341e7 MOV 0xf8(%RSP),%RDX |
(237) 0x4341ef CMP %R10D,%R8D |
(237) 0x4341f2 CMOVE %R8D,%R15D |
(237) 0x4341f6 CMOVE %R13D,%R14D |
(237) 0x4341fa INC %EDI |
(237) 0x4341fc ADD %RCX,%R9 |
(237) 0x4341ff ADD %RDX,%RSI |
(237) 0x434202 CMP %EDI,0x170(%RSP) |
(237) 0x434209 JG 434000 |
0x43420f MOV %R14D,%EDI |
0x434212 MOV 0xe8(%RSP),%R12 |
0x43421a MOV 0xd0(%RSP),%R14D |
0x434222 TEST %DIL,%DIL |
0x434225 JE 435560 |
0x43422b MOV %R15D,0x140(%R12) |
0x434233 VZEROUPPER |
0x434236 CALL 402220 <@plt_start@+0x200> |
0x43423b MOV 0x10(%R12),%R15 |
0x434240 MOV 0x18(%R12),%RAX |
0x434245 MOV (%R15),%R8D |
0x434248 MOV (%RAX),%EAX |
0x43424a SUB $0x2,%R8D |
0x43424e ADD $0x3,%EAX |
0x434251 SUB %R8D,%EAX |
0x434254 CLTD |
0x434255 IDIVL 0xc8(%RSP) |
0x43425c CMP %EDX,0xdc(%RSP) |
0x434263 JL 43553e |
0x434269 MOV 0xdc(%RSP),%EDI |
0x434270 IMUL %EAX,%EDI |
0x434273 ADD %EDX,%EDI |
0x434275 ADD %EDI,%EAX |
0x434277 CMP %EAX,%EDI |
0x434279 JGE 4345be |
0x43427f MOV (%R12),%R11 |
0x434283 MOV 0x8(%R12),%RSI |
0x434288 ADD %R8D,%EDI |
0x43428b ADD %R8D,%EAX |
0x43428e MOV 0x100(%RSP),%RCX |
0x434296 MOV 0x120(%RSP),%RDX |
0x43429e MOV %EAX,0x170(%RSP) |
0x4342a5 MOVSXD (%R11),%R9 |
0x4342a8 MOV (%RSI),%R13D |
0x4342ab MOVSXD %EDI,%RSI |
0x4342ae MOV %R12,0xd0(%RSP) |
0x4342b6 IMUL %RCX,%RSI |
0x4342ba LEA (,%RCX,8),%R15 |
0x4342c2 MOV 0x40(%R12),%R11 |
0x4342c7 MOV 0x68(%R12),%RAX |
0x4342cc MOV %R9,%R10 |
0x4342cf LEA -0x2(%R9),%EBX |
0x4342d3 MOV %R9,0xe8(%RSP) |
0x4342db LEA 0x3(%R13),%R8D |
0x4342df LEA (%R9,%RDX,1),%R9 |
0x4342e3 SUB %R10D,%R13D |
0x4342e6 MOV %R15,0x160(%RSP) |
0x4342ee ADD %RSI,%R9 |
0x4342f1 ADD %RDX,%RSI |
0x4342f4 LEA 0x5(%R13),%EDX |
0x4342f8 MOV %R13D,%R10D |
0x4342fb MOV %EDX,%ECX |
0x4342fd MOV %R13D,0x150(%RSP) |
0x434305 MOV %EDX,%R13D |
0x434308 LEA 0x5(%RBX,%R10,1),%R15D |
0x43430d AND $-0x8,%ECX |
0x434310 SHR $0x3,%R13D |
0x434314 MOV %EBX,0x178(%RSP) |
0x43431b MOV 0xe8(%RSP),%R12 |
0x434323 MOV %ECX,0x134(%RSP) |
0x43432a SAL $0x6,%R13 |
0x43432e ADD %EBX,%ECX |
0x434330 CMP %R8D,%EBX |
0x434333 CMOVGE %EBX,%R15D |
0x434337 AND $0x7,%EDX |
0x43433a LEA 0x4(%R10),%EBX |
0x43433e MOV %ECX,0x128(%RSP) |
0x434345 MOV %EDX,0x148(%RSP) |
0x43434c XOR %ECX,%ECX |
0x43434e LEA -0x10(%R11,%R9,8),%R9 |
0x434353 MOV $0x1,%R10D |
0x434359 MOV %R15D,0x168(%RSP) |
0x434361 KMOVB %R10D,%K0 |
0x434366 MOV %EBX,0x158(%RSP) |
0x43436d MOV 0x108(%RSP),%EBX |
0x434374 MOV %R14D,0xe0(%RSP) |
0x43437c MOV %ECX,%R14D |
0x43437f NOP |
(235) 0x434380 CMP %R8D,0x178(%RSP) |
(235) 0x434388 JGE 434554 |
(235) 0x43438e CMPL $0x6,0x158(%RSP) |
(235) 0x434396 JBE 4354f4 |
(235) 0x43439c LEA -0x40(%R13),%R10 |
(235) 0x4343a0 LEA (%R13,%R9,1),%R15 |
(235) 0x4343a5 MOV %R9,%RDX |
(235) 0x4343a8 SHR $0x6,%R10 |
(235) 0x4343ac INC %R10 |
(235) 0x4343af AND $0x7,%R10D |
(235) 0x4343b3 JE 43444c |
(235) 0x4343b9 CMP $0x1,%R10 |
(235) 0x4343bd JE 434436 |
(235) 0x4343bf CMP $0x2,%R10 |
(235) 0x4343c3 JE 434425 |
(235) 0x4343c5 CMP $0x3,%R10 |
(235) 0x4343c9 JE 434414 |
(235) 0x4343cb CMP $0x4,%R10 |
(235) 0x4343cf JE 434403 |
(235) 0x4343d1 CMP $0x5,%R10 |
(235) 0x4343d5 JE 4343f2 |
(235) 0x4343d7 CMP $0x6,%R10 |
(235) 0x4343db JNE 4354ca |
(235) 0x4343e1 VBROADCASTSD (%RAX),%ZMM3 |
(235) 0x4343e7 ADD $0x40,%RDX |
(235) 0x4343eb VMOVUPD %ZMM3,-0x40(%RDX) |
(235) 0x4343f2 VBROADCASTSD (%RAX),%ZMM4 |
(235) 0x4343f8 ADD $0x40,%RDX |
(235) 0x4343fc VMOVUPD %ZMM4,-0x40(%RDX) |
(235) 0x434403 VBROADCASTSD (%RAX),%ZMM5 |
(235) 0x434409 ADD $0x40,%RDX |
(235) 0x43440d VMOVUPD %ZMM5,-0x40(%RDX) |
(235) 0x434414 VBROADCASTSD (%RAX),%ZMM6 |
(235) 0x43441a ADD $0x40,%RDX |
(235) 0x43441e VMOVUPD %ZMM6,-0x40(%RDX) |
(235) 0x434425 VBROADCASTSD (%RAX),%ZMM7 |
(235) 0x43442b ADD $0x40,%RDX |
(235) 0x43442f VMOVUPD %ZMM7,-0x40(%RDX) |
(235) 0x434436 VBROADCASTSD (%RAX),%ZMM8 |
(235) 0x43443c ADD $0x40,%RDX |
(235) 0x434440 VMOVUPD %ZMM8,-0x40(%RDX) |
(235) 0x434447 CMP %R15,%RDX |
(235) 0x43444a JE 4344c0 |
(236) 0x43444c VBROADCASTSD (%RAX),%ZMM9 |
(236) 0x434452 ADD $0x200,%RDX |
(236) 0x434459 VMOVUPD %ZMM9,-0x200(%RDX) |
(236) 0x434460 VBROADCASTSD (%RAX),%ZMM10 |
(236) 0x434466 VMOVUPD %ZMM10,-0x1c0(%RDX) |
(236) 0x43446d VBROADCASTSD (%RAX),%ZMM11 |
(236) 0x434473 VMOVUPD %ZMM11,-0x180(%RDX) |
(236) 0x43447a VBROADCASTSD (%RAX),%ZMM12 |
(236) 0x434480 VMOVUPD %ZMM12,-0x140(%RDX) |
(236) 0x434487 VBROADCASTSD (%RAX),%ZMM13 |
(236) 0x43448d VMOVUPD %ZMM13,-0x100(%RDX) |
(236) 0x434494 VBROADCASTSD (%RAX),%ZMM14 |
(236) 0x43449a VMOVUPD %ZMM14,-0xc0(%RDX) |
(236) 0x4344a1 VBROADCASTSD (%RAX),%ZMM15 |
(236) 0x4344a7 VMOVUPD %ZMM15,-0x80(%RDX) |
(236) 0x4344ae VBROADCASTSD (%RAX),%ZMM0 |
(236) 0x4344b4 VMOVUPD %ZMM0,-0x40(%RDX) |
(236) 0x4344bb CMP %R15,%RDX |
(236) 0x4344be JNE 43444c |
(235) 0x4344c0 MOV 0x148(%RSP),%ECX |
(235) 0x4344c7 TEST %ECX,%ECX |
(235) 0x4344c9 JE 434554 |
(235) 0x4344cf MOV 0x134(%RSP),%ECX |
(235) 0x4344d6 MOV 0x128(%RSP),%EDX |
(235) 0x4344dd MOV 0x150(%RSP),%R15D |
(235) 0x4344e5 SUB %ECX,%R15D |
(235) 0x4344e8 LEA 0x5(%R15),%R10D |
(235) 0x4344ec ADD $0x4,%R15D |
(235) 0x4344f0 CMP $0x2,%R15D |
(235) 0x4344f4 JBE 434517 |
(235) 0x4344f6 VBROADCASTSD (%RAX),%YMM1 |
(235) 0x4344fb LEA (%R12,%RSI,1),%R15 |
(235) 0x4344ff ADD %R15,%RCX |
(235) 0x434502 VMOVUPD %YMM1,-0x10(%R11,%RCX,8) |
(235) 0x434509 MOV %R10D,%ECX |
(235) 0x43450c AND $-0x4,%ECX |
(235) 0x43450f ADD %ECX,%EDX |
(235) 0x434511 AND $0x3,%R10D |
(235) 0x434515 JE 434554 |
(235) 0x434517 VMOVSD (%RAX),%XMM2 |
(235) 0x43451b MOVSXD %EDX,%R10 |
(235) 0x43451e LEA 0x1(%RDX),%R15D |
(235) 0x434522 ADD %RSI,%R10 |
(235) 0x434525 VMOVSD %XMM2,(%R11,%R10,8) |
(235) 0x43452b CMP %R15D,%R8D |
(235) 0x43452e JLE 434554 |
(235) 0x434530 MOVSXD %R15D,%RCX |
(235) 0x434533 ADD $0x2,%EDX |
(235) 0x434536 ADD %RSI,%RCX |
(235) 0x434539 VMOVSD %XMM2,(%R11,%RCX,8) |
(235) 0x43453f CMP %EDX,%R8D |
(235) 0x434542 JLE 434554 |
(235) 0x434544 VMOVSD (%RAX),%XMM3 |
(235) 0x434548 MOVSXD %EDX,%RDX |
(235) 0x43454b ADD %RSI,%RDX |
(235) 0x43454e VMOVSD %XMM3,(%R11,%RDX,8) |
(235) 0x434554 MOV 0x168(%RSP),%R10D |
(235) 0x43455c MOV 0x160(%RSP),%RCX |
(235) 0x434564 KMOVB %K0,%R15D |
(235) 0x434568 MOV 0x100(%RSP),%RDX |
(235) 0x434570 CMP %R10D,%R8D |
(235) 0x434573 CMOVE %R8D,%EBX |
(235) 0x434577 CMOVE %R15D,%R14D |
(235) 0x43457b INC %EDI |
(235) 0x43457d ADD %RCX,%R9 |
(235) 0x434580 ADD %RDX,%RSI |
(235) 0x434583 CMP %EDI,0x170(%RSP) |
(235) 0x43458a JG 434380 |
0x434590 MOV %R14D,%EDI |
0x434593 MOV 0xd0(%RSP),%R12 |
0x43459b MOV 0xe0(%RSP),%R14D |
0x4345a3 MOV %EBX,0x108(%RSP) |
0x4345aa TEST %DIL,%DIL |
0x4345ad JE 435568 |
0x4345b3 MOV %EBX,0x140(%R12) |
0x4345bb VZEROUPPER |
0x4345be CALL 402220 <@plt_start@+0x200> |
0x4345c3 MOV 0x10(%R12),%R8 |
0x4345c8 MOV 0x18(%R12),%RAX |
0x4345cd MOV (%R8),%R11D |
0x4345d0 MOV (%RAX),%EAX |
0x4345d2 SUB $0x2,%R11D |
0x4345d6 ADD $0x3,%EAX |
0x4345d9 SUB %R11D,%EAX |
0x4345dc CLTD |
0x4345dd IDIVL 0xc8(%RSP) |
0x4345e4 CMP %EDX,0xdc(%RSP) |
0x4345eb JL 43552c |
0x4345f1 MOV 0xdc(%RSP),%EDI |
0x4345f8 IMUL %EAX,%EDI |
0x4345fb ADD %EDX,%EDI |
0x4345fd ADD %EDI,%EAX |
0x4345ff CMP %EAX,%EDI |
0x434601 JGE 434946 |
0x434607 MOV (%R12),%RSI |
0x43460b MOV 0x138(%RSP),%R15 |
0x434613 ADD %R11D,%EDI |
0x434616 ADD %R11D,%EAX |
0x434619 MOV 0x8(%R12),%R10 |
0x43461e MOV 0x40(%RSP),%RDX |
0x434623 MOV %EAX,0x170(%RSP) |
0x43462a MOVSXD (%RSI),%R9 |
0x43462d MOVSXD %EDI,%RSI |
0x434630 LEA (,%R15,8),%RCX |
0x434638 MOV 0x50(%R12),%R11 |
0x43463d IMUL %R15,%RSI |
0x434641 MOV (%R10),%R10D |
0x434644 MOV 0x78(%R12),%RAX |
0x434649 MOV %RCX,0x160(%RSP) |
0x434651 MOV %R9,%R13 |
0x434654 LEA -0x2(%R9),%EBX |
0x434658 MOV %R9,0x108(%RSP) |
0x434660 LEA (%R9,%RDX,1),%R9 |
0x434664 LEA 0x3(%R10),%R8D |
0x434668 SUB %R13D,%R10D |
0x43466b MOV %EBX,0x178(%RSP) |
0x434672 ADD %RSI,%R9 |
0x434675 ADD %RDX,%RSI |
0x434678 LEA 0x5(%R10),%EDX |
0x43467c MOV %R12,0xe0(%RSP) |
0x434684 MOV %EDX,%R13D |
0x434687 MOV %EDX,%R15D |
0x43468a LEA 0x5(%RBX,%R10,1),%ECX |
0x43468f MOV 0x108(%RSP),%R12 |
0x434697 AND $-0x8,%R15D |
0x43469b SHR $0x3,%R13D |
0x43469f MOV %R10D,0x150(%RSP) |
0x4346a7 LEA -0x10(%R11,%R9,8),%R9 |
0x4346ac MOV %R15D,0x134(%RSP) |
0x4346b4 SAL $0x6,%R13 |
0x4346b8 ADD %EBX,%R15D |
0x4346bb CMP %R8D,%EBX |
0x4346be CMOVGE %EBX,%ECX |
0x4346c1 AND $0x7,%EDX |
0x4346c4 LEA 0x4(%R10),%EBX |
0x4346c8 MOV %R15D,0x128(%RSP) |
0x4346d0 MOV %EDX,0x148(%RSP) |
0x4346d7 XOR %R15D,%R15D |
0x4346da MOV $0x1,%R10D |
0x4346e0 MOV %ECX,0x168(%RSP) |
0x4346e7 KMOVB %R10D,%K2 |
0x4346ec MOV %EBX,0x158(%RSP) |
0x4346f3 MOV 0xf0(%RSP),%EBX |
0x4346fa MOV %R14D,0xe8(%RSP) |
0x434702 MOV %R15D,%R14D |
0x434705 NOPL (%RAX) |
(233) 0x434708 CMP %R8D,0x178(%RSP) |
(233) 0x434710 JGE 4348dc |
(233) 0x434716 CMPL $0x6,0x158(%RSP) |
(233) 0x43471e JBE 435510 |
(233) 0x434724 LEA -0x40(%R13),%R10 |
(233) 0x434728 LEA (%R13,%R9,1),%R15 |
(233) 0x43472d MOV %R9,%RDX |
(233) 0x434730 SHR $0x6,%R10 |
(233) 0x434734 INC %R10 |
(233) 0x434737 AND $0x7,%R10D |
(233) 0x43473b JE 4347d4 |
(233) 0x434741 CMP $0x1,%R10 |
(233) 0x434745 JE 4347be |
(233) 0x434747 CMP $0x2,%R10 |
(233) 0x43474b JE 4347ad |
(233) 0x43474d CMP $0x3,%R10 |
(233) 0x434751 JE 43479c |
(233) 0x434753 CMP $0x4,%R10 |
(233) 0x434757 JE 43478b |
(233) 0x434759 CMP $0x5,%R10 |
(233) 0x43475d JE 43477a |
(233) 0x43475f CMP $0x6,%R10 |
(233) 0x434763 JNE 4354b5 |
(233) 0x434769 VBROADCASTSD (%RAX),%ZMM5 |
(233) 0x43476f ADD $0x40,%RDX |
(233) 0x434773 VMOVUPD %ZMM5,-0x40(%RDX) |
(233) 0x43477a VBROADCASTSD (%RAX),%ZMM6 |
(233) 0x434780 ADD $0x40,%RDX |
(233) 0x434784 VMOVUPD %ZMM6,-0x40(%RDX) |
(233) 0x43478b VBROADCASTSD (%RAX),%ZMM7 |
(233) 0x434791 ADD $0x40,%RDX |
(233) 0x434795 VMOVUPD %ZMM7,-0x40(%RDX) |
(233) 0x43479c VBROADCASTSD (%RAX),%ZMM8 |
(233) 0x4347a2 ADD $0x40,%RDX |
(233) 0x4347a6 VMOVUPD %ZMM8,-0x40(%RDX) |
(233) 0x4347ad VBROADCASTSD (%RAX),%ZMM9 |
(233) 0x4347b3 ADD $0x40,%RDX |
(233) 0x4347b7 VMOVUPD %ZMM9,-0x40(%RDX) |
(233) 0x4347be VBROADCASTSD (%RAX),%ZMM10 |
(233) 0x4347c4 ADD $0x40,%RDX |
(233) 0x4347c8 VMOVUPD %ZMM10,-0x40(%RDX) |
(233) 0x4347cf CMP %R15,%RDX |
(233) 0x4347d2 JE 434848 |
(234) 0x4347d4 VBROADCASTSD (%RAX),%ZMM11 |
(234) 0x4347da ADD $0x200,%RDX |
(234) 0x4347e1 VMOVUPD %ZMM11,-0x200(%RDX) |
(234) 0x4347e8 VBROADCASTSD (%RAX),%ZMM12 |
(234) 0x4347ee VMOVUPD %ZMM12,-0x1c0(%RDX) |
(234) 0x4347f5 VBROADCASTSD (%RAX),%ZMM13 |
(234) 0x4347fb VMOVUPD %ZMM13,-0x180(%RDX) |
(234) 0x434802 VBROADCASTSD (%RAX),%ZMM14 |
(234) 0x434808 VMOVUPD %ZMM14,-0x140(%RDX) |
(234) 0x43480f VBROADCASTSD (%RAX),%ZMM15 |
(234) 0x434815 VMOVUPD %ZMM15,-0x100(%RDX) |
(234) 0x43481c VBROADCASTSD (%RAX),%ZMM0 |
(234) 0x434822 VMOVUPD %ZMM0,-0xc0(%RDX) |
(234) 0x434829 VBROADCASTSD (%RAX),%ZMM1 |
(234) 0x43482f VMOVUPD %ZMM1,-0x80(%RDX) |
(234) 0x434836 VBROADCASTSD (%RAX),%ZMM2 |
(234) 0x43483c VMOVUPD %ZMM2,-0x40(%RDX) |
(234) 0x434843 CMP %R15,%RDX |
(234) 0x434846 JNE 4347d4 |
(233) 0x434848 MOV 0x148(%RSP),%ECX |
(233) 0x43484f TEST %ECX,%ECX |
(233) 0x434851 JE 4348dc |
(233) 0x434857 MOV 0x134(%RSP),%ECX |
(233) 0x43485e MOV 0x128(%RSP),%EDX |
(233) 0x434865 MOV 0x150(%RSP),%R15D |
(233) 0x43486d SUB %ECX,%R15D |
(233) 0x434870 LEA 0x5(%R15),%R10D |
(233) 0x434874 ADD $0x4,%R15D |
(233) 0x434878 CMP $0x2,%R15D |
(233) 0x43487c JBE 43489f |
(233) 0x43487e VBROADCASTSD (%RAX),%YMM3 |
(233) 0x434883 LEA (%R12,%RSI,1),%R15 |
(233) 0x434887 ADD %R15,%RCX |
(233) 0x43488a VMOVUPD %YMM3,-0x10(%R11,%RCX,8) |
(233) 0x434891 MOV %R10D,%ECX |
(233) 0x434894 AND $-0x4,%ECX |
(233) 0x434897 ADD %ECX,%EDX |
(233) 0x434899 AND $0x3,%R10D |
(233) 0x43489d JE 4348dc |
(233) 0x43489f VMOVSD (%RAX),%XMM4 |
(233) 0x4348a3 MOVSXD %EDX,%R10 |
(233) 0x4348a6 LEA 0x1(%RDX),%R15D |
(233) 0x4348aa ADD %RSI,%R10 |
(233) 0x4348ad VMOVSD %XMM4,(%R11,%R10,8) |
(233) 0x4348b3 CMP %R15D,%R8D |
(233) 0x4348b6 JLE 4348dc |
(233) 0x4348b8 MOVSXD %R15D,%RCX |
(233) 0x4348bb ADD $0x2,%EDX |
(233) 0x4348be ADD %RSI,%RCX |
(233) 0x4348c1 VMOVSD %XMM4,(%R11,%RCX,8) |
(233) 0x4348c7 CMP %EDX,%R8D |
(233) 0x4348ca JLE 4348dc |
(233) 0x4348cc VMOVSD (%RAX),%XMM5 |
(233) 0x4348d0 MOVSXD %EDX,%RDX |
(233) 0x4348d3 ADD %RSI,%RDX |
(233) 0x4348d6 VMOVSD %XMM5,(%R11,%RDX,8) |
(233) 0x4348dc MOV 0x168(%RSP),%R10D |
(233) 0x4348e4 MOV 0x160(%RSP),%RCX |
(233) 0x4348ec KMOVB %K2,%R15D |
(233) 0x4348f0 MOV 0x138(%RSP),%RDX |
(233) 0x4348f8 CMP %R10D,%R8D |
(233) 0x4348fb CMOVE %R8D,%EBX |
(233) 0x4348ff CMOVE %R15D,%R14D |
(233) 0x434903 INC %EDI |
(233) 0x434905 ADD %RCX,%R9 |
(233) 0x434908 ADD %RDX,%RSI |
(233) 0x43490b CMP %EDI,0x170(%RSP) |
(233) 0x434912 JG 434708 |
0x434918 MOV %R14D,%EDI |
0x43491b MOV 0xe0(%RSP),%R12 |
0x434923 MOV 0xe8(%RSP),%R14D |
0x43492b MOV %EBX,0xf0(%RSP) |
0x434932 TEST %DIL,%DIL |
0x434935 JE 435558 |
0x43493b MOV %EBX,0x140(%R12) |
0x434943 VZEROUPPER |
0x434946 CALL 402220 <@plt_start@+0x200> |
0x43494b MOV 0x10(%R12),%R8 |
0x434950 MOV 0x18(%R12),%RAX |
0x434955 MOV (%R8),%R11D |
0x434958 MOV (%RAX),%EAX |
0x43495a SUB $0x2,%R11D |
0x43495e ADD $0x3,%EAX |
0x434961 SUB %R11D,%EAX |
0x434964 CLTD |
0x434965 IDIVL 0xc8(%RSP) |
0x43496c CMP %EDX,0xdc(%RSP) |
0x434973 JL 435547 |
0x434979 MOV 0xdc(%RSP),%EDI |
0x434980 IMUL %EAX,%EDI |
0x434983 ADD %EDX,%EDI |
0x434985 ADD %EDI,%EAX |
0x434987 CMP %EAX,%EDI |
0x434989 JGE 434ca7 |
0x43498f MOV (%R12),%RSI |
0x434993 MOV 0x8(%R12),%R10 |
0x434998 ADD %R11D,%EDI |
0x43499b ADD %R11D,%EAX |
0x43499e MOV 0x140(%RSP),%RBX |
0x4349a6 MOV 0x58(%R12),%R11 |
0x4349ab MOV %EAX,0x170(%RSP) |
0x4349b2 MOVSXD (%RSI),%R9 |
0x4349b5 MOV (%R10),%ECX |
0x4349b8 MOVSXD %EDI,%RSI |
0x4349bb MOV %R12,0x108(%RSP) |
0x4349c3 IMUL %RBX,%RSI |
0x4349c7 MOV 0x48(%RSP),%R10 |
0x4349cc LEA (,%RBX,8),%RDX |
0x4349d4 MOV 0x80(%R12),%RAX |
0x4349dc MOV %R9,%R13 |
0x4349df LEA 0x3(%RCX),%R8D |
0x4349e3 LEA -0x2(%R9),%R15D |
0x4349e7 MOV %RDX,0x160(%RSP) |
0x4349ef SUB %R13D,%ECX |
0x4349f2 MOV %R9,%RBX |
0x4349f5 LEA (%R9,%R10,1),%R9 |
0x4349f9 MOV %R15D,0x178(%RSP) |
0x434a01 LEA 0x5(%RCX),%EDX |
0x434a04 ADD %RSI,%R9 |
0x434a07 MOV %ECX,0x150(%RSP) |
0x434a0e ADD %R10,%RSI |
0x434a11 MOV %ECX,%R10D |
0x434a14 MOV %EDX,%ECX |
0x434a16 LEA -0x10(%R11,%R9,8),%R9 |
0x434a1b MOV %EDX,%R13D |
0x434a1e AND $-0x8,%ECX |
0x434a21 SHR $0x3,%R13D |
0x434a25 MOV %ECX,0x128(%RSP) |
0x434a2c ADD %R15D,%ECX |
0x434a2f SAL $0x6,%R13 |
0x434a33 CMP %R8D,%R15D |
0x434a36 MOV %ECX,0x134(%RSP) |
0x434a3d LEA 0x5(%R15,%R10,1),%ECX |
0x434a42 LEA 0x4(%R10),%R10D |
0x434a46 CMOVGE %R15D,%ECX |
0x434a4a MOV %R10D,0x158(%RSP) |
0x434a52 AND $0x7,%EDX |
0x434a55 XOR %R15D,%R15D |
0x434a58 MOV %EDX,0x148(%RSP) |
0x434a5f MOV %R15D,%R12D |
0x434a62 MOV $0x1,%EDX |
0x434a67 MOV %ECX,0x168(%RSP) |
0x434a6e KMOVB %EDX,%K3 |
0x434a72 NOPW (%RAX,%RAX,1) |
(231) 0x434a78 CMP %R8D,0x178(%RSP) |
(231) 0x434a80 JGE 434c4c |
(231) 0x434a86 CMPL $0x6,0x158(%RSP) |
(231) 0x434a8e JBE 435502 |
(231) 0x434a94 LEA -0x40(%R13),%R10 |
(231) 0x434a98 LEA (%R13,%R9,1),%R15 |
(231) 0x434a9d MOV %R9,%RDX |
(231) 0x434aa0 SHR $0x6,%R10 |
(231) 0x434aa4 INC %R10 |
(231) 0x434aa7 AND $0x7,%R10D |
(231) 0x434aab JE 434b44 |
(231) 0x434ab1 CMP $0x1,%R10 |
(231) 0x434ab5 JE 434b2e |
(231) 0x434ab7 CMP $0x2,%R10 |
(231) 0x434abb JE 434b1d |
(231) 0x434abd CMP $0x3,%R10 |
(231) 0x434ac1 JE 434b0c |
(231) 0x434ac3 CMP $0x4,%R10 |
(231) 0x434ac7 JE 434afb |
(231) 0x434ac9 CMP $0x5,%R10 |
(231) 0x434acd JE 434aea |
(231) 0x434acf CMP $0x6,%R10 |
(231) 0x434ad3 JNE 4354a0 |
(231) 0x434ad9 VBROADCASTSD (%RAX),%ZMM7 |
(231) 0x434adf ADD $0x40,%RDX |
(231) 0x434ae3 VMOVUPD %ZMM7,-0x40(%RDX) |
(231) 0x434aea VBROADCASTSD (%RAX),%ZMM8 |
(231) 0x434af0 ADD $0x40,%RDX |
(231) 0x434af4 VMOVUPD %ZMM8,-0x40(%RDX) |
(231) 0x434afb VBROADCASTSD (%RAX),%ZMM9 |
(231) 0x434b01 ADD $0x40,%RDX |
(231) 0x434b05 VMOVUPD %ZMM9,-0x40(%RDX) |
(231) 0x434b0c VBROADCASTSD (%RAX),%ZMM10 |
(231) 0x434b12 ADD $0x40,%RDX |
(231) 0x434b16 VMOVUPD %ZMM10,-0x40(%RDX) |
(231) 0x434b1d VBROADCASTSD (%RAX),%ZMM11 |
(231) 0x434b23 ADD $0x40,%RDX |
(231) 0x434b27 VMOVUPD %ZMM11,-0x40(%RDX) |
(231) 0x434b2e VBROADCASTSD (%RAX),%ZMM12 |
(231) 0x434b34 ADD $0x40,%RDX |
(231) 0x434b38 VMOVUPD %ZMM12,-0x40(%RDX) |
(231) 0x434b3f CMP %R15,%RDX |
(231) 0x434b42 JE 434bb8 |
(232) 0x434b44 VBROADCASTSD (%RAX),%ZMM13 |
(232) 0x434b4a ADD $0x200,%RDX |
(232) 0x434b51 VMOVUPD %ZMM13,-0x200(%RDX) |
(232) 0x434b58 VBROADCASTSD (%RAX),%ZMM14 |
(232) 0x434b5e VMOVUPD %ZMM14,-0x1c0(%RDX) |
(232) 0x434b65 VBROADCASTSD (%RAX),%ZMM15 |
(232) 0x434b6b VMOVUPD %ZMM15,-0x180(%RDX) |
(232) 0x434b72 VBROADCASTSD (%RAX),%ZMM0 |
(232) 0x434b78 VMOVUPD %ZMM0,-0x140(%RDX) |
(232) 0x434b7f VBROADCASTSD (%RAX),%ZMM1 |
(232) 0x434b85 VMOVUPD %ZMM1,-0x100(%RDX) |
(232) 0x434b8c VBROADCASTSD (%RAX),%ZMM2 |
(232) 0x434b92 VMOVUPD %ZMM2,-0xc0(%RDX) |
(232) 0x434b99 VBROADCASTSD (%RAX),%ZMM3 |
(232) 0x434b9f VMOVUPD %ZMM3,-0x80(%RDX) |
(232) 0x434ba6 VBROADCASTSD (%RAX),%ZMM4 |
(232) 0x434bac VMOVUPD %ZMM4,-0x40(%RDX) |
(232) 0x434bb3 CMP %R15,%RDX |
(232) 0x434bb6 JNE 434b44 |
(231) 0x434bb8 MOV 0x148(%RSP),%ECX |
(231) 0x434bbf TEST %ECX,%ECX |
(231) 0x434bc1 JE 434c4c |
(231) 0x434bc7 MOV 0x128(%RSP),%ECX |
(231) 0x434bce MOV 0x134(%RSP),%EDX |
(231) 0x434bd5 MOV 0x150(%RSP),%R15D |
(231) 0x434bdd SUB %ECX,%R15D |
(231) 0x434be0 LEA 0x5(%R15),%R10D |
(231) 0x434be4 ADD $0x4,%R15D |
(231) 0x434be8 CMP $0x2,%R15D |
(231) 0x434bec JBE 434c0f |
(231) 0x434bee VBROADCASTSD (%RAX),%YMM5 |
(231) 0x434bf3 LEA (%RBX,%RSI,1),%R15 |
(231) 0x434bf7 ADD %R15,%RCX |
(231) 0x434bfa VMOVUPD %YMM5,-0x10(%R11,%RCX,8) |
(231) 0x434c01 MOV %R10D,%ECX |
(231) 0x434c04 AND $-0x4,%ECX |
(231) 0x434c07 ADD %ECX,%EDX |
(231) 0x434c09 AND $0x3,%R10D |
(231) 0x434c0d JE 434c4c |
(231) 0x434c0f VMOVSD (%RAX),%XMM6 |
(231) 0x434c13 MOVSXD %EDX,%R10 |
(231) 0x434c16 LEA 0x1(%RDX),%R15D |
(231) 0x434c1a ADD %RSI,%R10 |
(231) 0x434c1d VMOVSD %XMM6,(%R11,%R10,8) |
(231) 0x434c23 CMP %R8D,%R15D |
(231) 0x434c26 JGE 434c4c |
(231) 0x434c28 MOVSXD %R15D,%RCX |
(231) 0x434c2b ADD $0x2,%EDX |
(231) 0x434c2e ADD %RSI,%RCX |
(231) 0x434c31 VMOVSD %XMM6,(%R11,%RCX,8) |
(231) 0x434c37 CMP %R8D,%EDX |
(231) 0x434c3a JGE 434c4c |
(231) 0x434c3c VMOVSD (%RAX),%XMM7 |
(231) 0x434c40 MOVSXD %EDX,%RDX |
(231) 0x434c43 ADD %RSI,%RDX |
(231) 0x434c46 VMOVSD %XMM7,(%R11,%RDX,8) |
(231) 0x434c4c MOV 0x168(%RSP),%R10D |
(231) 0x434c54 MOV 0x160(%RSP),%RCX |
(231) 0x434c5c KMOVB %K3,%R15D |
(231) 0x434c60 MOV 0x140(%RSP),%RDX |
(231) 0x434c68 CMP %R10D,%R8D |
(231) 0x434c6b CMOVE %R8D,%R14D |
(231) 0x434c6f CMOVE %R15D,%R12D |
(231) 0x434c73 INC %EDI |
(231) 0x434c75 ADD %RCX,%R9 |
(231) 0x434c78 ADD %RDX,%RSI |
(231) 0x434c7b CMP %EDI,0x170(%RSP) |
(231) 0x434c82 JG 434a78 |
0x434c88 MOV %R12D,%EDI |
0x434c8b MOV 0x108(%RSP),%R12 |
0x434c93 TEST %DIL,%DIL |
0x434c96 JE 435550 |
0x434c9c MOV %R14D,0x140(%R12) |
0x434ca4 VZEROUPPER |
0x434ca7 CALL 402220 <@plt_start@+0x200> |
0x434cac MOV 0x60(%R12),%R14 |
0x434cb1 MOV (%R14),%R8D |
0x434cb4 CMP $0x1,%R8D |
0x434cb8 JLE 435491 |
0x434cbe MOV 0x120(%RSP),%RSI |
0x434cc6 MOV 0x100(%RSP),%RAX |
0x434cce MOV %R8,0x58(%RSP) |
0x434cd3 MOV 0x118(%RSP),%R11 |
0x434cdb MOV 0x110(%RSP),%R9 |
0x434ce3 MOV 0x38(%RSP),%R13 |
0x434ce8 NEG %RAX |
0x434ceb LEA -0x1(%RSI),%R15 |
0x434cef SUB %RSI,%R11 |
0x434cf2 SAL $0x3,%RAX |
0x434cf6 MOV %R15,0x8(%RSP) |
0x434cfb SUB %R13,%R9 |
0x434cfe LEA (,%R11,8),%RBX |
0x434d06 MOV %RAX,0xd0(%RSP) |
0x434d0e LEA (,%R9,8),%R10 |
0x434d16 MOV %RBX,0x18(%RSP) |
0x434d1b MOV $0x1,%EBX |
0x434d20 MOV %R10,0x10(%RSP) |
0x434d25 JMP 434d46 |
0x434d27 NOPW (%RAX,%RAX,1) |
(228) 0x434d30 CALL 402220 <@plt_start@+0x200> |
(228) 0x434d35 MOV 0x58(%RSP),%R13 |
(228) 0x434d3a INC %RBX |
(228) 0x434d3d CMP %R13,%RBX |
(228) 0x434d40 JE 435491 |
(228) 0x434d46 MOV 0x10(%R12),%RDI |
(228) 0x434d4b MOV 0x18(%R12),%R8 |
(228) 0x434d50 MOV 0x98(%R12),%RDX |
(228) 0x434d58 MOV 0x88(%R12),%RCX |
(228) 0x434d60 MOV (%RDI),%R14D |
(228) 0x434d63 MOV (%R8),%EAX |
(228) 0x434d66 VMOVSD (%RDX,%RBX,8),%XMM3 |
(228) 0x434d6b VMOVSD (%RCX,%RBX,8),%XMM2 |
(228) 0x434d70 MOV %RDX,0xb0(%RSP) |
(228) 0x434d78 SUB $0x2,%R14D |
(228) 0x434d7c ADD $0x3,%EAX |
(228) 0x434d7f MOV %RCX,0x158(%RSP) |
(228) 0x434d87 SUB %R14D,%EAX |
(228) 0x434d8a VUNPCKLPD %XMM2,%XMM3,%XMM8 |
(228) 0x434d8e CLTD |
(228) 0x434d8f VMOVUPD %XMM8,0x130(%R12) |
(228) 0x434d99 IDIVL 0xc8(%RSP) |
(228) 0x434da0 CMP %EDX,0xdc(%RSP) |
(228) 0x434da7 JL 435488 |
(228) 0x434dad MOV 0xdc(%RSP),%R11D |
(228) 0x434db5 IMUL %EAX,%R11D |
(228) 0x434db9 ADD %R11D,%EDX |
(228) 0x434dbc ADD %EDX,%EAX |
(228) 0x434dbe CMP %EAX,%EDX |
(228) 0x434dc0 JGE 434d30 |
(228) 0x434dc6 MOV 0x8(%R12),%R13 |
(228) 0x434dcb MOV 0xb8(%R12),%RCX |
(228) 0x434dd3 LEA (%R14,%RDX,1),%ESI |
(228) 0x434dd7 ADD %R14D,%EAX |
(228) 0x434dda KXORB %K4,%K4,%K4 |
(228) 0x434dde MOV (%R12),%R9 |
(228) 0x434de2 MOV 0x78(%R12),%RDX |
(228) 0x434de7 MOV %EAX,0xd8(%RSP) |
(228) 0x434dee MOV (%R13),%R8D |
(228) 0x434df2 MOV 0xc8(%R12),%RAX |
(228) 0x434dfa MOV %RCX,0xa0(%RSP) |
(228) 0x434e02 MOV 0x90(%R12),%RCX |
(228) 0x434e0a MOV (%R9),%R9D |
(228) 0x434e0d MOV %ESI,0x160(%RSP) |
(228) 0x434e14 MOV 0x50(%R12),%R11 |
(228) 0x434e19 LEA 0x3(%R8),%R10D |
(228) 0x434e1d MOV 0xc0(%R12),%R14 |
(228) 0x434e25 MOV %RDX,0x50(%RSP) |
(228) 0x434e2a MOV %RCX,0xf0(%RSP) |
(228) 0x434e32 MOV 0x100(%RSP),%RCX |
(228) 0x434e3a MOVSXD %ESI,%RDX |
(228) 0x434e3d LEA -0x2(%R9),%EDI |
(228) 0x434e41 MOV 0x8(%RSP),%RSI |
(228) 0x434e46 MOV 0xb0(%R12),%R15 |
(228) 0x434e4e MOV %R10D,0x134(%RSP) |
(228) 0x434e56 MOV 0x58(%R12),%R10 |
(228) 0x434e5b IMUL %RDX,%RCX |
(228) 0x434e5f MOV 0x80(%R12),%R13 |
(228) 0x434e67 MOV %RAX,0x168(%RSP) |
(228) 0x434e6f MOV %R11,0xc0(%RSP) |
(228) 0x434e77 MOVSXD %R9D,%RAX |
(228) 0x434e7a LEA 0x4(%R8),%R11D |
(228) 0x434e7e SUB %R9D,%R11D |
(228) 0x434e81 MOV %R10,0xb8(%RSP) |
(228) 0x434e89 LEA (%RSI,%RAX,1),%R10 |
(228) 0x434e8d ADD %R11,%R10 |
(228) 0x434e90 MOV %R14,0x178(%RSP) |
(228) 0x434e98 MOV 0x18(%RSP),%R14 |
(228) 0x434e9d ADD %RCX,%R10 |
(228) 0x434ea0 MOV 0xd0(%RSP),%RCX |
(228) 0x434ea8 MOV %R15,0xa8(%RSP) |
(228) 0x434eb0 MOV %R13,0x68(%RSP) |
(228) 0x434eb5 MOV 0xa8(%R12),%R15 |
(228) 0x434ebd IMUL %RDX,%RCX |
(228) 0x434ec1 MOV 0x20(%R12),%R13 |
(228) 0x434ec6 MOV %R15,0x110(%RSP) |
(228) 0x434ece MOV 0x38(%RSP),%R15 |
(228) 0x434ed3 MOV 0x40(%RSP),%RSI |
(228) 0x434ed8 MOV %EDI,0xe0(%RSP) |
(228) 0x434edf ADD %R14,%RCX |
(228) 0x434ee2 LEA (%RDX,%R15,1),%R15 |
(228) 0x434ee6 ADD %RCX,%R13 |
(228) 0x434ee9 MOV 0x138(%RSP),%RCX |
(228) 0x434ef1 IMUL %RDX,%RCX |
(228) 0x434ef5 LEA (%RCX,%RSI,1),%R14 |
(228) 0x434ef9 MOV 0x140(%RSP),%RCX |
(228) 0x434f01 MOV 0x48(%RSP),%RSI |
(228) 0x434f06 IMUL %RDX,%RCX |
(228) 0x434f0a ADD %RSI,%RCX |
(228) 0x434f0d MOVSXD %EDI,%RSI |
(228) 0x434f10 MOV 0xf8(%RSP),%RDI |
(228) 0x434f18 MOV %RCX,0x128(%RSP) |
(228) 0x434f20 MOV 0x30(%RSP),%RCX |
(228) 0x434f25 IMUL %RDI,%RDX |
(228) 0x434f29 MOV 0x30(%R12),%RDI |
(228) 0x434f2e ADD %RSI,%RCX |
(228) 0x434f31 ADD %RDX,%RCX |
(228) 0x434f34 MOV 0x20(%RSP),%RDX |
(228) 0x434f39 MOV %RCX,0x120(%RSP) |
(228) 0x434f41 LEA (,%RAX,8),%RCX |
(228) 0x434f49 ADD %RAX,%RDX |
(228) 0x434f4c ADD %R11,%RDX |
(228) 0x434f4f LEA (%RDI,%RDX,8),%RDX |
(228) 0x434f53 MOV 0x10(%RSP),%RDI |
(228) 0x434f58 MOV %RDX,0x98(%RSP) |
(228) 0x434f60 MOV $0x1,%EDX |
(228) 0x434f65 ADD 0x38(%R12),%RDI |
(228) 0x434f6a MOV %RDI,0x108(%RSP) |
(228) 0x434f72 MOV 0xe0(%RSP),%EDI |
(228) 0x434f79 LEA 0x5(%RDI,%R8,1),%R8D |
(228) 0x434f7e SUB %R9D,%R8D |
(228) 0x434f81 CMP %EDI,0x134(%RSP) |
(228) 0x434f88 MOV 0xc0(%RSP),%R9 |
(228) 0x434f90 CMOVLE %EDI,%R8D |
(228) 0x434f94 SUB %RAX,%RDX |
(228) 0x434f97 MOV %RDX,%RDI |
(228) 0x434f9a ADD %RSI,%RDI |
(228) 0x434f9d MOV %R8D,0xcc(%RSP) |
(228) 0x434fa5 MOV 0xb8(%RSP),%RSI |
(228) 0x434fad SUB %R11,%RDI |
(228) 0x434fb0 LEA -0x10(%R9,%RCX,1),%R11 |
(228) 0x434fb5 MOV 0x40(%RSP),%R8 |
(228) 0x434fba LEA (,%RBX,8),%R9 |
(228) 0x434fc2 MOV %RDI,0x90(%RSP) |
(228) 0x434fca MOV 0x48(%RSP),%RDI |
(228) 0x434fcf LEA -0x10(%RSI,%RCX,1),%RCX |
(228) 0x434fd4 MOV %R11,0x88(%RSP) |
(228) 0x434fdc MOV 0x50(%RSP),%R11 |
(228) 0x434fe1 LEA (%RAX,%R8,1),%RDX |
(228) 0x434fe5 LEA (%RAX,%RDI,1),%RAX |
(228) 0x434fe9 MOV %RCX,0x80(%RSP) |
(228) 0x434ff1 ADD %R9,%R11 |
(228) 0x434ff4 MOV %RDX,0x78(%RSP) |
(228) 0x434ff9 MOV %RAX,0x70(%RSP) |
(228) 0x434ffe MOV %R9,0x60(%RSP) |
(228) 0x435003 MOV %R11,0xe8(%RSP) |
(228) 0x43500b NOPL (%RAX,%RAX,1) |
(229) 0x435010 MOV 0xe0(%RSP),%ESI |
(229) 0x435017 INCL 0x160(%RSP) |
(229) 0x43501e CMP %ESI,0x134(%RSP) |
(229) 0x435025 JLE 435470 |
(229) 0x43502b MOV 0xa8(%RSP),%RCX |
(229) 0x435033 MOV 0xa0(%RSP),%RDX |
(229) 0x43503b MOV %R14,0x118(%RSP) |
(229) 0x435043 MOV 0x90(%RSP),%RDI |
(229) 0x43504b MOV 0x88(%RSP),%RAX |
(229) 0x435053 MOV (%RCX,%RBX,4),%R8D |
(229) 0x435057 MOV (%RDX),%R11D |
(229) 0x43505a MOV 0x138(%RSP),%RCX |
(229) 0x435062 MOVSXD 0x160(%RSP),%RDX |
(229) 0x43506a ADD %R10,%RDI |
(229) 0x43506d MOV 0x80(%RSP),%R9 |
(229) 0x435075 MOV 0x128(%RSP),%RSI |
(229) 0x43507d MOV %RDI,0x170(%RSP) |
(229) 0x435085 LEA (%RAX,%R14,8),%RDI |
(229) 0x435089 IMUL %RDX,%RCX |
(229) 0x43508d MOV 0x78(%RSP),%RAX |
(229) 0x435092 LEA (%R9,%RSI,8),%RSI |
(229) 0x435096 MOV 0xc0(%RSP),%R9 |
(229) 0x43509e ADD %RAX,%RCX |
(229) 0x4350a1 MOV 0x140(%RSP),%RAX |
(229) 0x4350a9 LEA -0x10(%R9,%RCX,8),%RCX |
(229) 0x4350ae MOV 0x70(%RSP),%R9 |
(229) 0x4350b3 IMUL %RAX,%RDX |
(229) 0x4350b7 MOV 0xb8(%RSP),%RAX |
(229) 0x4350bf ADD %R9,%RDX |
(229) 0x4350c2 MOV %R10,%R9 |
(229) 0x4350c5 LEA -0x10(%RAX,%RDX,8),%RDX |
(229) 0x4350ca MOV 0x98(%RSP),%RAX |
(229) 0x4350d2 NEG %R9 |
(229) 0x4350d5 LEA -0x8(%RAX,%R9,8),%R9 |
(229) 0x4350da LEA 0x1(%R15),%RAX |
(229) 0x4350de MOV %R9,0x148(%RSP) |
(229) 0x4350e6 MOV 0x120(%RSP),%R9 |
(229) 0x4350ee MOV %RAX,0x150(%RSP) |
(229) 0x4350f6 MOV 0x170(%RSP),%RAX |
(229) 0x4350fe MOV %R15,0x170(%RSP) |
(229) 0x435106 JMP 435151 |
0x435108 NOPL (%RAX,%RAX,1) |
(230) 0x435110 MOV 0x178(%RSP),%R14 |
(230) 0x435118 CMP (%R14),%R8D |
(230) 0x43511b JE 435270 |
(230) 0x435121 MOV 0x168(%RSP),%R15 |
(230) 0x435129 CMP (%R15),%R8D |
(230) 0x43512c JE 435328 |
(230) 0x435132 INC %RAX |
(230) 0x435135 INC %R9 |
(230) 0x435138 ADD $0x8,%RDI |
(230) 0x43513c ADD $0x8,%RSI |
(230) 0x435140 ADD $0x8,%RCX |
(230) 0x435144 ADD $0x8,%RDX |
(230) 0x435148 CMP %R10,%RAX |
(230) 0x43514b JE 4353b0 |
(230) 0x435151 CMP %R11D,%R8D |
(230) 0x435154 JNE 435110 |
(230) 0x435156 VMOVSD 0x8(%R13,%RAX,8),%XMM11 |
(230) 0x43515d MOV 0x158(%RSP),%R14 |
(230) 0x435165 VCOMISD (%R14,%RBX,8),%XMM11 |
(230) 0x43516b JB 435132 |
(230) 0x43516d MOV 0xf0(%RSP),%R15 |
(230) 0x435175 VMOVSD (%R15,%RBX,8),%XMM12 |
(230) 0x43517b VCOMISD (%R13,%RAX,8),%XMM12 |
(230) 0x435182 JBE 435132 |
(230) 0x435184 MOV 0x150(%RSP),%R15 |
(230) 0x43518c MOV 0x28(%R12),%R14 |
(230) 0x435191 VMOVSD (%R14,%R15,8),%XMM13 |
(230) 0x435197 MOV 0xb0(%RSP),%R15 |
(230) 0x43519f VCOMISD (%R15,%RBX,8),%XMM13 |
(230) 0x4351a5 JB 435132 |
(230) 0x4351a7 MOV 0xa0(%R12),%R15 |
(230) 0x4351af VMOVSD (%R15,%RBX,8),%XMM14 |
(230) 0x4351b5 MOV 0x170(%RSP),%R15 |
(230) 0x4351bd VCOMISD (%R14,%R15,8),%XMM14 |
(230) 0x4351c3 JBE 435132 |
(230) 0x4351c9 MOV 0x70(%R12),%R14 |
(230) 0x4351ce MOV 0x48(%R12),%R15 |
(230) 0x4351d3 VMOVSD (%R14,%RBX,8),%XMM15 |
(230) 0x4351d9 MOV 0x68(%R12),%R14 |
(230) 0x4351de VMOVSD %XMM15,(%R15,%R9,8) |
(230) 0x4351e4 MOV 0x40(%R12),%R15 |
(230) 0x4351e9 VMOVSD (%R14,%RBX,8),%XMM0 |
(230) 0x4351ef LEA (,%RBX,8),%R14 |
(230) 0x4351f7 VMOVSD %XMM0,(%R15,%RAX,8) |
(230) 0x4351fd MOV 0x50(%RSP),%R15 |
(230) 0x435202 ADD %R14,%R15 |
(230) 0x435205 VMOVSD (%R15),%XMM1 |
(230) 0x43520a MOV %R15,0x28(%RSP) |
(230) 0x43520f MOV 0x68(%RSP),%R15 |
(230) 0x435214 VMOVSD %XMM1,(%RDI) |
(230) 0x435218 ADD %R15,%R14 |
(230) 0x43521b MOV 0x28(%RSP),%R15 |
(230) 0x435220 VMOVSD (%R14),%XMM4 |
(230) 0x435225 VMOVSD %XMM4,(%RSI) |
(230) 0x435229 NOPL (%RAX) |
(230) 0x435230 VMOVSD (%R15),%XMM5 |
(230) 0x435235 VMOVSD %XMM5,0x8(%RDI) |
(230) 0x43523a VMOVSD (%R14),%XMM6 |
(230) 0x43523f VMOVSD %XMM6,0x8(%RSI) |
(230) 0x435244 VMOVSD (%R15),%XMM7 |
(230) 0x435249 VMOVSD %XMM7,(%RCX) |
(230) 0x43524d VMOVSD (%R14),%XMM8 |
(230) 0x435252 VMOVSD %XMM8,(%RDX) |
(230) 0x435256 VMOVSD (%R15),%XMM9 |
(230) 0x43525b VMOVSD %XMM9,0x8(%RCX) |
(230) 0x435260 VMOVSD (%R14),%XMM10 |
(230) 0x435265 VMOVSD %XMM10,0x8(%RDX) |
(230) 0x43526a JMP 435132 |
0x43526f NOP |
(230) 0x435270 MOV 0x148(%RSP),%R14 |
(230) 0x435278 MOV 0x170(%RSP),%R15 |
(230) 0x435280 VMOVSD (%R14,%RAX,8),%XMM13 |
(230) 0x435286 MOV 0x108(%RSP),%R14 |
(230) 0x43528e VMOVSD (%R14,%R15,8),%XMM15 |
(230) 0x435294 VSUBSD %XMM2,%XMM13,%XMM14 |
(230) 0x435298 MOV 0x110(%RSP),%R14 |
(230) 0x4352a0 VSUBSD %XMM3,%XMM15,%XMM0 |
(230) 0x4352a4 VUNPCKLPD %XMM0,%XMM14,%XMM1 |
(230) 0x4352a8 VMULPD %XMM1,%XMM1,%XMM4 |
(230) 0x4352ac VUNPCKHPD %XMM4,%XMM4,%XMM5 |
(230) 0x4352b0 VADDPD %XMM4,%XMM5,%XMM6 |
(230) 0x4352b4 VSQRTSD %XMM6,%XMM6,%XMM6 |
(230) 0x4352b8 VCOMISD (%R14,%RBX,8),%XMM6 |
(230) 0x4352be JA 435132 |
(230) 0x4352c4 MOV 0x70(%R12),%R15 |
(230) 0x4352c9 MOV 0x48(%R12),%R14 |
(230) 0x4352ce VMOVSD (%R15,%RBX,8),%XMM7 |
(230) 0x4352d4 MOV 0x68(%R12),%R15 |
(230) 0x4352d9 VMOVSD %XMM7,(%R14,%R9,8) |
(230) 0x4352df MOV 0x40(%R12),%R14 |
(230) 0x4352e4 VMOVSD (%R15,%RBX,8),%XMM8 |
(230) 0x4352ea MOV 0xe8(%RSP),%R15 |
(230) 0x4352f2 VMOVSD %XMM8,(%R14,%RAX,8) |
(230) 0x4352f8 MOV 0x60(%RSP),%R14 |
(230) 0x4352fd VMOVSD (%R15),%XMM9 |
(230) 0x435302 MOV 0x68(%RSP),%R15 |
(230) 0x435307 VMOVSD %XMM9,(%RDI) |
(230) 0x43530b ADD %R15,%R14 |
(230) 0x43530e MOV 0xe8(%RSP),%R15 |
(230) 0x435316 VMOVSD (%R14),%XMM10 |
(230) 0x43531b VMOVSD %XMM10,(%RSI) |
(230) 0x43531f JMP 435230 |
0x435324 NOPL (%RAX) |
(230) 0x435328 VCOMISD (%R13,%RAX,8),%XMM2 |
(230) 0x43532f JNE 435132 |
(230) 0x435335 MOV 0x28(%R12),%R14 |
(230) 0x43533a MOV 0x170(%RSP),%R15 |
(230) 0x435342 VCOMISD (%R14,%R15,8),%XMM3 |
(230) 0x435348 JNE 435132 |
(230) 0x43534e MOV 0x70(%R12),%R14 |
(230) 0x435353 MOV 0x48(%R12),%R15 |
(230) 0x435358 VMOVSD (%R14,%RBX,8),%XMM9 |
(230) 0x43535e MOV 0x68(%R12),%R14 |
(230) 0x435363 VMOVSD %XMM9,(%R15,%R9,8) |
(230) 0x435369 MOV 0x40(%R12),%R15 |
(230) 0x43536e VMOVSD (%R14,%RBX,8),%XMM10 |
(230) 0x435374 MOV 0xe8(%RSP),%R14 |
(230) 0x43537c VMOVSD %XMM10,(%R15,%RAX,8) |
(230) 0x435382 MOV 0x60(%RSP),%R15 |
(230) 0x435387 VMOVSD (%R14),%XMM11 |
(230) 0x43538c MOV 0x68(%RSP),%R14 |
(230) 0x435391 VMOVSD %XMM11,(%RDI) |
(230) 0x435395 ADD %R15,%R14 |
(230) 0x435398 MOV 0xe8(%RSP),%R15 |
(230) 0x4353a0 VMOVSD (%R14),%XMM12 |
(230) 0x4353a5 VMOVSD %XMM12,(%RSI) |
(230) 0x4353a9 JMP 435230 |
0x4353ae XCHG %AX,%AX |
(229) 0x4353b0 MOV 0x118(%RSP),%R14 |
(229) 0x4353b8 MOV 0x134(%RSP),%R15D |
(229) 0x4353c0 MOV 0xcc(%RSP),%EAX |
(229) 0x4353c7 MOV $0x1,%ECX |
(229) 0x4353cc KMOVB %K4,%ESI |
(229) 0x4353d0 MOV 0x130(%RSP),%EDX |
(229) 0x4353d7 MOV 0x100(%RSP),%RDI |
(229) 0x4353df CMP %EAX,%R15D |
(229) 0x4353e2 MOV 0xd0(%RSP),%R8 |
(229) 0x4353ea MOV 0x138(%RSP),%R9 |
(229) 0x4353f2 CMOVE %R15D,%EDX |
(229) 0x4353f6 CMOVE %ECX,%ESI |
(229) 0x4353f9 MOV 0x140(%RSP),%R11 |
(229) 0x435401 MOV 0xf8(%RSP),%RAX |
(229) 0x435409 MOV 0x150(%RSP),%R15 |
(229) 0x435411 ADD %RDI,%R10 |
(229) 0x435414 ADD %R8,%R13 |
(229) 0x435417 MOV %EDX,0x130(%RSP) |
(229) 0x43541e MOV 0x160(%RSP),%EDX |
(229) 0x435425 ADD %R9,%R14 |
(229) 0x435428 KMOVB %ESI,%K4 |
(229) 0x43542c ADD %R11,0x128(%RSP) |
(229) 0x435434 ADD %RAX,0x120(%RSP) |
(229) 0x43543c CMP %EDX,0xd8(%RSP) |
(229) 0x435443 JG 435010 |
(228) 0x435449 KORTESTB %K4,%K4 |
(228) 0x43544d JE 434d30 |
(228) 0x435453 MOV 0x130(%RSP),%R10D |
(228) 0x43545b MOV %R10D,0x140(%R12) |
(228) 0x435463 JMP 434d30 |
0x435468 NOPL (%RAX,%RAX,1) |
(229) 0x435470 LEA 0x1(%R15),%R15 |
(229) 0x435474 MOV %R15,0x150(%RSP) |
(229) 0x43547c JMP 4353b8 |
0x435481 NOPL (%RAX) |
(228) 0x435488 INC %EAX |
(228) 0x43548a XOR %EDX,%EDX |
(228) 0x43548c JMP 434dad |
0x435491 LEA -0x28(%RBP),%RSP |
0x435495 POP %RBX |
0x435496 POP %R12 |
0x435498 POP %R13 |
0x43549a POP %R14 |
0x43549c POP %R15 |
0x43549e POP %RBP |
0x43549f RET |
(231) 0x4354a0 VBROADCASTSD (%RAX),%ZMM6 |
(231) 0x4354a6 LEA 0x40(%R9),%RDX |
(231) 0x4354aa VMOVUPD %ZMM6,(%R9) |
(231) 0x4354b0 JMP 434ad9 |
(233) 0x4354b5 VBROADCASTSD (%RAX),%ZMM4 |
(233) 0x4354bb LEA 0x40(%R9),%RDX |
(233) 0x4354bf VMOVUPD %ZMM4,(%R9) |
(233) 0x4354c5 JMP 434769 |
(235) 0x4354ca VBROADCASTSD (%RAX),%ZMM2 |
(235) 0x4354d0 LEA 0x40(%R9),%RDX |
(235) 0x4354d4 VMOVUPD %ZMM2,(%R9) |
(235) 0x4354da JMP 4343e1 |
(237) 0x4354df VBROADCASTSD (%RAX),%ZMM0 |
(237) 0x4354e5 LEA 0x40(%R9),%RDX |
(237) 0x4354e9 VMOVUPD %ZMM0,(%R9) |
(237) 0x4354ef JMP 434060 |
(235) 0x4354f4 MOV 0x178(%RSP),%EDX |
(235) 0x4354fb XOR %ECX,%ECX |
(235) 0x4354fd JMP 4344dd |
(231) 0x435502 MOV 0x178(%RSP),%EDX |
(231) 0x435509 XOR %ECX,%ECX |
(231) 0x43550b JMP 434bd5 |
(233) 0x435510 MOV 0x178(%RSP),%EDX |
(233) 0x435517 XOR %ECX,%ECX |
(233) 0x435519 JMP 434865 |
(237) 0x43551e MOV 0x178(%RSP),%EDX |
(237) 0x435525 XOR %ECX,%ECX |
(237) 0x435527 JMP 43415c |
0x43552c INC %EAX |
0x43552e XOR %EDX,%EDX |
0x435530 JMP 4345f1 |
0x435535 INC %EAX |
0x435537 XOR %EDX,%EDX |
0x435539 JMP 433ede |
0x43553e INC %EAX |
0x435540 XOR %EDX,%EDX |
0x435542 JMP 434269 |
0x435547 INC %EAX |
0x435549 XOR %EDX,%EDX |
0x43554b JMP 434979 |
0x435550 VZEROUPPER |
0x435553 JMP 434ca7 |
0x435558 VZEROUPPER |
0x43555b JMP 434946 |
0x435560 VZEROUPPER |
0x435563 JMP 434236 |
0x435568 VZEROUPPER |
0x43556b JMP 4345be |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○97.59 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○2.41 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | generate_chunk_kernel.f90:85-161 |
Module | exec |
nb instructions | 409 |
nb uops | 438 |
loop length | 1922 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 33 |
micro-operation queue | 73.00 cycles |
front end | 73.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 33.50 | 33.40 | 32.33 | 32.33 | 42.00 | 33.40 | 33.30 | 42.00 | 42.00 | 42.00 | 33.40 | 32.33 |
cycles | 33.50 | 49.33 | 32.33 | 32.33 | 42.00 | 33.40 | 33.30 | 42.00 | 42.00 | 42.00 | 33.40 | 32.33 |
Cycles executing div or sqrt instructions | 24.00 |
FE+BE cycles | 69.72-69.79 |
Stall cycles | 0.00 |
Front-end | 73.00 |
Dispatch | 49.33 |
DIV/SQRT | 24.00 |
Overall L1 | 73.00 |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 32% |
all | 9% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x180,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x128(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x2,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x18(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0xdc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%RSI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 435535 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1755> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 434236 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x456> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EBX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RBX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVSXD (%R8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV (%R11),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RBX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x2(%R9),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RDX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x3,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
AND $-0x8,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EBX,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R8D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R10,1),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%R10,%R13,1),%R13D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVGE %R10D,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA 0x4(%RBX),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13D,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KMOVB %EDX,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RSP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 435560 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1780> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 43553e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x175e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4345be <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x7de> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x100(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x120(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%R11),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RCX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (,%RCX,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x2(%R9),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x3(%R13),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R9,%RDX,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R10D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%R13),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%RBX,%R10,1),%R15D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EBX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %EBX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %EBX,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%R10),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV $0x1,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
KMOVB %R10D,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x108(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xd0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 435568 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1788> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R11D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 43552c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x174c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 434946 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xb66> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x8(%R12),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%RSI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA (,%R15,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x50(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R15,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV (%R10),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x2(%R9),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R9,%RDX,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%R10),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EBX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%R10),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R12,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%RBX,%R10,1),%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x108(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R10D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15D,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %EBX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %EBX,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%R10),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15D,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x1,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
KMOVB %R10D,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RSP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 435558 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1778> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R11D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 435547 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1767> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 434ca7 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xec7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x140(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%RSI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R10),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RBX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x48(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RBX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x80(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x2(%R9),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RDX,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R9,%R10,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x6,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
CMP %R8D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x5(%R15,%R10,1),%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x4(%R10),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMOVGE %R15D,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
KMOVB %EDX,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x108(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 435550 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1770> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x60(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 435491 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x16b1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x120(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NEG %RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RSI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R15,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R13,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (,%R11,8),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R9,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 434d46 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xf66> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4345f1 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x811> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 433ede <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xfe> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 434269 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x489> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 434979 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xb99> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 434ca7 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xec7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 434946 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xb66> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 434236 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x456> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 4345be <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x7de> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | generate_chunk_kernel.f90:85-161 |
Module | exec |
nb instructions | 409 |
nb uops | 438 |
loop length | 1922 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 33 |
micro-operation queue | 73.00 cycles |
front end | 73.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 33.50 | 33.40 | 32.33 | 32.33 | 42.00 | 33.40 | 33.30 | 42.00 | 42.00 | 42.00 | 33.40 | 32.33 |
cycles | 33.50 | 49.33 | 32.33 | 32.33 | 42.00 | 33.40 | 33.30 | 42.00 | 42.00 | 42.00 | 33.40 | 32.33 |
Cycles executing div or sqrt instructions | 24.00 |
FE+BE cycles | 69.72-69.79 |
Stall cycles | 0.00 |
Front-end | 73.00 |
Dispatch | 49.33 |
DIV/SQRT | 24.00 |
Overall L1 | 73.00 |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 32% |
all | 9% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x180,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x128(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x2,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x18(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0xdc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%RSI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 435535 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1755> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 434236 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x456> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EBX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RBX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVSXD (%R8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV (%R11),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RBX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x2(%R9),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RDX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x3,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
AND $-0x8,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EBX,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R8D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R10,1),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%R10,%R13,1),%R13D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVGE %R10D,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA 0x4(%RBX),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13D,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KMOVB %EDX,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RSP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 435560 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1780> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 43553e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x175e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4345be <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x7de> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x100(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x120(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%R11),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RCX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (,%RCX,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x2(%R9),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x3(%R13),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R9,%RDX,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R10D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%R13),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%RBX,%R10,1),%R15D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EBX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %EBX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %EBX,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%R10),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV $0x1,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
KMOVB %R10D,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x108(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xd0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 435568 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1788> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R11D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 43552c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x174c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 434946 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xb66> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x8(%R12),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%RSI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA (,%R15,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x50(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R15,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV (%R10),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x2(%R9),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R9,%RDX,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%R10),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EBX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%R10),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R12,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%RBX,%R10,1),%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x108(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R10D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15D,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %EBX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %EBX,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%R10),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15D,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x1,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
KMOVB %R10D,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RSP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 435558 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1778> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R11D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 435547 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1767> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 434ca7 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xec7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x140(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%RSI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R10),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RBX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x48(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RBX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x80(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x2(%R9),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RDX,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R9,%R10,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x6,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
CMP %R8D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x5(%R15,%R10,1),%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x4(%R10),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMOVGE %R15D,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
KMOVB %EDX,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x108(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 435550 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x1770> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x60(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 435491 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x16b1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x120(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NEG %RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RSI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R15,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R13,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (,%R11,8),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R9,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 434d46 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xf66> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4345f1 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x811> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 433ede <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xfe> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 434269 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x489> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 434979 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xb99> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 434ca7 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xec7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 434946 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0xb66> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 434236 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x456> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 4345be <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0+0x7de> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0.lto_priv.0– | 0.04 | 0.03 |
▼Loop 228 - generate_chunk_kernel.f90:119-161 - exec– | 0 | 0 |
▼Loop 229 - generate_chunk_kernel.f90:127-161 - exec– | 0 | 0 |
○Loop 230 - generate_chunk_kernel.f90:129-161 - exec | 0.01 | 0.01 |
▼Loop 235 - generate_chunk_kernel.f90:96-98 - exec– | 0 | 0 |
○Loop 236 - generate_chunk_kernel.f90:98-98 - exec | 0.01 | 0.01 |
▼Loop 233 - generate_chunk_kernel.f90:104-106 - exec– | 0 | 0 |
○Loop 234 - generate_chunk_kernel.f90:106-106 - exec | 0.01 | 0.01 |
▼Loop 231 - generate_chunk_kernel.f90:112-114 - exec– | 0 | 0 |
○Loop 232 - generate_chunk_kernel.f90:114-114 - exec | 0.01 | 0.01 |
▼Loop 237 - generate_chunk_kernel.f90:88-90 - exec– | 0 | 0 |
○Loop 238 - generate_chunk_kernel.f90:90-90 - exec | 0.01 | 0.01 |