Loop Id: 179 | Module: exec | Source: advec_mom_kernel.f90:81-241 [...] | Coverage: 0.02% |
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Loop Id: 179 | Module: exec | Source: advec_mom_kernel.f90:81-241 [...] | Coverage: 0.02% |
---|
0x4348c0 MOV 0x138(%RSP),%RCX |
0x4348c8 MOV 0x58(%RSP),%R9 |
0x4348cd ADD %RCX,%R9 |
0x4348d0 MOV 0x168(%RSP),%RAX |
0x4348d8 MOV 0x98(%RSP),%RSI |
0x4348e0 ADD %RAX,%RSI |
0x4348e3 ADD %RCX,0x20(%RSP) |
0x4348e8 ADD %RAX,0x28(%RSP) |
0x4348ed MOV 0x1e0(%RSP),%RCX |
0x4348f5 CMP 0x30(%RSP),%RCX |
0x4348fa LEA 0x1(%RCX),%RCX |
0x4348fe MOV 0x38(%RSP),%RDI |
0x434903 JE 434780 |
0x434909 CMPQ $0,0x50(%RSP) |
0x43490f MOV %RSI,0x98(%RSP) |
0x434917 MOV %R9,0x58(%RSP) |
0x43491c MOV %RCX,0x1e0(%RSP) |
0x434924 JE 434e00 |
0x43492a MOV 0x70(%RSP),%RAX |
0x43492f LEA -0x1(%RAX,%RCX,1),%R8 |
0x434934 MOV %R8,%R10 |
0x434937 SUB %RDX,%R10 |
0x43493a MOV 0x68(%RSP),%RAX |
0x43493f LEA (%RAX,%RCX,1),%R15D |
0x434943 LEA 0x1(%RAX,%RCX,1),%EBX |
0x434947 MOV %EBX,0x78(%RSP) |
0x43494b VPBROADCASTD %EBX,%ZMM20 |
0x434951 LEA -0x2(%RAX,%RCX,1),%EAX |
0x434955 MOV %EAX,0x80(%RSP) |
0x43495c VPBROADCASTD %EAX,%ZMM21 |
0x434962 VPBROADCASTD %R15D,%ZMM22 |
0x434968 VPBROADCASTD %R8D,%ZMM23 |
0x43496e XOR %EBX,%EBX |
0x434970 MOV 0x110(%RSP),%RCX |
0x434978 JMP 434b02 |
(181) 0x434980 VCMPPD $0x1,%ZMM31,%ZMM16,%K2 |
(181) 0x434987 VCMPPD $0x1,%ZMM30,%ZMM16,%K3 |
(181) 0x43498e VPBLENDMD %ZMM22,%ZMM21,%ZMM5{%K1} |
(181) 0x434994 MOV 0x90(%RSP),%RAX |
(181) 0x43499c VMOVSD (%RAX,%R10,8),%XMM8 |
(181) 0x4349a2 VANDPD %ZMM11,%ZMM4,%ZMM4 |
(181) 0x4349a8 VANDPD %ZMM11,%ZMM14,%ZMM13 |
(181) 0x4349ae VANDPD %ZMM11,%ZMM9,%ZMM14 |
(181) 0x4349b4 VANDPD %ZMM11,%ZMM7,%ZMM18 |
(181) 0x4349ba VBROADCASTSD 0xd1d54(%RIP),%ZMM0 |
(181) 0x4349c4 VSUBPD %ZMM28,%ZMM0,%ZMM19 |
(181) 0x4349ca VSUBPD %ZMM29,%ZMM0,%ZMM10 |
(181) 0x4349d0 VMULPD %ZMM10,%ZMM18,%ZMM10 |
(181) 0x4349d6 VMULPD %ZMM19,%ZMM14,%ZMM19 |
(181) 0x4349dc VMOVSD 0xcfbfc(%RIP),%XMM0 |
(181) 0x4349e4 VDIVSD %XMM8,%XMM0,%XMM0 |
(181) 0x4349e9 VBROADCASTSD %XMM0,%ZMM0 |
(181) 0x4349ef VMINPD %ZMM14,%ZMM13,%ZMM17 |
(181) 0x4349f5 VFMADD213PD %ZMM13,%ZMM28,%ZMM13 |
(181) 0x4349fb VMINPD %ZMM18,%ZMM4,%ZMM14 |
(181) 0x434a01 VFMADD213PD %ZMM4,%ZMM29,%ZMM4 |
(181) 0x434a07 VEXTRACTI64X4 $0x1,%ZMM5,%YMM18 |
(181) 0x434a0e VPMOVSXDQ %YMM5,%ZMM5 |
(181) 0x434a14 VPMOVSXDQ %YMM18,%ZMM18 |
(181) 0x434a1a VPSUBQ %ZMM1,%ZMM18,%ZMM18 |
(181) 0x434a20 VPSUBQ %ZMM1,%ZMM5,%ZMM5 |
(181) 0x434a26 VXORPD %XMM6,%XMM6,%XMM6 |
(181) 0x434a2a VGATHERQPD (%RAX,%ZMM5,8),%ZMM6{%K3} |
(181) 0x434a31 VXORPD %XMM5,%XMM5,%XMM5 |
(181) 0x434a35 VGATHERQPD (%RAX,%ZMM18,8),%ZMM5{%K2} |
(181) 0x434a3c VDIVPD %ZMM6,%ZMM13,%ZMM6 |
(181) 0x434a42 VDIVPD %ZMM5,%ZMM4,%ZMM4 |
(181) 0x434a48 VFMADD231PD %ZMM19,%ZMM0,%ZMM6 |
(181) 0x434a4e VFMADD231PD %ZMM10,%ZMM0,%ZMM4 |
(181) 0x434a54 VMULSD 0xd1ccc(%RIP),%XMM8,%XMM0 |
(181) 0x434a5c VBROADCASTSD %XMM0,%ZMM0 |
(181) 0x434a62 VMULPD %ZMM4,%ZMM0,%ZMM4 |
(181) 0x434a68 VMULPD %ZMM6,%ZMM0,%ZMM0 |
(181) 0x434a6e VMINPD %ZMM14,%ZMM4,%ZMM14 |
(181) 0x434a74 VMINPD %ZMM17,%ZMM0,%ZMM13 |
(181) 0x434a7a VFPCLASSPD $0x56,%ZMM9,%K1 |
(181) 0x434a81 VFPCLASSPD $0x56,%ZMM7,%K2 |
(181) 0x434a88 VBROADCASTSD 0xd1c8e(%RIP),%ZMM0 |
(181) 0x434a92 VXORPD %ZMM0,%ZMM14,%ZMM14{%K2} |
(181) 0x434a98 VXORPD %ZMM0,%ZMM13,%ZMM13{%K1} |
(181) 0x434a9e VCMPPD $0x1,%ZMM30,%ZMM16,%K1 |
(181) 0x434aa5 VCMPPD $0x1,%ZMM31,%ZMM16,%K2 |
(181) 0x434aac VMOVAPD %ZMM14,%ZMM0{%K2}{z} |
(181) 0x434ab2 VMOVAPD %ZMM13,%ZMM4{%K1}{z} |
(181) 0x434ab8 VBROADCASTSD 0xcfb1e(%RIP),%ZMM6 |
(181) 0x434ac2 VSUBPD %ZMM29,%ZMM6,%ZMM5 |
(181) 0x434ac8 VSUBPD %ZMM28,%ZMM6,%ZMM6 |
(181) 0x434ace VFMADD213PD %ZMM26,%ZMM4,%ZMM6 |
(181) 0x434ad4 VFMADD213PD %ZMM27,%ZMM0,%ZMM5 |
(181) 0x434ada VMULPD %ZMM25,%ZMM5,%ZMM0 |
(181) 0x434ae0 VMULPD %ZMM24,%ZMM6,%ZMM4 |
(181) 0x434ae6 VMOVUPD %ZMM4,(%R9,%RBX,8) |
(181) 0x434aed VMOVUPD %ZMM0,0x40(%R9,%RBX,8) |
(181) 0x434af5 ADD $0x10,%RBX |
(181) 0x434af9 CMP %RCX,%RBX |
(181) 0x434afc JG 434d80 |
(181) 0x434b02 LEA (%RDI,%RBX,1),%RAX |
(181) 0x434b06 VMOVUPD (%RSI,%RBX,8),%ZMM24 |
(181) 0x434b0d VMOVUPD 0x40(%RSI,%RBX,8),%ZMM25 |
(181) 0x434b15 VFPCLASSPD $0x50,%ZMM24,%K0 |
(181) 0x434b1c VFPCLASSPD $0x50,%ZMM25,%K1 |
(181) 0x434b23 KUNPCKBW %K0,%K1,%K1 |
(181) 0x434b27 VPBLENDMD %ZMM22,%ZMM23,%ZMM4{%K1} |
(181) 0x434b2d VEXTRACTI64X4 $0x1,%ZMM4,%YMM7 |
(181) 0x434b34 VPMOVSXDQ %YMM7,%ZMM7 |
(181) 0x434b3a VPSUBQ %ZMM1,%ZMM7,%ZMM9 |
(181) 0x434b40 VPXOR %XMM7,%XMM7,%XMM7 |
(181) 0x434b44 VPMULLQ %ZMM9,%ZMM2,%ZMM7 |
(181) 0x434b4a VPMOVSXDQ %YMM4,%ZMM4 |
(181) 0x434b50 VPSUBQ %ZMM1,%ZMM4,%ZMM4 |
(181) 0x434b56 VPXOR %XMM13,%XMM13,%XMM13 |
(181) 0x434b5b VPMULLQ %ZMM4,%ZMM2,%ZMM13 |
(181) 0x434b61 VPBROADCASTQ %RAX,%ZMM14 |
(181) 0x434b67 VPSUBQ 0x2c0(%RSP),%ZMM14,%ZMM14 |
(181) 0x434b6f VPSLLQ $0x3,%ZMM14,%ZMM14 |
(181) 0x434b76 VPADDQ 0xd2580(%RIP),%ZMM14,%ZMM26 |
(181) 0x434b80 VPADDQ %ZMM26,%ZMM12,%ZMM27 |
(181) 0x434b86 VPADDQ %ZMM13,%ZMM27,%ZMM13 |
(181) 0x434b8c VXORPD %XMM28,%XMM28,%XMM28 |
(181) 0x434b92 KXNORW %K0,%K0,%K2 |
(181) 0x434b96 VGATHERQPD (,%ZMM13,1),%ZMM28{%K2} |
(181) 0x434ba1 VPADDQ 0xd2515(%RIP),%ZMM14,%ZMM13 |
(181) 0x434bab VPADDQ %ZMM13,%ZMM12,%ZMM14 |
(181) 0x434bb1 VPADDQ %ZMM7,%ZMM14,%ZMM14 |
(181) 0x434bb7 VPXOR %XMM7,%XMM7,%XMM7 |
(181) 0x434bbb KXNORW %K0,%K0,%K2 |
(181) 0x434bbf VGATHERQPD (,%ZMM14,1),%ZMM7{%K2} |
(181) 0x434bca VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
(181) 0x434bd0 VPADDQ %ZMM26,%ZMM15,%ZMM14 |
(181) 0x434bd6 VPADDQ %ZMM4,%ZMM14,%ZMM4 |
(181) 0x434bdc VPXORD %XMM26,%XMM26,%XMM26 |
(181) 0x434be2 KXNORW %K0,%K0,%K2 |
(181) 0x434be6 VGATHERQPD (,%ZMM4,1),%ZMM26{%K2} |
(181) 0x434bf1 VPXOR %XMM4,%XMM4,%XMM4 |
(181) 0x434bf5 VPMULLQ %ZMM9,%ZMM3,%ZMM4 |
(181) 0x434bfb VPADDQ %ZMM13,%ZMM15,%ZMM9 |
(181) 0x434c01 VPADDQ %ZMM4,%ZMM9,%ZMM4 |
(181) 0x434c07 VPXORD %XMM27,%XMM27,%XMM27 |
(181) 0x434c0d KXNORW %K0,%K0,%K2 |
(181) 0x434c11 VGATHERQPD (,%ZMM4,1),%ZMM27{%K2} |
(181) 0x434c1c VPBLENDMD %ZMM20,%ZMM21,%ZMM4{%K1} |
(181) 0x434c22 VEXTRACTI64X4 $0x1,%ZMM4,%YMM13 |
(181) 0x434c29 VPMOVSXDQ %YMM13,%ZMM13 |
(181) 0x434c2f VPMOVSXDQ %YMM4,%ZMM4 |
(181) 0x434c35 VPSUBQ %ZMM1,%ZMM4,%ZMM4 |
(181) 0x434c3b VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
(181) 0x434c41 VPADDQ %ZMM4,%ZMM14,%ZMM4 |
(181) 0x434c47 VXORPD %XMM30,%XMM30,%XMM30 |
(181) 0x434c4d KXNORW %K0,%K0,%K2 |
(181) 0x434c51 VGATHERQPD (,%ZMM4,1),%ZMM30{%K2} |
(181) 0x434c5c VPSUBQ %ZMM1,%ZMM13,%ZMM4 |
(181) 0x434c62 VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
(181) 0x434c68 VPADDQ %ZMM4,%ZMM9,%ZMM4 |
(181) 0x434c6e VXORPD %XMM31,%XMM31,%XMM31 |
(181) 0x434c74 KXNORW %K0,%K0,%K2 |
(181) 0x434c78 VGATHERQPD (,%ZMM4,1),%ZMM31{%K2} |
(181) 0x434c83 VPBLENDMD %ZMM23,%ZMM22,%ZMM4{%K1} |
(181) 0x434c89 VANDPD %ZMM11,%ZMM24,%ZMM29 |
(181) 0x434c8f VANDPD %ZMM11,%ZMM25,%ZMM5 |
(181) 0x434c95 VPXOR %XMM13,%XMM13,%XMM13 |
(181) 0x434c9a VDIVPD %ZMM28,%ZMM29,%ZMM28 |
(181) 0x434ca0 VEXTRACTI64X4 $0x1,%ZMM4,%YMM29 |
(181) 0x434ca7 VPMOVSXDQ %YMM29,%ZMM29 |
(181) 0x434cad VPMOVSXDQ %YMM4,%ZMM4 |
(181) 0x434cb3 VPSUBQ %ZMM1,%ZMM4,%ZMM4 |
(181) 0x434cb9 VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
(181) 0x434cbf VPADDQ %ZMM4,%ZMM14,%ZMM4 |
(181) 0x434cc5 VXORPD %XMM8,%XMM8,%XMM8 |
(181) 0x434cca KXNORW %K0,%K0,%K2 |
(181) 0x434cce VGATHERQPD (,%ZMM4,1),%ZMM8{%K2} |
(181) 0x434cd9 VPSUBQ %ZMM1,%ZMM29,%ZMM4 |
(181) 0x434cdf VPMULLQ %ZMM4,%ZMM3,%ZMM4 |
(181) 0x434ce5 VPADDQ %ZMM4,%ZMM9,%ZMM4 |
(181) 0x434ceb VPXOR %XMM9,%XMM9,%XMM9 |
(181) 0x434cf0 KXNORW %K0,%K0,%K2 |
(181) 0x434cf4 VGATHERQPD (,%ZMM4,1),%ZMM9{%K2} |
(181) 0x434cff VDIVPD %ZMM7,%ZMM5,%ZMM29 |
(181) 0x434d05 VSUBPD %ZMM31,%ZMM27,%ZMM4 |
(181) 0x434d0b VSUBPD %ZMM30,%ZMM26,%ZMM14 |
(181) 0x434d11 VSUBPD %ZMM27,%ZMM9,%ZMM7 |
(181) 0x434d17 VSUBPD %ZMM26,%ZMM8,%ZMM9 |
(181) 0x434d1d VMULPD %ZMM14,%ZMM9,%ZMM30 |
(181) 0x434d23 VMULPD %ZMM4,%ZMM7,%ZMM31 |
(181) 0x434d29 VCMPPD $0x1,%ZMM31,%ZMM13,%K0 |
(181) 0x434d30 VCMPPD $0x1,%ZMM30,%ZMM13,%K2 |
(181) 0x434d37 KORTESTB %K0,%K2 |
(181) 0x434d3b JNE 434980 |
(181) 0x434d41 VXORPD %XMM14,%XMM14,%XMM14 |
(181) 0x434d46 JMP 434a9e |
0x434d80 MOV %R10,0x18(%RSP) |
0x434d85 MOV 0x50(%RSP),%RCX |
0x434d8a MOV %RCX,%RAX |
0x434d8d CMP %RCX,0x118(%RSP) |
0x434d95 VMOVDDUP 0xcf66b(%RIP),%XMM8 |
0x434d9d VXORPD %XMM10,%XMM10,%XMM10 |
0x434da2 VMOVAPD 0x230(%RSP),%XMM14 |
0x434dab VMOVSD 0xd1963(%RIP),%XMM17 |
0x434db5 VMOVDDUP 0xd1961(%RIP),%XMM18 |
0x434dbf VMOVSD 0xcf817(%RIP),%XMM19 |
0x434dc9 JNE 434e33 |
0x434dcb JMP 4348c0 |
0x434e00 MOV 0x70(%RSP),%RAX |
0x434e05 LEA -0x1(%RAX,%RCX,1),%R8 |
0x434e0a MOV %R8,%RAX |
0x434e0d SUB %RDX,%RAX |
0x434e10 MOV %RAX,0x18(%RSP) |
0x434e15 MOV 0x68(%RSP),%RAX |
0x434e1a LEA (%RAX,%RCX,1),%R15D |
0x434e1e LEA 0x1(%RAX,%RCX,1),%ESI |
0x434e22 MOV %ESI,0x78(%RSP) |
0x434e26 LEA -0x2(%RAX,%RCX,1),%EAX |
0x434e2a MOV %EAX,0x80(%RSP) |
0x434e31 XOR %EAX,%EAX |
0x434e33 MOV 0x150(%RSP),%RBX |
0x434e3b SUB %RAX,%RBX |
0x434e3e MOV 0x120(%RSP),%RCX |
0x434e46 LEA (%RCX,%RAX,1),%R10 |
0x434e4a MOV 0x20(%RSP),%RCX |
0x434e4f LEA (%RCX,%R10,8),%RSI |
0x434e53 ADD 0x128(%RSP),%RAX |
0x434e5b MOV 0x130(%RSP),%RCX |
0x434e63 LEA (%RCX,%RAX,8),%RDI |
0x434e67 MOV 0xe0(%RSP),%RCX |
0x434e6f LEA (%RCX,%RAX,8),%RCX |
0x434e73 MOV 0x28(%RSP),%RAX |
0x434e78 LEA (%RAX,%R10,8),%R10 |
0x434e7c XOR %EAX,%EAX |
0x434e7e VMOVSD 0xd18a0(%RIP),%XMM23 |
0x434e88 JMP 434ee3 |
(180) 0x434ec0 VSUBSD %XMM7,%XMM19,%XMM0 |
(180) 0x434ec6 VFMADD213SD %XMM21,%XMM9,%XMM0 |
(180) 0x434ecc VMULSD %XMM20,%XMM0,%XMM0 |
(180) 0x434ed2 VMOVSD %XMM0,(%RSI,%RAX,8) |
(180) 0x434ed7 INC %RAX |
(180) 0x434eda CMP %RAX,%RBX |
(180) 0x434edd JE 4348c0 |
(180) 0x434ee3 VMOVSD (%R10,%RAX,8),%XMM20 |
(180) 0x434eea VXORPD %XMM9,%XMM9,%XMM9 |
(180) 0x434eef VUCOMISD %XMM20,%XMM9 |
(180) 0x434ef5 MOV 0x80(%RSP),%R9D |
(180) 0x434efd CMOVA 0x78(%RSP),%R9D |
(180) 0x434f03 MOV %R8D,%R12D |
(180) 0x434f06 CMOVA %R15D,%R12D |
(180) 0x434f0a MOV %R15D,%R13D |
(180) 0x434f0d CMOVA %R8D,%R13D |
(180) 0x434f11 VANDPD %XMM8,%XMM20,%XMM0 |
(180) 0x434f17 MOVSXD %R12D,%R12 |
(180) 0x434f1a SUB %RDX,%R12 |
(180) 0x434f1d MOV 0x40(%RSP),%R14 |
(180) 0x434f22 IMUL %R12,%R14 |
(180) 0x434f26 ADD %RCX,%R14 |
(180) 0x434f29 VDIVSD (%R14,%RAX,8),%XMM0,%XMM7 |
(180) 0x434f2f IMUL %R11,%R12 |
(180) 0x434f33 ADD %RDI,%R12 |
(180) 0x434f36 VMOVSD (%R12,%RAX,8),%XMM21 |
(180) 0x434f3d MOVSXD %R9D,%R9 |
(180) 0x434f40 SUB %RDX,%R9 |
(180) 0x434f43 IMUL %R11,%R9 |
(180) 0x434f47 ADD %RDI,%R9 |
(180) 0x434f4a VSUBSD (%R9,%RAX,8),%XMM21,%XMM22 |
(180) 0x434f51 MOVSXD %R13D,%R9 |
(180) 0x434f54 SUB %RDX,%R9 |
(180) 0x434f57 IMUL %R11,%R9 |
(180) 0x434f5b ADD %RDI,%R9 |
(180) 0x434f5e VMOVSD (%R9,%RAX,8),%XMM0 |
(180) 0x434f64 VSUBSD %XMM21,%XMM0,%XMM13 |
(180) 0x434f6a VMULSD %XMM22,%XMM13,%XMM0 |
(180) 0x434f70 VUCOMISD %XMM9,%XMM0 |
(180) 0x434f75 JBE 434ec0 |
(180) 0x434f7b VUCOMISD %XMM20,%XMM10 |
(180) 0x434f81 MOV 0x80(%RSP),%R9D |
(180) 0x434f89 CMOVA %R15D,%R9D |
(180) 0x434f8d MOV 0x90(%RSP),%R14 |
(180) 0x434f95 MOV 0x18(%RSP),%R12 |
(180) 0x434f9a VMOVSD (%R14,%R12,8),%XMM0 |
(180) 0x434fa0 VANDPD %XMM14,%XMM22,%XMM4 |
(180) 0x434fa6 VANDPD %XMM14,%XMM13,%XMM5 |
(180) 0x434fab VSUBSD %XMM7,%XMM17,%XMM6 |
(180) 0x434fb1 VMULSD %XMM6,%XMM5,%XMM6 |
(180) 0x434fb5 VDIVSD %XMM0,%XMM6,%XMM6 |
(180) 0x434fb9 VMINSD %XMM5,%XMM4,%XMM5 |
(180) 0x434fbd VFMADD213SD %XMM4,%XMM7,%XMM4 |
(180) 0x434fc2 MOVSXD %R9D,%R9 |
(180) 0x434fc5 SUB %RDX,%R9 |
(180) 0x434fc8 VDIVSD (%R14,%R9,8),%XMM4,%XMM4 |
(180) 0x434fce VADDSD %XMM6,%XMM4,%XMM4 |
(180) 0x434fd2 VMULSD %XMM23,%XMM0,%XMM0 |
(180) 0x434fd8 VMULSD %XMM4,%XMM0,%XMM0 |
(180) 0x434fdc VMINSD %XMM5,%XMM0,%XMM9 |
(180) 0x434fe0 VXORPD %XMM18,%XMM9,%XMM0 |
(180) 0x434fe6 VCMPSD $0x2,%XMM10,%XMM13,%K1 |
(180) 0x434fed VMOVSD %XMM0,%XMM9,%XMM9{%K1} |
(180) 0x434ff3 JMP 434ec0 |
/scratch_na/users/xoserete/qaas_runs/171-415-7919/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 81 - 241 |
-------------------------------------------------------------------------------- |
81: IF(mom_sweep.EQ.1)THEN ! x 1 |
[...] |
215: IF(node_flux(j,k).LT.0.0)THEN |
[...] |
227: sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor)) |
228: width=celldy(k) |
229: vdiffuw=vel1(j,donor)-vel1(j,upwind) |
230: vdiffdw=vel1(j,downwind)-vel1(j,donor) |
231: limiter=0.0 |
232: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
233: auw=ABS(vdiffuw) |
234: adw=ABS(vdiffdw) |
235: wind=1.0_8 |
236: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
237: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw) |
238: ENDIF |
239: advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter |
240: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
241: ENDDO |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.96 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 12.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.28 |
Bottlenecks | micro-operation queue, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:241-241 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.83 |
CQA cycles if no scalar integer | 4.33 |
CQA cycles if FP arith vectorized | 12.83 |
CQA cycles if fully vectorized | 1.07 |
Front-end cycles | 12.83 |
DIV/SQRT cycles | 5.10 |
P0 cycles | 8.60 |
P1 cycles | 10.00 |
P2 cycles | 10.00 |
P3 cycles | 5.50 |
P4 cycles | 5.00 |
P5 cycles | 4.90 |
P6 cycles | 5.50 |
P7 cycles | 5.50 |
P8 cycles | 5.50 |
P9 cycles | 5.00 |
P10 cycles | 10.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 13.31 |
Stall cycles (UFS) | 0.00 |
Nb insns | 75.00 |
Nb uops | 77.00 |
Nb loads | 30.00 |
Nb stores | 11.00 |
Nb stack references | 23.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.94 |
Bytes prefetched | 0.00 |
Bytes loaded | 248.00 |
Bytes stored | 72.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 6.06 |
Vectorization ratio load | 6.67 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 11.11 |
Vector-efficiency ratio all | 11.55 |
Vector-efficiency ratio load | 13.33 |
Vector-efficiency ratio store | 10.23 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 10.42 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.96 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 12.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.28 |
Bottlenecks | micro-operation queue, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:241-241 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.83 |
CQA cycles if no scalar integer | 4.33 |
CQA cycles if FP arith vectorized | 12.83 |
CQA cycles if fully vectorized | 1.07 |
Front-end cycles | 12.83 |
DIV/SQRT cycles | 5.10 |
P0 cycles | 8.60 |
P1 cycles | 10.00 |
P2 cycles | 10.00 |
P3 cycles | 5.50 |
P4 cycles | 5.00 |
P5 cycles | 4.90 |
P6 cycles | 5.50 |
P7 cycles | 5.50 |
P8 cycles | 5.50 |
P9 cycles | 5.00 |
P10 cycles | 10.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 13.31 |
Stall cycles (UFS) | 0.00 |
Nb insns | 75.00 |
Nb uops | 77.00 |
Nb loads | 30.00 |
Nb stores | 11.00 |
Nb stack references | 23.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.94 |
Bytes prefetched | 0.00 |
Bytes loaded | 248.00 |
Bytes stored | 72.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 6.06 |
Vectorization ratio load | 6.67 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 11.11 |
Vector-efficiency ratio all | 11.55 |
Vector-efficiency ratio load | 13.33 |
Vector-efficiency ratio store | 10.23 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 10.42 |
Path / |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-241 |
Module | exec |
nb instructions | 75 |
nb uops | 77 |
loop length | 407 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 7 |
used ymm registers | 0 |
used zmm registers | 4 |
nb stack references | 23 |
micro-operation queue | 12.83 cycles |
front end | 12.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 6.00 | 10.00 | 10.00 | 5.50 | 5.00 | 4.90 | 5.50 | 5.50 | 5.50 | 5.00 | 10.00 |
cycles | 5.10 | 8.60 | 10.00 | 10.00 | 5.50 | 5.00 | 4.90 | 5.50 | 5.50 | 5.50 | 5.00 | 10.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 13.31 |
Stall cycles | 0.00 |
Front-end | 12.83 |
Dispatch | 10.00 |
Overall L1 | 12.83 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 28% |
load | 16% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 6% |
load | 6% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 10% |
load | 12% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 16% |
load | 14% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 11% |
load | 13% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x138(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x168(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RCX,0x20(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
ADD %RAX,0x28(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV 0x1e0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP 0x30(%RSP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x1(%RCX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x38(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 434780 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2aa0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMPQ $0,0x50(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RSI,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x1e0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 434e00 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3120> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%RAX,%RCX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x68(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%RCX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RAX,%RCX,1),%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTD %EBX,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA -0x2(%RAX,%RCX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EAX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTD %EAX,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBROADCASTD %R15D,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBROADCASTD %R8D,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x110(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 434b02 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2e22> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RCX,0x118(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVDDUP 0xcf66b(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM10,%XMM10,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVAPD 0x230(%RSP),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVSD 0xd1963(%RIP),%XMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0xd1961(%RIP),%XMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xcf817(%RIP),%XMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 434e33 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3153> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4348c0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2be0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%RAX,%RCX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%RCX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RAX,%RCX,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %ESI,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%RAX,%RCX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EAX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x150(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x120(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%RAX,1),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x20(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%R10,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD 0x128(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x130(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%RAX,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xe0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%RAX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x28(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R10,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xd18a0(%RIP),%XMM23 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 434ee3 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3203> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-241 |
Module | exec |
nb instructions | 75 |
nb uops | 77 |
loop length | 407 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 7 |
used ymm registers | 0 |
used zmm registers | 4 |
nb stack references | 23 |
micro-operation queue | 12.83 cycles |
front end | 12.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 6.00 | 10.00 | 10.00 | 5.50 | 5.00 | 4.90 | 5.50 | 5.50 | 5.50 | 5.00 | 10.00 |
cycles | 5.10 | 8.60 | 10.00 | 10.00 | 5.50 | 5.00 | 4.90 | 5.50 | 5.50 | 5.50 | 5.00 | 10.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 13.31 |
Stall cycles | 0.00 |
Front-end | 12.83 |
Dispatch | 10.00 |
Overall L1 | 12.83 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 28% |
load | 16% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 6% |
load | 6% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 10% |
load | 12% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 16% |
load | 14% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 11% |
load | 13% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x138(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x168(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RCX,0x20(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
ADD %RAX,0x28(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV 0x1e0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP 0x30(%RSP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x1(%RCX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x38(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 434780 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2aa0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMPQ $0,0x50(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RSI,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x1e0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 434e00 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3120> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%RAX,%RCX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x68(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%RCX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RAX,%RCX,1),%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTD %EBX,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA -0x2(%RAX,%RCX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EAX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTD %EAX,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBROADCASTD %R15D,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBROADCASTD %R8D,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x110(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 434b02 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2e22> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RCX,0x118(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVDDUP 0xcf66b(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM10,%XMM10,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVAPD 0x230(%RSP),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVSD 0xd1963(%RIP),%XMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0xd1961(%RIP),%XMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xcf817(%RIP),%XMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 434e33 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3153> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4348c0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2be0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%RAX,%RCX,1),%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%RCX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RAX,%RCX,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %ESI,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%RAX,%RCX,1),%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EAX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x150(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x120(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%RAX,1),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x20(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%R10,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD 0x128(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x130(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%RAX,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xe0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%RAX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x28(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R10,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xd18a0(%RIP),%XMM23 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 434ee3 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3203> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |