Loop Id: 156 | Module: exec | Source: advec_mom_kernel.f90:184-184 | Coverage: 4.49% |
---|
Loop Id: 156 | Module: exec | Source: advec_mom_kernel.f90:184-184 | Coverage: 4.49% |
---|
0x43c46e VMOVUPD (%RSI,%RDX,1),%ZMM0 [5] |
0x43c475 VMOVUPD (%R9,%RDX,1),%ZMM7 [4] |
0x43c47c VFMSUB132PD (%R13,%RDX,1),%ZMM7,%ZMM0 [2] |
0x43c484 VADDPD (%RBX,%RDX,1),%ZMM0,%ZMM6 [3] |
0x43c48b VDIVPD (%R12,%RDX,1),%ZMM6,%ZMM4 [1] |
0x43c492 VMOVUPD %ZMM4,(%R13,%RDX,1) [2] |
0x43c49a VMOVUPD 0x40(%RSI,%RDX,1),%ZMM13 [5] |
0x43c4a2 VMOVUPD 0x40(%R9,%RDX,1),%ZMM9 [4] |
0x43c4aa VFMSUB132PD 0x40(%R13,%RDX,1),%ZMM9,%ZMM13 [2] |
0x43c4b2 VADDPD 0x40(%RBX,%RDX,1),%ZMM13,%ZMM12 [3] |
0x43c4ba VDIVPD 0x40(%R12,%RDX,1),%ZMM12,%ZMM14 [1] |
0x43c4c2 VMOVUPD %ZMM14,0x40(%R13,%RDX,1) [2] |
0x43c4ca VMOVUPD 0x80(%RSI,%RDX,1),%ZMM10 [5] |
0x43c4d2 VMOVUPD 0x80(%R9,%RDX,1),%ZMM8 [4] |
0x43c4da VFMSUB132PD 0x80(%R13,%RDX,1),%ZMM8,%ZMM10 [2] |
0x43c4e2 VADDPD 0x80(%RBX,%RDX,1),%ZMM10,%ZMM11 [3] |
0x43c4ea VDIVPD 0x80(%R12,%RDX,1),%ZMM11,%ZMM1 [1] |
0x43c4f2 VMOVUPD %ZMM1,0x80(%R13,%RDX,1) [2] |
0x43c4fa VMOVUPD 0xc0(%RSI,%RDX,1),%ZMM15 [5] |
0x43c502 VMOVUPD 0xc0(%R9,%RDX,1),%ZMM3 [4] |
0x43c50a VFMSUB132PD 0xc0(%R13,%RDX,1),%ZMM3,%ZMM15 [2] |
0x43c512 VADDPD 0xc0(%RBX,%RDX,1),%ZMM15,%ZMM5 [3] |
0x43c51a VDIVPD 0xc0(%R12,%RDX,1),%ZMM5,%ZMM2 [1] |
0x43c522 VMOVUPD %ZMM2,0xc0(%R13,%RDX,1) [2] |
0x43c52a ADD $0x100,%RDX |
0x43c531 CMP %RDX,0x268(%RSP) [6] |
0x43c539 JNE 43c46e |
/scratch_na/users/xoserete/qaas_runs/171-215-0463/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 184 - 184 |
-------------------------------------------------------------------------------- |
184: vel1 (j,k)=(vel1 (j,k)*node_mass_pre(j,k)+mom_flux(j-1,k)-mom_flux(j,k))/node_mass_post(j,k) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 6.40 |
Bottlenecks | P0, |
Function | advec_mom_kernel._omp_fn.0 |
Source | advec_mom_kernel.f90:184-184 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 64.00 |
CQA cycles if no scalar integer | 64.00 |
CQA cycles if FP arith vectorized | 64.00 |
CQA cycles if fully vectorized | 64.00 |
Front-end cycles | 7.67 |
DIV/SQRT cycles | 10.00 |
P0 cycles | 4.00 |
P1 cycles | 7.00 |
P2 cycles | 7.00 |
P3 cycles | 2.00 |
P4 cycles | 10.00 |
P5 cycles | 1.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 0.40 |
P10 cycles | 7.00 |
P11 cycles | 64.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 64.26 - 64.28 |
Stall cycles (UFS) | 55.90 - 55.92 |
Nb insns | 27.00 |
Nb uops | 38.00 |
Nb loads | 21.00 |
Nb stores | 4.00 |
Nb stack references | 1.00 |
FLOP/cycle | 2.00 |
Nb FLOP add-sub | 32.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 32.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.13 |
Bytes prefetched | 0.00 |
Bytes loaded | 1288.00 |
Bytes stored | 256.00 |
Stride 0 | 1.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 6.40 |
Bottlenecks | P0, |
Function | advec_mom_kernel._omp_fn.0 |
Source | advec_mom_kernel.f90:184-184 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 64.00 |
CQA cycles if no scalar integer | 64.00 |
CQA cycles if FP arith vectorized | 64.00 |
CQA cycles if fully vectorized | 64.00 |
Front-end cycles | 7.67 |
DIV/SQRT cycles | 10.00 |
P0 cycles | 4.00 |
P1 cycles | 7.00 |
P2 cycles | 7.00 |
P3 cycles | 2.00 |
P4 cycles | 10.00 |
P5 cycles | 1.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 0.40 |
P10 cycles | 7.00 |
P11 cycles | 64.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 64.26 - 64.28 |
Stall cycles (UFS) | 55.90 - 55.92 |
Nb insns | 27.00 |
Nb uops | 38.00 |
Nb loads | 21.00 |
Nb stores | 4.00 |
Nb stack references | 1.00 |
FLOP/cycle | 2.00 |
Nb FLOP add-sub | 32.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 32.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.13 |
Bytes prefetched | 0.00 |
Bytes loaded | 1288.00 |
Bytes stored | 256.00 |
Stride 0 | 1.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | NA |
Path / |
Function | advec_mom_kernel._omp_fn.0 |
Source file and lines | advec_mom_kernel.f90:184-184 |
Module | exec |
nb instructions | 27 |
nb uops | 38 |
loop length | 209 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 1 |
micro-operation queue | 7.67 cycles |
front end | 7.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 10.00 | 0.60 | 7.00 | 7.00 | 2.00 | 10.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.40 | 7.00 |
cycles | 10.00 | 4.00 | 7.00 | 7.00 | 2.00 | 10.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.40 | 7.00 |
Cycles executing div or sqrt instructions | 64.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 64.26-64.28 |
Stall cycles | 55.90-55.92 |
LB full (events) | 59.54-59.56 |
Front-end | 7.67 |
Dispatch | 10.00 |
DIV/SQRT | 64.00 |
Data deps. | 1.00 |
Overall L1 | 64.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%RSI,%RDX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD (%R9,%RDX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFMSUB132PD (%R13,%RDX,1),%ZMM7,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD (%RBX,%RDX,1),%ZMM0,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD (%R12,%RDX,1),%ZMM6,%ZMM4 | 4 | 2.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 22-24 | 16 |
VMOVUPD %ZMM4,(%R13,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%RSI,%RDX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x40(%R9,%RDX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFMSUB132PD 0x40(%R13,%RDX,1),%ZMM9,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x40(%RBX,%RDX,1),%ZMM13,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD 0x40(%R12,%RDX,1),%ZMM12,%ZMM14 | 4 | 2.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 22-24 | 16 |
VMOVUPD %ZMM14,0x40(%R13,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%RSI,%RDX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x80(%R9,%RDX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFMSUB132PD 0x80(%R13,%RDX,1),%ZMM8,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x80(%RBX,%RDX,1),%ZMM10,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD 0x80(%R12,%RDX,1),%ZMM11,%ZMM1 | 4 | 2.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 22-24 | 16 |
VMOVUPD %ZMM1,0x80(%R13,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%RSI,%RDX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0xc0(%R9,%RDX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFMSUB132PD 0xc0(%R13,%RDX,1),%ZMM3,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0xc0(%RBX,%RDX,1),%ZMM15,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD 0xc0(%R12,%RDX,1),%ZMM5,%ZMM2 | 4 | 2.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 22-24 | 16 |
VMOVUPD %ZMM2,0xc0(%R13,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x100,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RDX,0x268(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 43c46e <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x171e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | advec_mom_kernel._omp_fn.0 |
Source file and lines | advec_mom_kernel.f90:184-184 |
Module | exec |
nb instructions | 27 |
nb uops | 38 |
loop length | 209 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 1 |
micro-operation queue | 7.67 cycles |
front end | 7.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 10.00 | 0.60 | 7.00 | 7.00 | 2.00 | 10.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.40 | 7.00 |
cycles | 10.00 | 4.00 | 7.00 | 7.00 | 2.00 | 10.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.40 | 7.00 |
Cycles executing div or sqrt instructions | 64.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 64.26-64.28 |
Stall cycles | 55.90-55.92 |
LB full (events) | 59.54-59.56 |
Front-end | 7.67 |
Dispatch | 10.00 |
DIV/SQRT | 64.00 |
Data deps. | 1.00 |
Overall L1 | 64.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%RSI,%RDX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD (%R9,%RDX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFMSUB132PD (%R13,%RDX,1),%ZMM7,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD (%RBX,%RDX,1),%ZMM0,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD (%R12,%RDX,1),%ZMM6,%ZMM4 | 4 | 2.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 22-24 | 16 |
VMOVUPD %ZMM4,(%R13,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%RSI,%RDX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x40(%R9,%RDX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFMSUB132PD 0x40(%R13,%RDX,1),%ZMM9,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x40(%RBX,%RDX,1),%ZMM13,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD 0x40(%R12,%RDX,1),%ZMM12,%ZMM14 | 4 | 2.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 22-24 | 16 |
VMOVUPD %ZMM14,0x40(%R13,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%RSI,%RDX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x80(%R9,%RDX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFMSUB132PD 0x80(%R13,%RDX,1),%ZMM8,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x80(%RBX,%RDX,1),%ZMM10,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD 0x80(%R12,%RDX,1),%ZMM11,%ZMM1 | 4 | 2.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 22-24 | 16 |
VMOVUPD %ZMM1,0x80(%R13,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%RSI,%RDX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0xc0(%R9,%RDX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VFMSUB132PD 0xc0(%R13,%RDX,1),%ZMM3,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0xc0(%RBX,%RDX,1),%ZMM15,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
VDIVPD 0xc0(%R12,%RDX,1),%ZMM5,%ZMM2 | 4 | 2.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 22-24 | 16 |
VMOVUPD %ZMM2,0xc0(%R13,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x100,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RDX,0x268(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 43c46e <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x171e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |