Loop Id: 264 | Module: exec | Source: field_summary_kernel.f90:58-71 | Coverage: 0.29% |
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Loop Id: 264 | Module: exec | Source: field_summary_kernel.f90:58-71 | Coverage: 0.29% |
---|
0x436c40 VPADDQ %XMM4,%XMM15,%XMM16 |
0x436c46 VMOVQ %XMM16,%R15 |
0x436c4c SUB %RDX,%R15 |
0x436c4f VMOVUPD (%R12,%R15,8),%YMM16 [2] |
0x436c56 VMOVUPD 0x8(%R12,%R15,8),%YMM17 [2] |
0x436c61 VMOVUPD (%R11,%R15,8),%YMM18 [1] |
0x436c68 VMOVUPD 0x8(%R11,%R15,8),%YMM19 [1] |
0x436c73 VMOVUPD (%R8,%R15,8),%YMM20 [5] |
0x436c7a VMOVUPD 0x8(%R8,%R15,8),%YMM21 [5] |
0x436c85 VMOVUPD (%R9,%R15,8),%YMM22 [4] |
0x436c8c VMOVUPD 0x8(%R9,%R15,8),%YMM23 [4] |
0x436c97 VMOVUPD (%RBX,%R15,8),%YMM24 [7] |
0x436c9e VMULPD (%R14,%R15,8),%YMM24,%YMM25 [3] |
0x436ca5 VFMADD231PD (%RDI,%R15,8),%YMM25,%YMM12 [8] |
0x436cac VFMADD231PD (%RCX,%R15,8),%YMM24,%YMM14 [6] |
0x436cb3 VMULPD %YMM16,%YMM16,%YMM16 |
0x436cb9 VFMADD213PD %YMM16,%YMM18,%YMM18 |
0x436cbf VFMADD231PD %YMM17,%YMM17,%YMM18 |
0x436cc5 VFMADD231PD %YMM19,%YMM19,%YMM18 |
0x436ccb VFMADD213PD %YMM18,%YMM20,%YMM20 |
0x436cd1 VFMADD213PD %YMM20,%YMM22,%YMM22 |
0x436cd7 VFMADD231PD %YMM21,%YMM21,%YMM22 |
0x436cdd VFMADD231PD %YMM23,%YMM23,%YMM22 |
0x436ce3 VADDPD %YMM24,%YMM10,%YMM10 |
0x436ce9 VADDPD %YMM25,%YMM11,%YMM11 |
0x436cef VMULPD %YMM22,%YMM25,%YMM16 |
0x436cf5 VFMADD231PD %YMM8,%YMM16,%YMM13 |
0x436cfb VPADDQ %YMM9,%YMM15,%YMM15 |
0x436d00 ADD $0x4,%RSI |
0x436d04 CMP %R10,%RSI |
0x436d07 JB 436c40 |
/scratch_na/users/xoserete/qaas_runs/171-215-0463/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 58 - 71 |
-------------------------------------------------------------------------------- |
58: DO j=x_min,x_max |
59: vsqrd=0.0 |
60: DO kv=k,k+1 |
61: DO jv=j,j+1 |
62: vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2) |
63: ENDDO |
64: ENDDO |
65: cell_vol=volume(j,k) |
66: cell_mass=cell_vol*density0(j,k) |
67: vol=vol+cell_vol |
68: mass=mass+cell_mass |
69: ie=ie+cell_mass*energy0(j,k) |
70: ke=ke+cell_mass*0.5*vsqrd |
71: press=press+cell_vol*pressure(j,k) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.88 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | P1, |
Function | field_summary_kernel_.DIR.OMP.PARALLEL.2 |
Source | field_summary_kernel.f90:58-71 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 7.50 |
CQA cycles if no scalar integer | 7.50 |
CQA cycles if FP arith vectorized | 4.00 |
CQA cycles if fully vectorized | 3.75 |
Front-end cycles | 5.50 |
DIV/SQRT cycles | 7.00 |
P0 cycles | 7.50 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 0.00 |
P4 cycles | 4.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 4.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 4 |
FE+BE cycles (UFS) | 8.81 |
Stall cycles (UFS) | 2.89 |
Nb insns | 31.00 |
Nb uops | 30.00 |
Nb loads | 12.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 13.33 |
Nb FLOP add-sub | 8.00 |
Nb FLOP mul | 12.00 |
Nb FLOP fma | 40.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 51.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 384.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 8.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 96.30 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 47.69 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 43.75 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.88 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | P1, |
Function | field_summary_kernel_.DIR.OMP.PARALLEL.2 |
Source | field_summary_kernel.f90:58-71 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 7.50 |
CQA cycles if no scalar integer | 7.50 |
CQA cycles if FP arith vectorized | 4.00 |
CQA cycles if fully vectorized | 3.75 |
Front-end cycles | 5.50 |
DIV/SQRT cycles | 7.00 |
P0 cycles | 7.50 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 0.00 |
P4 cycles | 4.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 4.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 4 |
FE+BE cycles (UFS) | 8.81 |
Stall cycles (UFS) | 2.89 |
Nb insns | 31.00 |
Nb uops | 30.00 |
Nb loads | 12.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 13.33 |
Nb FLOP add-sub | 8.00 |
Nb FLOP mul | 12.00 |
Nb FLOP fma | 40.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 51.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 384.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 8.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 96.30 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 47.69 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 43.75 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | field_summary_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | field_summary_kernel.f90:58-71 |
Module | exec |
nb instructions | 31 |
nb uops | 30 |
loop length | 205 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 18 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.67 |
micro-operation queue | 5.50 cycles |
front end | 5.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 4.00 | 4.00 | 0.00 | 4.00 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 4.00 |
cycles | 7.00 | 7.50 | 4.00 | 4.00 | 0.00 | 4.00 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 4.00 |
FE+BE cycles | 8.81 |
Stall cycles | 2.89 |
LM full (events) | 3.56 |
Front-end | 5.50 |
Dispatch | 7.50 |
Data deps. | 4.00 |
Overall L1 | 7.50 |
all | 66% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 96% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 29% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 37% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 47% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 43% |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPADDQ %XMM4,%XMM15,%XMM16 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVQ %XMM16,%R15 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
SUB %RDX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVUPD (%R12,%R15,8),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x8(%R12,%R15,8),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%R11,%R15,8),%YMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x8(%R11,%R15,8),%YMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%R8,%R15,8),%YMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x8(%R8,%R15,8),%YMM21 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%R9,%R15,8),%YMM22 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x8(%R9,%R15,8),%YMM23 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%RBX,%R15,8),%YMM24 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMULPD (%R14,%R15,8),%YMM24,%YMM25 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD231PD (%RDI,%R15,8),%YMM25,%YMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD231PD (%RCX,%R15,8),%YMM24,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMULPD %YMM16,%YMM16,%YMM16 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD %YMM16,%YMM18,%YMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM17,%YMM17,%YMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM19,%YMM19,%YMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD %YMM18,%YMM20,%YMM20 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD %YMM20,%YMM22,%YMM22 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM21,%YMM21,%YMM22 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM23,%YMM23,%YMM22 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM24,%YMM10,%YMM10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM25,%YMM11,%YMM11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM22,%YMM25,%YMM16 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM8,%YMM16,%YMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPADDQ %YMM9,%YMM15,%YMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
ADD $0x4,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 436c40 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x430> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | field_summary_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | field_summary_kernel.f90:58-71 |
Module | exec |
nb instructions | 31 |
nb uops | 30 |
loop length | 205 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 18 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.67 |
micro-operation queue | 5.50 cycles |
front end | 5.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 4.00 | 4.00 | 0.00 | 4.00 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 4.00 |
cycles | 7.00 | 7.50 | 4.00 | 4.00 | 0.00 | 4.00 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 4.00 |
FE+BE cycles | 8.81 |
Stall cycles | 2.89 |
LM full (events) | 3.56 |
Front-end | 5.50 |
Dispatch | 7.50 |
Data deps. | 4.00 |
Overall L1 | 7.50 |
all | 66% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 96% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 29% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 37% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 47% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 43% |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPADDQ %XMM4,%XMM15,%XMM16 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVQ %XMM16,%R15 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
SUB %RDX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVUPD (%R12,%R15,8),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x8(%R12,%R15,8),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%R11,%R15,8),%YMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x8(%R11,%R15,8),%YMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%R8,%R15,8),%YMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x8(%R8,%R15,8),%YMM21 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%R9,%R15,8),%YMM22 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x8(%R9,%R15,8),%YMM23 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%RBX,%R15,8),%YMM24 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMULPD (%R14,%R15,8),%YMM24,%YMM25 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD231PD (%RDI,%R15,8),%YMM25,%YMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD231PD (%RCX,%R15,8),%YMM24,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMULPD %YMM16,%YMM16,%YMM16 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD %YMM16,%YMM18,%YMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM17,%YMM17,%YMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM19,%YMM19,%YMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD %YMM18,%YMM20,%YMM20 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD %YMM20,%YMM22,%YMM22 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM21,%YMM21,%YMM22 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM23,%YMM23,%YMM22 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM24,%YMM10,%YMM10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM25,%YMM11,%YMM11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM22,%YMM25,%YMM16 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM8,%YMM16,%YMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPADDQ %YMM9,%YMM15,%YMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
ADD $0x4,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 436c40 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x430> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |