Function: clover_pack_message_left._omp_fn.0 | Module: exec | Source: pack_kernel.f90:61-66 | Coverage: 0.02% |
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Function: clover_pack_message_left._omp_fn.0 | Module: exec | Source: pack_kernel.f90:61-66 | Coverage: 0.02% |
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/scratch_na/users/xoserete/qaas_runs/171-215-0463/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/pack_kernel.f90: 61 - 66 |
-------------------------------------------------------------------------------- |
61: !$OMP PARALLEL DO PRIVATE(index) |
62: DO k=y_min-depth,y_max+y_inc+depth |
63: !$OMP SIMD |
64: DO j=1,depth |
65: index= buffer_offset + j+(k+depth-1)*depth |
66: left_snd_buffer(index)=field(x_min+x_inc-1+j,k) |
0x458400 PUSH %RBP |
0x458401 MOV %RSP,%RBP |
0x458404 PUSH %R15 |
0x458406 PUSH %R14 |
0x458408 PUSH %R13 |
0x45840a PUSH %R12 |
0x45840c PUSH %RBX |
0x45840d AND $-0x40,%RSP |
0x458411 SUB $0xc0,%RSP |
0x458418 MOV 0x48(%RDI),%RDX |
0x45841c MOV 0x54(%RDI),%EAX |
0x45841f MOV %RDI,0xb8(%RSP) |
0x458427 MOV 0x28(%RDI),%RCX |
0x45842b MOV 0x58(%RDI),%R13D |
0x45842f MOV 0x40(%RDI),%RBX |
0x458433 MOV 0x30(%RDI),%R15 |
0x458437 MOV %RDX,0xb0(%RSP) |
0x45843f MOV %RCX,0xa0(%RSP) |
0x458447 MOV 0x20(%RDI),%R12 |
0x45844b MOV %EAX,0x98(%RSP) |
0x458452 CALL 402080 <@plt_start@+0x60> |
0x458457 MOV %EAX,%R14D |
0x45845a CALL 402180 <@plt_start@+0x160> |
0x45845f MOV 0xb8(%RSP),%R10 |
0x458467 MOV %EAX,%ESI |
0x458469 MOV 0x5c(%R10),%EAX |
0x45846d INC %EAX |
0x45846f SUB %R13D,%EAX |
0x458472 CLTD |
0x458473 IDIV %R14D |
0x458476 CMP %EDX,%ESI |
0x458478 JL 4588c9 |
0x45847e IMUL %EAX,%ESI |
0x458481 ADD %EDX,%ESI |
0x458483 ADD %ESI,%EAX |
0x458485 CMP %EAX,%ESI |
0x458487 JGE 45885f |
0x45848d ADD %R13D,%EAX |
0x458490 CMP $0x1,%R12 |
0x458494 LEA (%R13,%RSI,1),%EDI |
0x458499 MOV 0x8(%R10),%R8 |
0x45849d SETNE %R13B |
0x4584a1 CMP $0x1,%RBX |
0x4584a5 MOV 0x10(%R10),%R9 |
0x4584a9 MOV (%R10),%R11 |
0x4584ac SETNE %CL |
0x4584af MOV %EAX,0x9c(%RSP) |
0x4584b6 MOV 0x18(%R10),%R14 |
0x4584ba OR %CL,%R13B |
0x4584bd MOV (%R8),%EAX |
0x4584c0 MOV 0x38(%R10),%R8 |
0x4584c4 MOV %EDI,0xb8(%RSP) |
0x4584cb MOV %R9,0x90(%RSP) |
0x4584d3 MOV %R11,0x88(%RSP) |
0x4584db MOV %R13B,0x5f(%RSP) |
0x4584e0 JNE 4588d2 |
0x4584e6 MOVSXD 0xb8(%RSP),%RDI |
0x4584ee MOV 0xa0(%RSP),%R12 |
0x4584f6 MOV %EAX,%R13D |
0x4584f9 MOV %EAX,%R11D |
0x4584fc AND $-0x8,%R11D |
0x458500 SHR $0x3,%R13D |
0x458504 XOR %ECX,%ECX |
0x458506 MOV 0xb0(%RSP),%RSI |
0x45850e MOV %RDI,%RBX |
0x458511 IMUL %R12,%RDI |
0x458515 SAL $0x6,%R13 |
0x458519 MOV %R11D,0x70(%RSP) |
0x45851e INC %R11D |
0x458521 MOV %R10,0x78(%RSP) |
0x458526 MOV %R11D,0x64(%RSP) |
0x45852b ADD %R15,%RDI |
0x45852e LEA -0x1(%RAX),%R15D |
0x458532 MOV %R13,0xa8(%RSP) |
0x45853a MOVSXD 0x98(%RSP),%R13 |
0x458542 LEA (%RBX,%R15,1),%R9D |
0x458546 MOV %R15D,0x80(%RSP) |
0x45854e IMUL %EAX,%R9D |
0x458552 TEST %EAX,%EAX |
0x458554 CMOVNS %EAX,%ECX |
0x458557 INC %RSI |
0x45855a MOV %RSI,0x68(%RSP) |
0x45855f LEA 0x1(%RCX),%EDX |
0x458562 MOV %EDX,0x58(%RSP) |
0x458566 NOPW %CS:(%RAX,%RAX,1) |
(322) 0x458570 TEST %EAX,%EAX |
(322) 0x458572 JLE 458823 |
(322) 0x458578 MOV 0x90(%RSP),%R10 |
(322) 0x458580 MOV 0x88(%RSP),%R12 |
(322) 0x458588 CMPL $0x6,0x80(%RSP) |
(322) 0x458590 MOV (%R10),%EBX |
(322) 0x458593 MOV (%R12),%R15D |
(322) 0x458597 JBE 4588bd |
(322) 0x45859d MOV 0x68(%RSP),%RSI |
(322) 0x4585a2 MOVSXD %R15D,%R11 |
(322) 0x4585a5 MOVSXD %EBX,%R10 |
(322) 0x4585a8 MOVSXD %R9D,%RCX |
(322) 0x4585ab ADD %R13,%R11 |
(322) 0x4585ae XOR %EDX,%EDX |
(322) 0x4585b0 ADD %RSI,%R10 |
(322) 0x4585b3 ADD %RDI,%R11 |
(322) 0x4585b6 ADD %RCX,%R10 |
(322) 0x4585b9 LEA (%R14,%R11,8),%R12 |
(322) 0x4585bd LEA (%R8,%R10,8),%R11 |
(322) 0x4585c1 MOV 0xa8(%RSP),%R10 |
(322) 0x4585c9 SUB $0x40,%R10 |
(322) 0x4585cd SHR $0x6,%R10 |
(322) 0x4585d1 INC %R10 |
(322) 0x4585d4 AND $0x7,%R10D |
(322) 0x4585d8 JE 458692 |
(322) 0x4585de CMP $0x1,%R10 |
(322) 0x4585e2 JE 458672 |
(322) 0x4585e8 CMP $0x2,%R10 |
(322) 0x4585ec JE 458660 |
(322) 0x4585ee CMP $0x3,%R10 |
(322) 0x4585f2 JE 45864e |
(322) 0x4585f4 CMP $0x4,%R10 |
(322) 0x4585f8 JE 45863c |
(322) 0x4585fa CMP $0x5,%R10 |
(322) 0x4585fe JE 45862a |
(322) 0x458600 CMP $0x6,%R10 |
(322) 0x458604 JE 458618 |
(322) 0x458606 VMOVUPD (%R12),%ZMM15 |
(322) 0x45860d MOV $0x40,%EDX |
(322) 0x458612 VMOVUPD %ZMM15,(%R11) |
(322) 0x458618 VMOVUPD (%R12,%RDX,1),%ZMM7 |
(322) 0x45861f VMOVUPD %ZMM7,(%R11,%RDX,1) |
(322) 0x458626 ADD $0x40,%RDX |
(322) 0x45862a VMOVUPD (%R12,%RDX,1),%ZMM6 |
(322) 0x458631 VMOVUPD %ZMM6,(%R11,%RDX,1) |
(322) 0x458638 ADD $0x40,%RDX |
(322) 0x45863c VMOVUPD (%R12,%RDX,1),%ZMM5 |
(322) 0x458643 VMOVUPD %ZMM5,(%R11,%RDX,1) |
(322) 0x45864a ADD $0x40,%RDX |
(322) 0x45864e VMOVUPD (%R12,%RDX,1),%ZMM4 |
(322) 0x458655 VMOVUPD %ZMM4,(%R11,%RDX,1) |
(322) 0x45865c ADD $0x40,%RDX |
(322) 0x458660 VMOVUPD (%R12,%RDX,1),%ZMM3 |
(322) 0x458667 VMOVUPD %ZMM3,(%R11,%RDX,1) |
(322) 0x45866e ADD $0x40,%RDX |
(322) 0x458672 VMOVUPD (%R12,%RDX,1),%ZMM2 |
(322) 0x458679 VMOVUPD %ZMM2,(%R11,%RDX,1) |
(322) 0x458680 ADD $0x40,%RDX |
(322) 0x458684 CMP %RDX,0xa8(%RSP) |
(322) 0x45868c JE 45872f |
(322) 0x458692 MOV 0x78(%RSP),%RSI |
(323) 0x458697 VMOVUPD (%R12,%RDX,1),%ZMM1 |
(323) 0x45869e VMOVUPD %ZMM1,(%R11,%RDX,1) |
(323) 0x4586a5 VMOVUPD 0x40(%R12,%RDX,1),%ZMM0 |
(323) 0x4586ad VMOVUPD %ZMM0,0x40(%R11,%RDX,1) |
(323) 0x4586b5 VMOVUPD 0x80(%R12,%RDX,1),%ZMM8 |
(323) 0x4586bd VMOVUPD %ZMM8,0x80(%R11,%RDX,1) |
(323) 0x4586c5 VMOVUPD 0xc0(%R12,%RDX,1),%ZMM9 |
(323) 0x4586cd VMOVUPD %ZMM9,0xc0(%R11,%RDX,1) |
(323) 0x4586d5 VMOVUPD 0x100(%R12,%RDX,1),%ZMM10 |
(323) 0x4586dd VMOVUPD %ZMM10,0x100(%R11,%RDX,1) |
(323) 0x4586e5 VMOVUPD 0x140(%R12,%RDX,1),%ZMM11 |
(323) 0x4586ed VMOVUPD %ZMM11,0x140(%R11,%RDX,1) |
(323) 0x4586f5 VMOVUPD 0x180(%R12,%RDX,1),%ZMM12 |
(323) 0x4586fd VMOVUPD %ZMM12,0x180(%R11,%RDX,1) |
(323) 0x458705 VMOVUPD 0x1c0(%R12,%RDX,1),%ZMM13 |
(323) 0x45870d VMOVUPD %ZMM13,0x1c0(%R11,%RDX,1) |
(323) 0x458715 ADD $0x200,%RDX |
(323) 0x45871c CMP %RDX,0xa8(%RSP) |
(323) 0x458724 JNE 458697 |
(322) 0x45872a MOV %RSI,0x78(%RSP) |
(322) 0x45872f MOV 0x70(%RSP),%R12D |
(322) 0x458734 CMP %EAX,%R12D |
(322) 0x458737 JE 458823 |
(322) 0x45873d MOV 0x64(%RSP),%EDX |
(322) 0x458741 MOV %R12D,%ECX |
(322) 0x458744 MOV %EAX,%R12D |
(322) 0x458747 SUB %ECX,%R12D |
(322) 0x45874a LEA -0x1(%R12),%R11D |
(322) 0x45874f CMP $0x2,%R11D |
(322) 0x458753 JBE 458799 |
(322) 0x458755 LEA (%RDI,%RCX,1),%RSI |
(322) 0x458759 MOVSXD %R15D,%R10 |
(322) 0x45875c MOVSXD %R9D,%R11 |
(322) 0x45875f ADD %R13,%RSI |
(322) 0x458762 ADD %R10,%RSI |
(322) 0x458765 MOV 0xb0(%RSP),%R10 |
(322) 0x45876d VMOVUPD (%R14,%RSI,8),%YMM14 |
(322) 0x458773 MOVSXD %EBX,%RSI |
(322) 0x458776 ADD %R10,%RCX |
(322) 0x458779 ADD %RCX,%RSI |
(322) 0x45877c LEA 0x1(%R11,%RSI,1),%RCX |
(322) 0x458781 MOV %R12D,%ESI |
(322) 0x458784 AND $-0x4,%ESI |
(322) 0x458787 VMOVUPD %YMM14,(%R8,%RCX,8) |
(322) 0x45878d ADD %ESI,%EDX |
(322) 0x45878f AND $0x3,%R12D |
(322) 0x458793 JE 458823 |
(322) 0x458799 MOV 0x98(%RSP),%R12D |
(322) 0x4587a1 LEA (%RBX,%RDX,1),%ECX |
(322) 0x4587a4 ADD %R9D,%ECX |
(322) 0x4587a7 LEA -0x1(%R12,%R15,1),%R10D |
(322) 0x4587ac MOV 0xb0(%RSP),%R12 |
(322) 0x4587b4 MOVSXD %ECX,%RSI |
(322) 0x4587b7 LEA (%R10,%RDX,1),%R15D |
(322) 0x4587bb MOVSXD %R15D,%R11 |
(322) 0x4587be ADD %R12,%RSI |
(322) 0x4587c1 LEA 0x1(%RDX),%R15D |
(322) 0x4587c5 ADD %RDI,%R11 |
(322) 0x4587c8 VMOVSD (%R14,%R11,8),%XMM15 |
(322) 0x4587ce VMOVSD %XMM15,(%R8,%RSI,8) |
(322) 0x4587d4 CMP %R15D,%EAX |
(322) 0x4587d7 JL 458823 |
(322) 0x4587d9 LEA (%R10,%R15,1),%R11D |
(322) 0x4587dd ADD %EBX,%R15D |
(322) 0x4587e0 ADD $0x2,%EDX |
(322) 0x4587e3 MOVSXD %R11D,%RCX |
(322) 0x4587e6 ADD %R9D,%R15D |
(322) 0x4587e9 ADD %RDI,%RCX |
(322) 0x4587ec MOVSXD %R15D,%RSI |
(322) 0x4587ef VMOVSD (%R14,%RCX,8),%XMM7 |
(322) 0x4587f5 ADD %R12,%RSI |
(322) 0x4587f8 VMOVSD %XMM7,(%R8,%RSI,8) |
(322) 0x4587fe CMP %EDX,%EAX |
(322) 0x458800 JL 458823 |
(322) 0x458802 LEA (%RDX,%R10,1),%R10D |
(322) 0x458806 ADD %EBX,%EDX |
(322) 0x458808 MOVSXD %R10D,%R15 |
(322) 0x45880b ADD %R9D,%EDX |
(322) 0x45880e ADD %RDI,%R15 |
(322) 0x458811 MOVSXD %EDX,%RBX |
(322) 0x458814 VMOVSD (%R14,%R15,8),%XMM6 |
(322) 0x45881a ADD %R12,%RBX |
(322) 0x45881d VMOVSD %XMM6,(%R8,%RBX,8) |
(322) 0x458823 INCL 0xb8(%RSP) |
(322) 0x45882a MOV 0xa0(%RSP),%R12 |
(322) 0x458832 ADD %EAX,%R9D |
(322) 0x458835 ADD %R12,%RDI |
(322) 0x458838 MOV 0xb8(%RSP),%EDX |
(322) 0x45883f TEST %EAX,%EAX |
(322) 0x458841 JNS 4588a0 |
(322) 0x458843 CMP %EDX,0x9c(%RSP) |
(322) 0x45884a JG 458570 |
0x458850 MOV 0x78(%RSP),%R14 |
0x458855 VZEROUPPER |
0x458858 CMPB $0,0x5f(%RSP) |
0x45885d JNE 45887e |
0x45885f LEA -0x28(%RBP),%RSP |
0x458863 POP %RBX |
0x458864 POP %R12 |
0x458866 POP %R13 |
0x458868 POP %R14 |
0x45886a POP %R15 |
0x45886c POP %RBP |
0x45886d RET |
0x45886e MOV 0x78(%RSP),%R14 |
0x458873 VZEROUPPER |
0x458876 MOV 0x58(%RSP),%EAX |
0x45887a MOV %EAX,0x54(%RSP) |
0x45887e MOV 0x54(%RSP),%R8D |
0x458883 MOV %R8D,0x50(%R14) |
0x458887 LEA -0x28(%RBP),%RSP |
0x45888b POP %RBX |
0x45888c POP %R12 |
0x45888e POP %R13 |
0x458890 POP %R14 |
0x458892 POP %R15 |
0x458894 POP %RBP |
0x458895 RET |
0x458896 NOPW %CS:(%RAX,%RAX,1) |
(322) 0x4588a0 CMP %EDX,0x9c(%RSP) |
(322) 0x4588a7 JLE 45886e |
(322) 0x4588a9 MOV 0x58(%RSP),%R11D |
(322) 0x4588ae MOVB $0x1,0x5f(%RSP) |
(322) 0x4588b3 MOV %R11D,0x54(%RSP) |
(322) 0x4588b8 JMP 458570 |
(322) 0x4588bd XOR %ECX,%ECX |
(322) 0x4588bf MOV $0x1,%EDX |
(322) 0x4588c4 JMP 458744 |
0x4588c9 INC %EAX |
0x4588cb XOR %EDX,%EDX |
0x4588cd JMP 45847e |
0x4588d2 MOVSXD 0xb8(%RSP),%RSI |
0x4588da MOV 0xa0(%RSP),%RDI |
0x4588e2 LEA -0x1(%RAX),%R9D |
0x4588e6 MOV %EAX,%R13D |
0x4588e9 KXORB %K0,%K0,%K0 |
0x4588ed MOV %R9D,0x50(%RSP) |
0x4588f2 SHR $0x3,%R13D |
0x4588f6 MOV %R12,%RCX |
0x4588f9 MOV %RSI,%RDX |
0x4588fc IMUL %RDI,%RSI |
0x458900 MOV %R12,%RDI |
0x458903 SAL $0x6,%RCX |
0x458907 LEA (%RDX,%R9,1),%R11D |
0x45890b SAL $0x5,%RDI |
0x45890f MOV %RBX,%R9 |
0x458912 MOV %R13D,0x68(%RSP) |
0x458917 IMUL %EAX,%R11D |
0x45891b SAL $0x5,%R9 |
0x45891f LEA (,%RBX,8),%RDX |
0x458927 MOV %RDI,0x10(%RSP) |
0x45892c LEA (%RSI,%R15,1),%R15 |
0x458930 MOV %EAX,%EDI |
0x458932 LEA (,%R12,8),%RSI |
0x45893a MOV %RDX,0x48(%RSP) |
0x45893f AND $-0x8,%EDI |
0x458942 LEA (%RBX,%RBX,2),%RDX |
0x458946 MOV %R15,0x80(%RSP) |
0x45894e MOV %RBX,%R15 |
0x458951 MOV %R11D,0xa8(%RSP) |
0x458959 LEA (%R12,%R12,2),%R11 |
0x45895d SAL $0x6,%R15 |
0x458961 MOV %RSI,0x40(%RSP) |
0x458966 MOV %R12,%RSI |
0x458969 LEA (,%R11,8),%R13 |
0x458971 LEA (,%RDX,8),%R11 |
0x458979 MOV %R9,0x18(%RSP) |
0x45897e MOV %RBX,%R9 |
0x458981 SAL $0x4,%RSI |
0x458985 XOR %EDX,%EDX |
0x458987 SAL $0x4,%R9 |
0x45898b MOV %EDI,0x24(%RSP) |
0x45898f INC %EDI |
0x458991 TEST %EAX,%EAX |
0x458993 CMOVNS %EAX,%EDX |
0x458996 MOV %EDI,0x20(%RSP) |
0x45899a MOV %R8,0x70(%RSP) |
0x45899f LEA 0x1(%RDX),%EDI |
0x4589a2 MOV %R9,0x30(%RSP) |
0x4589a7 MOV %EDI,0x58(%RSP) |
0x4589ab MOV %R10,0x8(%RSP) |
0x4589b0 MOV %RCX,0x38(%RSP) |
0x4589b5 MOV %R14,0x78(%RSP) |
0x4589ba MOV %RSI,%R14 |
0x4589bd NOPL (%RAX) |
(320) 0x4589c0 TEST %EAX,%EAX |
(320) 0x4589c2 JLE 458d85 |
(320) 0x4589c8 MOV 0x90(%RSP),%R10 |
(320) 0x4589d0 MOV 0x88(%RSP),%RCX |
(320) 0x4589d8 MOV 0x98(%RSP),%ESI |
(320) 0x4589df MOV (%R10),%R8D |
(320) 0x4589e2 ADD (%RCX),%ESI |
(320) 0x4589e4 CMPL $0x6,0x50(%RSP) |
(320) 0x4589e9 MOV %R8D,0x64(%RSP) |
(320) 0x4589ee MOV %ESI,0x60(%RSP) |
(320) 0x4589f2 JBE 458de9 |
(320) 0x4589f8 MOVSXD %ESI,%R9 |
(320) 0x4589fb MOVSXD 0xa8(%RSP),%RSI |
(320) 0x458a03 MOVSXD %R8D,%R8 |
(320) 0x458a06 MOV 0x80(%RSP),%RDX |
(320) 0x458a0e IMUL %R12,%R9 |
(320) 0x458a12 MOV 0xb0(%RSP),%RCX |
(320) 0x458a1a MOV 0x78(%RSP),%RDI |
(320) 0x458a1f LEA 0x1(%R8,%RSI,1),%R10 |
(320) 0x458a24 XOR %R8D,%R8D |
(320) 0x458a27 IMUL %RBX,%R10 |
(320) 0x458a2b ADD %RDX,%R9 |
(320) 0x458a2e MOV 0x70(%RSP),%RDX |
(320) 0x458a33 LEA (%RDI,%R9,8),%RDI |
(320) 0x458a37 ADD %RCX,%R10 |
(320) 0x458a3a MOV 0x10(%RSP),%RCX |
(320) 0x458a3f LEA (%RDX,%R10,8),%RSI |
(320) 0x458a43 MOV 0x18(%RSP),%RDX |
(320) 0x458a48 MOV %RSI,0x28(%RSP) |
(320) 0x458a4d ADD %RDI,%RCX |
(320) 0x458a50 ADD %RSI,%RDX |
(320) 0x458a53 TESTB $0x1,0x68(%RSP) |
(320) 0x458a58 JE 458ade |
(320) 0x458a5e VMOVSD (%RDI),%XMM7 |
(320) 0x458a62 VMOVSD (%RDI,%R12,8),%XMM6 |
(320) 0x458a68 VMOVSD (%RDI,%R14,1),%XMM5 |
(320) 0x458a6e VMOVSD (%RDI,%R13,1),%XMM4 |
(320) 0x458a74 VMOVSD (%RCX),%XMM3 |
(320) 0x458a78 VMOVSD (%RCX,%R12,8),%XMM2 |
(320) 0x458a7e VMOVSD (%RCX,%R14,1),%XMM1 |
(320) 0x458a84 MOV 0x30(%RSP),%R8 |
(320) 0x458a89 VMOVSD (%RCX,%R13,1),%XMM0 |
(320) 0x458a8f MOV 0x38(%RSP),%R10 |
(320) 0x458a94 VMOVSD %XMM7,(%RSI) |
(320) 0x458a98 MOV 0x68(%RSP),%R9D |
(320) 0x458a9d VMOVSD %XMM6,(%RSI,%RBX,8) |
(320) 0x458aa2 VMOVSD %XMM5,(%RSI,%R8,1) |
(320) 0x458aa8 ADD %R10,%RDI |
(320) 0x458aab ADD %R10,%RCX |
(320) 0x458aae VMOVSD %XMM4,(%RSI,%R11,1) |
(320) 0x458ab4 ADD %R15,%RSI |
(320) 0x458ab7 VMOVSD %XMM3,(%RDX) |
(320) 0x458abb VMOVSD %XMM2,(%RDX,%RBX,8) |
(320) 0x458ac0 VMOVSD %XMM1,(%RDX,%R8,1) |
(320) 0x458ac6 MOV $0x1,%R8D |
(320) 0x458acc VMOVSD %XMM0,(%RDX,%R11,1) |
(320) 0x458ad2 ADD %R15,%RDX |
(320) 0x458ad5 CMP %R9D,%R8D |
(320) 0x458ad8 JE 458bcf |
(320) 0x458ade MOV 0x38(%RSP),%R10 |
(320) 0x458ae3 MOV 0x30(%RSP),%R9 |
(320) 0x458ae8 MOV %EAX,0x28(%RSP) |
(321) 0x458aec VMOVSD (%RDI),%XMM8 |
(321) 0x458af0 VMOVSD (%RDI,%R12,8),%XMM9 |
(321) 0x458af6 ADD $0x2,%R8D |
(321) 0x458afa VMOVSD (%RDI,%R14,1),%XMM10 |
(321) 0x458b00 VMOVSD (%RDI,%R13,1),%XMM11 |
(321) 0x458b06 ADD %R10,%RDI |
(321) 0x458b09 VMOVSD (%RCX),%XMM12 |
(321) 0x458b0d VMOVSD (%RCX,%R12,8),%XMM13 |
(321) 0x458b13 VMOVSD (%RCX,%R14,1),%XMM14 |
(321) 0x458b19 VMOVSD (%RCX,%R13,1),%XMM15 |
(321) 0x458b1f VMOVSD %XMM8,(%RSI) |
(321) 0x458b23 ADD %R10,%RCX |
(321) 0x458b26 VMOVSD %XMM9,(%RSI,%RBX,8) |
(321) 0x458b2b VMOVSD %XMM10,(%RSI,%R9,1) |
(321) 0x458b31 VMOVSD %XMM11,(%RSI,%R11,1) |
(321) 0x458b37 ADD %R15,%RSI |
(321) 0x458b3a VMOVSD %XMM12,(%RDX) |
(321) 0x458b3e VMOVSD %XMM13,(%RDX,%RBX,8) |
(321) 0x458b43 VMOVSD %XMM14,(%RDX,%R9,1) |
(321) 0x458b49 VMOVSD %XMM15,(%RDX,%R11,1) |
(321) 0x458b4f ADD %R15,%RDX |
(321) 0x458b52 VMOVSD (%RDI),%XMM7 |
(321) 0x458b56 VMOVSD (%RDI,%R12,8),%XMM6 |
(321) 0x458b5c VMOVSD (%RDI,%R14,1),%XMM5 |
(321) 0x458b62 VMOVSD (%RDI,%R13,1),%XMM4 |
(321) 0x458b68 ADD %R10,%RDI |
(321) 0x458b6b VMOVSD (%RCX),%XMM3 |
(321) 0x458b6f VMOVSD (%RCX,%R12,8),%XMM2 |
(321) 0x458b75 VMOVSD (%RCX,%R14,1),%XMM1 |
(321) 0x458b7b VMOVSD (%RCX,%R13,1),%XMM0 |
(321) 0x458b81 VMOVSD %XMM7,(%RSI) |
(321) 0x458b85 ADD %R10,%RCX |
(321) 0x458b88 VMOVSD %XMM6,(%RSI,%RBX,8) |
(321) 0x458b8d VMOVSD %XMM5,(%RSI,%R9,1) |
(321) 0x458b93 VMOVSD %XMM4,(%RSI,%R11,1) |
(321) 0x458b99 ADD %R15,%RSI |
(321) 0x458b9c VMOVSD %XMM3,(%RDX) |
(321) 0x458ba0 VMOVSD %XMM2,(%RDX,%RBX,8) |
(321) 0x458ba5 VMOVSD %XMM1,(%RDX,%R9,1) |
(321) 0x458bab VMOVSD %XMM0,(%RDX,%R11,1) |
(321) 0x458bb1 MOV 0x68(%RSP),%EAX |
(321) 0x458bb5 ADD %R15,%RDX |
(321) 0x458bb8 CMP %EAX,%R8D |
(321) 0x458bbb JNE 458aec |
(320) 0x458bc1 MOV %R10,0x38(%RSP) |
(320) 0x458bc6 MOV 0x28(%RSP),%EAX |
(320) 0x458bca MOV %R9,0x30(%RSP) |
(320) 0x458bcf MOV 0x24(%RSP),%EDI |
(320) 0x458bd3 CMP %EAX,%EDI |
(320) 0x458bd5 JE 458d85 |
(320) 0x458bdb MOV 0x20(%RSP),%ECX |
(320) 0x458bdf MOV %EDI,%R10D |
(320) 0x458be2 MOV %EAX,%R8D |
(320) 0x458be5 SUB %R10D,%R8D |
(320) 0x458be8 LEA -0x1(%R8),%ESI |
(320) 0x458bec CMP $0x2,%ESI |
(320) 0x458bef JBE 458c9b |
(320) 0x458bf5 MOVSXD 0x60(%RSP),%RDX |
(320) 0x458bfa MOV %R12,%RDI |
(320) 0x458bfd MOV 0x80(%RSP),%R9 |
(320) 0x458c05 IMUL %R10,%RDI |
(320) 0x458c09 MOV 0x78(%RSP),%RSI |
(320) 0x458c0e IMUL %R12,%RDX |
(320) 0x458c12 IMUL %RBX,%R10 |
(320) 0x458c16 ADD %R9,%RDX |
(320) 0x458c19 MOVSXD 0xa8(%RSP),%R9 |
(320) 0x458c21 ADD %RDI,%RDX |
(320) 0x458c24 MOVSXD 0x64(%RSP),%RDI |
(320) 0x458c29 LEA (%RSI,%RDX,8),%RDX |
(320) 0x458c2d MOV 0xb0(%RSP),%RSI |
(320) 0x458c35 LEA 0x1(%RDI,%R9,1),%RDI |
(320) 0x458c3a VMOVSD (%RDX),%XMM8 |
(320) 0x458c3e IMUL %RBX,%RDI |
(320) 0x458c42 ADD %RSI,%RDI |
(320) 0x458c45 MOV %R8D,%ESI |
(320) 0x458c48 ADD %R10,%RDI |
(320) 0x458c4b MOV 0x70(%RSP),%R10 |
(320) 0x458c50 AND $-0x4,%ESI |
(320) 0x458c53 ADD %ESI,%ECX |
(320) 0x458c55 LEA (%R10,%RDI,8),%R9 |
(320) 0x458c59 MOV 0x40(%RSP),%RDI |
(320) 0x458c5e ADD %RDI,%RDX |
(320) 0x458c61 VMOVSD (%RDX),%XMM9 |
(320) 0x458c65 ADD %RDI,%RDX |
(320) 0x458c68 VMOVSD (%RDX),%XMM10 |
(320) 0x458c6c VMOVSD (%RDX,%RDI,1),%XMM11 |
(320) 0x458c71 VMOVSD %XMM8,(%R9) |
(320) 0x458c76 MOV 0x48(%RSP),%RDX |
(320) 0x458c7b ADD %RDX,%R9 |
(320) 0x458c7e VMOVSD %XMM9,(%R9) |
(320) 0x458c83 ADD %RDX,%R9 |
(320) 0x458c86 AND $0x3,%R8D |
(320) 0x458c8a VMOVSD %XMM10,(%R9) |
(320) 0x458c8f VMOVSD %XMM11,(%R9,%RDX,1) |
(320) 0x458c95 JE 458d85 |
(320) 0x458c9b MOV 0x60(%RSP),%ESI |
(320) 0x458c9f MOV 0x80(%RSP),%R9 |
(320) 0x458ca7 MOV 0x78(%RSP),%RDI |
(320) 0x458cac DEC %ESI |
(320) 0x458cae LEA (%RSI,%RCX,1),%R8D |
(320) 0x458cb2 MOVSXD %R8D,%R10 |
(320) 0x458cb5 MOV 0x64(%RSP),%R8D |
(320) 0x458cba IMUL %R12,%R10 |
(320) 0x458cbe LEA (%R8,%RCX,1),%EDX |
(320) 0x458cc2 ADD %R9,%R10 |
(320) 0x458cc5 VMOVSD (%RDI,%R10,8),%XMM12 |
(320) 0x458ccb MOV 0xa8(%RSP),%R10D |
(320) 0x458cd3 MOV 0xb0(%RSP),%RDI |
(320) 0x458cdb ADD %R10D,%EDX |
(320) 0x458cde MOV 0x70(%RSP),%R10 |
(320) 0x458ce3 MOVSXD %EDX,%RDX |
(320) 0x458ce6 IMUL %RBX,%RDX |
(320) 0x458cea ADD %RDI,%RDX |
(320) 0x458ced VMOVSD %XMM12,(%R10,%RDX,8) |
(320) 0x458cf3 LEA 0x1(%RCX),%EDX |
(320) 0x458cf6 CMP %EDX,%EAX |
(320) 0x458cf8 JL 458d85 |
(320) 0x458cfe LEA (%RSI,%RDX,1),%EDI |
(320) 0x458d01 MOV 0x78(%RSP),%R10 |
(320) 0x458d06 ADD %R8D,%EDX |
(320) 0x458d09 ADD $0x2,%ECX |
(320) 0x458d0c MOVSXD %EDI,%RDI |
(320) 0x458d0f IMUL %R12,%RDI |
(320) 0x458d13 ADD %R9,%RDI |
(320) 0x458d16 VMOVSD (%R10,%RDI,8),%XMM13 |
(320) 0x458d1c MOV %R8D,%EDI |
(320) 0x458d1f MOV 0xa8(%RSP),%R8D |
(320) 0x458d27 MOV 0xb0(%RSP),%R10 |
(320) 0x458d2f ADD %R8D,%EDX |
(320) 0x458d32 MOVSXD %EDX,%RDX |
(320) 0x458d35 IMUL %RBX,%RDX |
(320) 0x458d39 ADD %R10,%RDX |
(320) 0x458d3c MOV 0x70(%RSP),%R10 |
(320) 0x458d41 VMOVSD %XMM13,(%R10,%RDX,8) |
(320) 0x458d47 CMP %ECX,%EAX |
(320) 0x458d49 JL 458d85 |
(320) 0x458d4b LEA (%RSI,%RCX,1),%ESI |
(320) 0x458d4e ADD %ECX,%EDI |
(320) 0x458d50 MOV 0x70(%RSP),%R10 |
(320) 0x458d55 MOVSXD %ESI,%RDX |
(320) 0x458d58 ADD %R8D,%EDI |
(320) 0x458d5b MOV 0xb0(%RSP),%R8 |
(320) 0x458d63 IMUL %R12,%RDX |
(320) 0x458d67 MOVSXD %EDI,%RCX |
(320) 0x458d6a IMUL %RBX,%RCX |
(320) 0x458d6e ADD %R9,%RDX |
(320) 0x458d71 MOV 0x78(%RSP),%R9 |
(320) 0x458d76 ADD %R8,%RCX |
(320) 0x458d79 VMOVSD (%R9,%RDX,8),%XMM14 |
(320) 0x458d7f VMOVSD %XMM14,(%R10,%RCX,8) |
(320) 0x458d85 INCL 0xb8(%RSP) |
(320) 0x458d8c MOV 0xa0(%RSP),%RSI |
(320) 0x458d94 ADD %EAX,0xa8(%RSP) |
(320) 0x458d9b ADD %RSI,0x80(%RSP) |
(320) 0x458da3 MOV 0xb8(%RSP),%EDX |
(320) 0x458daa TEST %EAX,%EAX |
(320) 0x458dac JNS 458dcb |
(320) 0x458dae CMP %EDX,0x9c(%RSP) |
(320) 0x458db5 JG 4589c0 |
0x458dbb MOV 0x8(%RSP),%R14 |
0x458dc0 KMOVB %K0,0x5f(%RSP) |
0x458dc6 JMP 458858 |
(320) 0x458dcb CMP %EDX,0x9c(%RSP) |
(320) 0x458dd2 JLE 458df6 |
(320) 0x458dd4 MOV 0x58(%RSP),%R9D |
(320) 0x458dd9 KMOVB 0x5f(%RSP),%K0 |
(320) 0x458ddf MOV %R9D,0x54(%RSP) |
(320) 0x458de4 JMP 4589c0 |
(320) 0x458de9 XOR %R10D,%R10D |
(320) 0x458dec MOV $0x1,%ECX |
(320) 0x458df1 JMP 458be2 |
0x458df6 MOV 0x8(%RSP),%R14 |
0x458dfb JMP 458876 |
Path / |
Source file and lines | pack_kernel.f90:61-66 |
Module | exec |
nb instructions | 174 |
nb uops | 181 |
loop length | 721 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 27 |
micro-operation queue | 30.17 cycles |
front end | 30.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.50 | 11.40 | 14.00 | 14.00 | 21.50 | 11.40 | 11.30 | 21.50 | 21.50 | 21.50 | 11.40 | 14.00 |
cycles | 11.50 | 13.60 | 14.00 | 14.00 | 21.50 | 11.40 | 11.30 | 21.50 | 21.50 | 21.50 | 11.40 | 14.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 29.47-29.49 |
Stall cycles | 0.00 |
Front-end | 30.17 |
Dispatch | 21.50 |
DIV/SQRT | 6.00 |
Overall L1 | 30.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 22% |
all | 9% |
load | 1% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x48(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x54(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RDI),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x5c(%R10),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R14D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 4588c9 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x4c9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 45885f <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x45f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x1,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R13,%RSI,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x8(%R10),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %R13B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP $0x1,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R10),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %CL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x9c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R10),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
OR %CL,%R13B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV (%R8),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%R10),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDI,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13B,0x5f(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 4588d2 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x4d2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD 0xb8(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xb0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R12,%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x6,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11D,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11D,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R15,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD 0x98(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RBX,%R15,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15D,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %EAX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %EAX,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x78(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CMPB $0,0x5f(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 45887e <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x47e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV 0x78(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x58(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x54(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8D,0x50(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 45847e <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x7e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOVSXD 0xb8(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%RAX),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
KXORB %K0,%K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %R9D,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R12,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RDI,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDX,%R9,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x5,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RBX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %EAX,%R11D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x5,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (,%RBX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RSI,%R15,1),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%R12,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $-0x8,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RBX,%RBX,2),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11D,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R12,%R12,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x6,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%R11,8),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (,%RDX,8),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x4,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x4,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EDI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %EAX,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RDX),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
KMOVB %K0,0x5f(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
JMP 458858 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x458> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 458876 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x476> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | pack_kernel.f90:61-66 |
Module | exec |
nb instructions | 174 |
nb uops | 181 |
loop length | 721 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 27 |
micro-operation queue | 30.17 cycles |
front end | 30.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.50 | 11.40 | 14.00 | 14.00 | 21.50 | 11.40 | 11.30 | 21.50 | 21.50 | 21.50 | 11.40 | 14.00 |
cycles | 11.50 | 13.60 | 14.00 | 14.00 | 21.50 | 11.40 | 11.30 | 21.50 | 21.50 | 21.50 | 11.40 | 14.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 29.47-29.49 |
Stall cycles | 0.00 |
Front-end | 30.17 |
Dispatch | 21.50 |
DIV/SQRT | 6.00 |
Overall L1 | 30.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 22% |
all | 9% |
load | 1% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x48(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x54(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RDI),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x5c(%R10),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R14D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 4588c9 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x4c9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 45885f <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x45f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x1,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R13,%RSI,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x8(%R10),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %R13B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP $0x1,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R10),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %CL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x9c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R10),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
OR %CL,%R13B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV (%R8),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%R10),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDI,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13B,0x5f(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 4588d2 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x4d2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD 0xb8(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xb0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R12,%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x6,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11D,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11D,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R15,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD 0x98(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RBX,%R15,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15D,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %EAX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %EAX,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x78(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CMPB $0,0x5f(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 45887e <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x47e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV 0x78(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x58(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x54(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8D,0x50(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 45847e <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x7e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOVSXD 0xb8(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%RAX),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
KXORB %K0,%K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %R9D,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R12,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RDI,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDX,%R9,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x5,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RBX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %EAX,%R11D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x5,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (,%RBX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RSI,%R15,1),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%R12,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $-0x8,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RBX,%RBX,2),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11D,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R12,%R12,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x6,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%R11,8),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (,%RDX,8),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x4,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x4,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EDI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %EAX,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RDX),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
KMOVB %K0,0x5f(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
JMP 458858 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x458> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 458876 <__pack_kernel_module_MOD_clover_pack_message_left._omp_fn.0+0x476> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼clover_pack_message_left._omp_fn.0– | 0.02 | 0.02 |
▼Loop 322 - pack_kernel.f90:61-66 - exec– | 0.02 | 0.04 |
○Loop 323 - pack_kernel.f90:66-66 - exec | 0 | 0 |
▼Loop 320 - pack_kernel.f90:65-66 - exec– | 0 | 0 |
○Loop 321 - pack_kernel.f90:66-66 - exec | 0 | 0 |