Function: calc_dt_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: calc_dt_kernel.f90:89-133 | Coverage: 3.34% |
---|
Function: calc_dt_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: calc_dt_kernel.f90:89-133 | Coverage: 3.34% |
---|
/scratch_na/users/xoserete/qaas_runs/171-215-0463/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 133 |
-------------------------------------------------------------------------------- |
89: !$OMP PARALLEL |
90: |
91: !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val) |
92: DO k=y_min,y_max |
93: !$OMP SIMD |
94: DO j=x_min,x_max |
95: |
96: dsx=celldx(j) |
97: dsy=celldy(k) |
98: |
99: cc=soundspeed(j,k)*soundspeed(j,k) |
100: cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k) |
101: cc=MAX(SQRT(cc),g_small) |
102: |
103: dtct=dtc_safe*MIN(dsx,dsy)/cc |
104: |
105: div=0.0 |
106: |
107: dv1=(xvel0(j ,k)+xvel0(j ,k+1))*xarea(j ,k) |
108: dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k) |
109: |
110: div=div+dv2-dv1 |
111: |
112: dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
113: |
114: dv1=(yvel0(j,k )+yvel0(j+1,k ))*yarea(j,k ) |
115: dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1) |
116: |
117: div=div+dv2-dv1 |
118: |
119: dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
120: |
121: div=div/(2.0_8*volume(j,k)) |
122: |
123: IF(div.LT.-g_small)THEN |
124: dtdivt=dtdiv_safe*(-1.0_8/div) |
125: ELSE |
126: dtdivt=g_big |
127: ENDIF |
128: |
129: dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt) |
130: |
131: ENDDO |
132: ENDDO |
133: !$OMP END DO |
0x43a520 PUSH %RBP |
0x43a521 MOV %RSP,%RBP |
0x43a524 PUSH %R15 |
0x43a526 PUSH %R14 |
0x43a528 PUSH %R13 |
0x43a52a PUSH %R12 |
0x43a52c PUSH %RBX |
0x43a52d AND $-0x40,%RSP |
0x43a531 SUB $0x4c0,%RSP |
0x43a538 MOV %RDI,%RBX |
0x43a53b MOV 0x90(%RBP),%R14D |
0x43a542 MOV 0x88(%RBP),%EAX |
0x43a548 SUB %R14D,%EAX |
0x43a54b MOVL $0,0x44(%RSP) |
0x43a553 JS 43a652 |
0x43a559 MOV %R8,0x70(%RSP) |
0x43a55e MOV %RCX,%R12 |
0x43a561 MOV %RDX,%R15 |
0x43a564 MOV %R9,0x48(%RSP) |
0x43a569 MOV %RBX,0x78(%RSP) |
0x43a56e MOV (%RBX),%ESI |
0x43a570 MOVL $0,0x2c(%RSP) |
0x43a578 MOV %EAX,0x28(%RSP) |
0x43a57c MOVL $0x1,0x40(%RSP) |
0x43a584 SUB $0x8,%RSP |
0x43a588 LEA 0x48(%RSP),%RAX |
0x43a58d LEA 0x4c(%RSP),%RCX |
0x43a592 LEA 0x34(%RSP),%R8 |
0x43a597 LEA 0x30(%RSP),%R9 |
0x43a59c MOV $0x74a3d0,%EDI |
0x43a5a1 MOV %ESI,0x40(%RSP) |
0x43a5a5 MOV $0x22,%EDX |
0x43a5aa PUSH $0x1 |
0x43a5ac PUSH $0x1 |
0x43a5ae PUSH %RAX |
0x43a5af CALL 4045a0 <__kmpc_for_static_init_4@plt> |
0x43a5b4 ADD $0x20,%RSP |
0x43a5b8 MOV 0x2c(%RSP),%R11D |
0x43a5bd MOV 0x28(%RSP),%EAX |
0x43a5c1 SUB %R11D,%EAX |
0x43a5c4 MOV %EAX,0x3c(%RSP) |
0x43a5c8 JAE 43a680 |
0x43a5ce VMOVSD 0xd10e8(%RIP),%XMM28 |
0x43a5d8 VMOVSD %XMM28,0x68(%RSP) |
0x43a5e0 MOV $0x74a3f0,%EDI |
0x43a5e5 MOV 0x38(%RSP),%ESI |
0x43a5e9 VZEROUPPER |
0x43a5ec CALL 404190 <__kmpc_for_static_fini@plt> |
0x43a5f1 MOV 0x78(%RSP),%RBX |
0x43a5f6 MOV (%RBX),%ESI |
0x43a5f8 SUB $0x8,%RSP |
0x43a5fc MOV $0x7a3060,%RAX |
0x43a603 LEA 0x70(%RSP),%R8 |
0x43a608 MOV $0x74a410,%EDI |
0x43a60d MOV $0x43a510,%R9D |
0x43a613 MOV $0x1,%EDX |
0x43a618 MOV $0x8,%ECX |
0x43a61d PUSH %RAX |
0x43a61e CALL 404780 <__kmpc_reduce@plt> |
0x43a623 ADD $0x10,%RSP |
0x43a627 CMP $0x1,%EAX |
0x43a62a MOV 0x70(%RSP),%RAX |
0x43a62f JNE 43a652 |
0x43a631 VMOVSD 0x68(%RSP),%XMM0 |
0x43a637 VMINSD (%RAX),%XMM0,%XMM0 |
0x43a63b VMOVSD %XMM0,(%RAX) |
0x43a63f MOV (%RBX),%ESI |
0x43a641 MOV $0x7a3060,%RDX |
0x43a648 MOV $0x74a430,%EDI |
0x43a64d CALL 404900 <__kmpc_end_reduce@plt> |
0x43a652 MOV (%RBX),%ESI |
0x43a654 MOV $0x74a450,%EDI |
0x43a659 CALL 404660 <__kmpc_barrier@plt> |
0x43a65e LEA -0x28(%RBP),%RSP |
0x43a662 POP %RBX |
0x43a663 POP %R12 |
0x43a665 POP %R13 |
0x43a667 POP %R14 |
0x43a669 POP %R15 |
0x43a66b POP %RBP |
0x43a66c RET |
0x43a66d NOPW %CS:(%RAX,%RAX,1) |
0x43a67c NOPL (%RAX) |
0x43a680 MOV 0xa0(%RBP),%RSI |
0x43a687 MOV 0x98(%RBP),%RAX |
0x43a68e SAL $0x20,%R12 |
0x43a692 MOV $-0x200000000,%RCX |
0x43a69c LEA (%R12,%RCX,1),%RDX |
0x43a6a0 MOV %RDX,%RDI |
0x43a6a3 SAR $0x20,%RDI |
0x43a6a7 MOV %RDI,0x88(%RSP) |
0x43a6af SAL $0x20,%R15 |
0x43a6b3 ADD %R15,%RCX |
0x43a6b6 MOV %RCX,%R10 |
0x43a6b9 SAR $0x20,%R10 |
0x43a6bd MOVSXD (%RSI),%RDI |
0x43a6c0 MOV (%RAX),%EAX |
0x43a6c2 SUB %EDI,%EAX |
0x43a6c4 ADD %R14D,%R11D |
0x43a6c7 MOV %RAX,%R14 |
0x43a6ca INC %EAX |
0x43a6cc CMP $0x2,%EAX |
0x43a6cf MOV $0x1,%EBX |
0x43a6d4 CMOVGE %EAX,%EBX |
0x43a6d7 MOV %EBX,%EAX |
0x43a6d9 AND $0x7ffffff8,%EAX |
0x43a6de TEST %RDX,%RDX |
0x43a6e1 MOV $-0x1,%RSI |
0x43a6e8 CMOVNS %RDX,%RSI |
0x43a6ec TEST %RSI,%RSI |
0x43a6ef MOV $0x1,%R13D |
0x43a6f5 CMOVG %R13,%RSI |
0x43a6f9 MOV $0x200000000,%R9 |
0x43a703 MOV %R9,%R8 |
0x43a706 SUB %R12,%R8 |
0x43a709 CMP %R8,%RDX |
0x43a70c CMOVG %RDX,%R8 |
0x43a710 MOV %RDI,0x80(%RSP) |
0x43a718 LEA (,%RDI,8),%R12 |
0x43a720 SHR $0x20,%R8 |
0x43a724 IMUL %RSI,%R8 |
0x43a728 MOV $-0x1,%RDX |
0x43a72f SAL $0x3,%R8 |
0x43a733 SUB %R8,%R12 |
0x43a736 MOV $0x1,%ESI |
0x43a73b MOV %R10,0xf0(%RSP) |
0x43a743 SUB %R10,%RSI |
0x43a746 MOV %RSI,0xd0(%RSP) |
0x43a74e TEST %RCX,%RCX |
0x43a751 CMOVNS %RCX,%RDX |
0x43a755 TEST %RDX,%RDX |
0x43a758 CMOVG %R13,%RDX |
0x43a75c MOV 0x50(%RBP),%RSI |
0x43a760 SUB %R15,%R9 |
0x43a763 MOV 0x48(%RBP),%RDI |
0x43a767 CMP %R9,%RCX |
0x43a76a CMOVG %RCX,%R9 |
0x43a76e SHR $0x20,%R9 |
0x43a772 IMUL %RDX,%R9 |
0x43a776 MOV 0x30(%RBP),%RCX |
0x43a77a MOV %RBX,0xe0(%RSP) |
0x43a782 VPBROADCASTQ %RBX,%ZMM0 |
0x43a788 VMOVDQA64 %ZMM0,0x140(%RSP) |
0x43a790 NEG %R9 |
0x43a793 MOV %R9,0xd8(%RSP) |
0x43a79b MOV 0x28(%RBP),%RDX |
0x43a79f MOV 0x20(%RBP),%R8 |
0x43a7a3 MOV 0x18(%RBP),%R9 |
0x43a7a7 MOV 0x10(%RBP),%R10 |
0x43a7ab MOV 0x48(%RSP),%RBX |
0x43a7b0 LEA 0x8(%RBX,%R12,1),%RBX |
0x43a7b5 MOV %RBX,0xc8(%RSP) |
0x43a7bd LEA 0x8(%RSI,%R12,1),%RSI |
0x43a7c2 MOV %RSI,0xc0(%RSP) |
0x43a7ca LEA 0x8(%R10,%R12,1),%RSI |
0x43a7cf MOV %RSI,0xb8(%RSP) |
0x43a7d7 LEA (%RDI,%R12,1),%RSI |
0x43a7db MOV %RSI,0xb0(%RSP) |
0x43a7e3 ADD %R12,%RCX |
0x43a7e6 MOV %RCX,0xa8(%RSP) |
0x43a7ee LEA (%RDX,%R12,1),%RCX |
0x43a7f2 MOV %RCX,0xa0(%RSP) |
0x43a7fa LEA (%R8,%R12,1),%RCX |
0x43a7fe MOV %RCX,0x98(%RSP) |
0x43a806 LEA (%R9,%R12,1),%RCX |
0x43a80a MOV %RCX,0x90(%RSP) |
0x43a812 ADD 0x40(%RBP),%R12 |
0x43a816 MOV %R12,0x138(%RSP) |
0x43a81e VMOVSD 0xd0e98(%RIP),%XMM28 |
0x43a828 VBROADCASTSD 0xcc196(%RIP),%ZMM3 |
0x43a832 VBROADCASTSD 0xce564(%RIP),%ZMM4 |
0x43a83c XOR %EDI,%EDI |
0x43a83e MOV %R11D,%R13D |
0x43a841 MOV %R11,%R12 |
0x43a844 MOV %R11,0x58(%RSP) |
0x43a849 MOV %R14,0xe8(%RSP) |
0x43a851 MOV %RAX,0x50(%RSP) |
0x43a856 JMP 43a950 |
0x43a85b NOPW %CS:(%RAX,%RAX,1) |
0x43a86a NOPW %CS:(%RAX,%RAX,1) |
0x43a879 NOPL (%RAX) |
(226) 0x43a880 VPXOR %XMM1,%XMM1,%XMM1 |
(226) 0x43a884 VMOVAPD %ZMM1,%ZMM28{%K1} |
(226) 0x43a88a VEXTRACTF32X4 $0x3,%ZMM28,%XMM0 |
(226) 0x43a891 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(226) 0x43a896 VEXTRACTF32X4 $0x2,%ZMM28,%XMM2 |
(226) 0x43a89d VSHUFPD $0x1,%XMM2,%XMM2,%XMM5 |
(226) 0x43a8a2 VMOVAPD %YMM28,%YMM6 |
(226) 0x43a8a8 VEXTRACTF32X4 $0x1,%YMM28,%XMM6 |
(226) 0x43a8af VSHUFPD $0x1,%XMM6,%XMM6,%XMM7 |
(226) 0x43a8b4 VMOVAPD %XMM28,%XMM8 |
(226) 0x43a8ba VSHUFPD $0x1,%XMM28,%XMM28,%XMM9 |
(226) 0x43a8c1 VMINSD %XMM28,%XMM9,%XMM10 |
(226) 0x43a8c7 VCMPSD $0x3,%XMM28,%XMM28,%K1 |
(226) 0x43a8ce VMOVSD %XMM9,%XMM10,%XMM10{%K1} |
(226) 0x43a8d4 VCMPSD $0x3,%XMM10,%XMM10,%K1 |
(226) 0x43a8db VMINSD %XMM10,%XMM6,%XMM8 |
(226) 0x43a8e0 VMOVSD %XMM6,%XMM8,%XMM8{%K1} |
(226) 0x43a8e6 VCMPSD $0x3,%XMM8,%XMM8,%K1 |
(226) 0x43a8ed VMINSD %XMM8,%XMM7,%XMM6 |
(226) 0x43a8f2 VMOVSD %XMM7,%XMM6,%XMM6{%K1} |
(226) 0x43a8f8 VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(226) 0x43a8ff VMINSD %XMM6,%XMM2,%XMM6 |
(226) 0x43a903 VMOVSD %XMM2,%XMM6,%XMM6{%K1} |
(226) 0x43a909 VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(226) 0x43a910 VMINSD %XMM6,%XMM5,%XMM2 |
(226) 0x43a914 VMOVSD %XMM5,%XMM2,%XMM2{%K1} |
(226) 0x43a91a VCMPSD $0x3,%XMM2,%XMM2,%K1 |
(226) 0x43a921 VMINSD %XMM2,%XMM0,%XMM2 |
(226) 0x43a925 VMOVSD %XMM0,%XMM2,%XMM2{%K1} |
(226) 0x43a92b VCMPSD $0x3,%XMM2,%XMM2,%K1 |
(226) 0x43a932 VMINSD %XMM2,%XMM1,%XMM28 |
(226) 0x43a938 VMOVSD %XMM1,%XMM28,%XMM28{%K1} |
(226) 0x43a93e LEA 0x1(%RDI),%ECX |
(226) 0x43a941 INC %R13D |
(226) 0x43a944 CMP 0x3c(%RSP),%EDI |
(226) 0x43a948 MOV %ECX,%EDI |
(226) 0x43a94a JE 43a5d8 |
(226) 0x43a950 TEST %R14D,%R14D |
(226) 0x43a953 JS 43a93e |
(226) 0x43a955 LEA (%R12,%RDI,1),%ECX |
(226) 0x43a959 MOVSXD %ECX,%R11 |
(226) 0x43a95c SUB 0xf0(%RSP),%R11 |
(226) 0x43a964 MOV 0x38(%RBP),%RCX |
(226) 0x43a968 VMOVSD (%RCX,%R11,8),%XMM23 |
(226) 0x43a96f MOV 0xa8(%RBP),%RCX |
(226) 0x43a976 MOV (%RCX),%R9 |
(226) 0x43a979 MOV 0xb0(%RBP),%RCX |
(226) 0x43a980 MOV (%RCX),%RCX |
(226) 0x43a983 MOV %RCX,0x30(%RSP) |
(226) 0x43a988 MOV 0xb8(%RBP),%RCX |
(226) 0x43a98f MOV (%RCX),%R15 |
(226) 0x43a992 MOV 0x80(%RBP),%RCX |
(226) 0x43a999 VMOVSD (%RCX),%XMM26 |
(226) 0x43a99f MOV 0x70(%RBP),%RCX |
(226) 0x43a9a3 VMOVSD (%RCX),%XMM24 |
(226) 0x43a9a9 MOV 0xc0(%RBP),%RCX |
(226) 0x43a9b0 MOV (%RCX),%RBX |
(226) 0x43a9b3 MOV 0xc8(%RBP),%RCX |
(226) 0x43a9ba MOV (%RCX),%R10 |
(226) 0x43a9bd MOV 0x68(%RBP),%RCX |
(226) 0x43a9c1 VMOVSD (%RCX),%XMM25 |
(226) 0x43a9c7 MOV 0xd0(%RBP),%RCX |
(226) 0x43a9ce MOV (%RCX),%RDX |
(226) 0x43a9d1 MOV 0xd8(%RBP),%RCX |
(226) 0x43a9d8 MOV (%RCX),%RSI |
(226) 0x43a9db MOV 0xe0(%RBP),%RCX |
(226) 0x43a9e2 MOV (%RCX),%R8 |
(226) 0x43a9e5 MOV 0x60(%RBP),%RCX |
(226) 0x43a9e9 VMOVSD (%RCX),%XMM22 |
(226) 0x43a9ef VXORPD 0xce3a7(%RIP){1to2},%XMM26,%XMM27 |
(226) 0x43a9f9 TEST %RAX,%RAX |
(226) 0x43a9fc MOV %R13D,0x24(%RSP) |
(226) 0x43aa01 MOV %RDI,0x60(%RSP) |
(226) 0x43aa06 MOV %R15,0x130(%RSP) |
(226) 0x43aa0e MOV %R9,0x128(%RSP) |
(226) 0x43aa16 MOV %RDX,0x120(%RSP) |
(226) 0x43aa1e MOV %R10,0x118(%RSP) |
(226) 0x43aa26 JE 43ae40 |
(226) 0x43aa2c MOV %R11,0x110(%RSP) |
(226) 0x43aa34 MOV %RDX,%RAX |
(226) 0x43aa37 MOV %R10,%R14 |
(226) 0x43aa3a MOVSXD %R13D,%R10 |
(226) 0x43aa3d MOV 0xd0(%RSP),%RCX |
(226) 0x43aa45 LEA (%RCX,%R10,1),%R13 |
(226) 0x43aa49 ADD 0xd8(%RSP),%R10 |
(226) 0x43aa51 VBROADCASTSD %XMM28,%ZMM6 |
(226) 0x43aa57 VBROADCASTSD %XMM26,%ZMM28 |
(226) 0x43aa5d VBROADCASTSD %XMM23,%ZMM29 |
(226) 0x43aa63 VBROADCASTSD %XMM24,%ZMM30 |
(226) 0x43aa69 VBROADCASTSD %XMM25,%ZMM31 |
(226) 0x43aa6f VBROADCASTSD %XMM22,%ZMM2 |
(226) 0x43aa75 VBROADCASTSD %XMM27,%ZMM0 |
(226) 0x43aa7b MOV %R9,%R12 |
(226) 0x43aa7e MOV %RSI,%RDX |
(226) 0x43aa81 IMUL %R13,%RDX |
(226) 0x43aa85 MOV 0xc8(%RSP),%RCX |
(226) 0x43aa8d ADD %RCX,%RDX |
(226) 0x43aa90 MOV %RSI,0x100(%RSP) |
(226) 0x43aa98 MOV %RSI,%R11 |
(226) 0x43aa9b IMUL %R10,%R11 |
(226) 0x43aa9f ADD %RCX,%R11 |
(226) 0x43aaa2 MOV %R14,%RCX |
(226) 0x43aaa5 IMUL %R10,%RCX |
(226) 0x43aaa9 ADD 0xc0(%RSP),%RCX |
(226) 0x43aab1 MOV %RBX,%R14 |
(226) 0x43aab4 IMUL %R10,%R14 |
(226) 0x43aab8 MOV 0xb8(%RSP),%RSI |
(226) 0x43aac0 ADD %RSI,%R14 |
(226) 0x43aac3 MOV %RBX,0xf8(%RSP) |
(226) 0x43aacb IMUL %R13,%RBX |
(226) 0x43aacf ADD %RSI,%RBX |
(226) 0x43aad2 IMUL %R8,%R13 |
(226) 0x43aad6 MOV 0xb0(%RSP),%RSI |
(226) 0x43aade ADD %RSI,%R13 |
(226) 0x43aae1 MOV %R8,0x108(%RSP) |
(226) 0x43aae9 MOV %R8,%RDI |
(226) 0x43aaec IMUL %R10,%RDI |
(226) 0x43aaf0 ADD %RSI,%RDI |
(226) 0x43aaf3 MOV %RAX,%R9 |
(226) 0x43aaf6 IMUL %R10,%R9 |
(226) 0x43aafa ADD 0xa8(%RSP),%R9 |
(226) 0x43ab02 IMUL %R10,%R15 |
(226) 0x43ab06 ADD 0xa0(%RSP),%R15 |
(226) 0x43ab0e MOV 0x30(%RSP),%R8 |
(226) 0x43ab13 IMUL %R10,%R8 |
(226) 0x43ab17 ADD 0x98(%RSP),%R8 |
(226) 0x43ab1f IMUL %R12,%R10 |
(226) 0x43ab23 ADD 0x90(%RSP),%R10 |
(226) 0x43ab2b XOR %ESI,%ESI |
(226) 0x43ab2d MOV 0x50(%RSP),%RAX |
(226) 0x43ab32 JMP 43ac65 |
0x43ab37 NOPW (%RAX,%RAX,1) |
(227) 0x43ab40 MOV 0x138(%RSP),%R12 |
(227) 0x43ab48 VMOVUPD (%R12,%RSI,8),%ZMM14 |
(227) 0x43ab4f VMOVUPD (%R10,%RSI,8),%ZMM16 |
(227) 0x43ab56 VMOVUPD (%R8,%RSI,8),%ZMM17 |
(227) 0x43ab5d VADDPD %ZMM17,%ZMM17,%ZMM17 |
(227) 0x43ab63 VDIVPD (%R15,%RSI,8),%ZMM17,%ZMM17 |
(227) 0x43ab6a VFMADD231PD %ZMM16,%ZMM16,%ZMM17 |
(227) 0x43ab70 VSQRTPD %ZMM17,%ZMM16 |
(227) 0x43ab76 VCMPPD $0x2,%ZMM16,%ZMM28,%K2 |
(227) 0x43ab7d VBLENDMPD %ZMM16,%ZMM28,%ZMM16{%K2} |
(227) 0x43ab83 VCMPPD $0x2,%ZMM29,%ZMM14,%K2 |
(227) 0x43ab8a VBLENDMPD %ZMM14,%ZMM29,%ZMM14{%K2} |
(227) 0x43ab90 VMULPD %ZMM14,%ZMM30,%ZMM14 |
(227) 0x43ab96 VDIVPD %ZMM16,%ZMM14,%ZMM14 |
(227) 0x43ab9c VMULPD %ZMM31,%ZMM1,%ZMM16 |
(227) 0x43aba2 VANDPD %ZMM3,%ZMM10,%ZMM10 |
(227) 0x43aba8 VANDPD %ZMM3,%ZMM11,%ZMM11 |
(227) 0x43abae VMULPD %ZMM28,%ZMM12,%ZMM12 |
(227) 0x43abb4 VCMPPD $0x2,%ZMM11,%ZMM12,%K2 |
(227) 0x43abbb VBLENDMPD %ZMM11,%ZMM12,%ZMM11{%K2} |
(227) 0x43abc1 VCMPPD $0x2,%ZMM10,%ZMM11,%K2 |
(227) 0x43abc8 VMOVAPD %ZMM10,%ZMM11{%K2} |
(227) 0x43abce VDIVPD %ZMM11,%ZMM16,%ZMM10 |
(227) 0x43abd4 VMULPD %ZMM2,%ZMM1,%ZMM1 |
(227) 0x43abda VANDPD %ZMM3,%ZMM7,%ZMM7 |
(227) 0x43abe0 VANDPD %ZMM3,%ZMM9,%ZMM9 |
(227) 0x43abe6 VCMPPD $0x2,%ZMM9,%ZMM12,%K2 |
(227) 0x43abed VMOVAPD %ZMM9,%ZMM12{%K2} |
(227) 0x43abf3 VCMPPD $0x2,%ZMM7,%ZMM12,%K2 |
(227) 0x43abfa VMOVAPD %ZMM7,%ZMM12{%K2} |
(227) 0x43ac00 VDIVPD %ZMM12,%ZMM1,%ZMM7 |
(227) 0x43ac06 VBROADCASTSD %XMM13,%ZMM1 |
(227) 0x43ac0c VXORPD %ZMM4,%ZMM1,%ZMM9 |
(227) 0x43ac12 VBROADCASTSD %XMM8,%ZMM1 |
(227) 0x43ac18 VDIVPD %ZMM5,%ZMM9,%ZMM1{%K1} |
(227) 0x43ac1e VCMPPD $0x2,%ZMM1,%ZMM7,%K1 |
(227) 0x43ac25 VMOVAPD %ZMM7,%ZMM1{%K1} |
(227) 0x43ac2b VCMPPD $0x2,%ZMM1,%ZMM10,%K1 |
(227) 0x43ac32 VMOVAPD %ZMM10,%ZMM1{%K1} |
(227) 0x43ac38 VCMPPD $0x2,%ZMM1,%ZMM14,%K1 |
(227) 0x43ac3f VMOVAPD %ZMM14,%ZMM1{%K1} |
(227) 0x43ac45 VCMPPD $0x2,%ZMM1,%ZMM6,%K1 |
(227) 0x43ac4c VMOVAPD %ZMM6,%ZMM1{%K1} |
(227) 0x43ac52 ADD $0x8,%RSI |
(227) 0x43ac56 VMOVAPD %ZMM1,%ZMM6 |
(227) 0x43ac5c CMP %RAX,%RSI |
(227) 0x43ac5f JAE 43ad40 |
(227) 0x43ac65 VMOVUPD -0x8(%RBX,%RSI,8),%ZMM1 |
(227) 0x43ac70 VMOVUPD (%RBX,%RSI,8),%ZMM5 |
(227) 0x43ac77 VADDPD -0x8(%R14,%RSI,8),%ZMM1,%ZMM1 |
(227) 0x43ac82 VMULPD -0x8(%RCX,%RSI,8),%ZMM1,%ZMM10 |
(227) 0x43ac8d VADDPD (%R14,%RSI,8),%ZMM5,%ZMM1 |
(227) 0x43ac94 VMULPD (%RCX,%RSI,8),%ZMM1,%ZMM11 |
(227) 0x43ac9b VMOVUPD (%R9,%RSI,8),%ZMM12 |
(227) 0x43aca2 VADDPD %ZMM12,%ZMM12,%ZMM1 |
(227) 0x43aca8 VMOVUPD (%R11,%RSI,8),%ZMM5 |
(227) 0x43acaf VADDPD -0x8(%R11,%RSI,8),%ZMM5,%ZMM5 |
(227) 0x43acba VMULPD (%RDI,%RSI,8),%ZMM5,%ZMM7 |
(227) 0x43acc1 VMOVUPD (%RDX,%RSI,8),%ZMM5 |
(227) 0x43acc8 VADDPD -0x8(%RDX,%RSI,8),%ZMM5,%ZMM5 |
(227) 0x43acd3 VMULPD (%R13,%RSI,8),%ZMM5,%ZMM9 |
(227) 0x43acdb VADDPD %ZMM7,%ZMM10,%ZMM5 |
(227) 0x43ace1 VSUBPD %ZMM5,%ZMM11,%ZMM5 |
(227) 0x43ace7 VADDPD %ZMM9,%ZMM5,%ZMM5 |
(227) 0x43aced VDIVPD %ZMM1,%ZMM5,%ZMM5 |
(227) 0x43acf3 VCMPPD $0x1,%ZMM0,%ZMM5,%K1 |
(227) 0x43acfa KORTESTB %K1,%K1 |
(227) 0x43acfe JB 43ad0a |
(227) 0x43ad00 MOV 0x78(%RBP),%R12 |
(227) 0x43ad04 VMOVSD (%R12),%XMM8 |
(227) 0x43ad0a KORTESTB %K1,%K1 |
(227) 0x43ad0e JE 43ab40 |
(227) 0x43ad14 MOV 0x58(%RBP),%R12 |
(227) 0x43ad18 VMOVSD (%R12),%XMM13 |
(227) 0x43ad1e JMP 43ab40 |
0x43ad23 NOPW %CS:(%RAX,%RAX,1) |
0x43ad32 NOPW %CS:(%RAX,%RAX,1) |
(226) 0x43ad40 VMOVAPD %XMM1,%XMM0 |
(226) 0x43ad44 VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 |
(226) 0x43ad49 VMINSD %XMM1,%XMM2,%XMM5 |
(226) 0x43ad4d VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(226) 0x43ad54 VMOVSD %XMM2,%XMM5,%XMM5{%K1} |
(226) 0x43ad5a VCMPSD $0x3,%XMM5,%XMM5,%K1 |
(226) 0x43ad61 VMOVAPD %YMM1,%YMM0 |
(226) 0x43ad65 VEXTRACTF128 $0x1,%YMM1,%XMM0 |
(226) 0x43ad6b VMINSD %XMM5,%XMM0,%XMM2 |
(226) 0x43ad6f VMOVSD %XMM0,%XMM2,%XMM2{%K1} |
(226) 0x43ad75 VCMPSD $0x3,%XMM2,%XMM2,%K1 |
(226) 0x43ad7c VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(226) 0x43ad81 VMINSD %XMM2,%XMM0,%XMM2 |
(226) 0x43ad85 VMOVSD %XMM0,%XMM2,%XMM2{%K1} |
(226) 0x43ad8b VCMPSD $0x3,%XMM2,%XMM2,%K1 |
(226) 0x43ad92 VEXTRACTF32X4 $0x2,%ZMM1,%XMM0 |
(226) 0x43ad99 VMINSD %XMM2,%XMM0,%XMM2 |
(226) 0x43ad9d VMOVSD %XMM0,%XMM2,%XMM2{%K1} |
(226) 0x43ada3 VCMPSD $0x3,%XMM2,%XMM2,%K1 |
(226) 0x43adaa VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(226) 0x43adaf VMINSD %XMM2,%XMM0,%XMM2 |
(226) 0x43adb3 VMOVSD %XMM0,%XMM2,%XMM2{%K1} |
(226) 0x43adb9 VCMPSD $0x3,%XMM2,%XMM2,%K1 |
(226) 0x43adc0 VEXTRACTF32X4 $0x3,%ZMM1,%XMM0 |
(226) 0x43adc7 VMINSD %XMM2,%XMM0,%XMM1 |
(226) 0x43adcb VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(226) 0x43add1 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(226) 0x43add8 VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(226) 0x43addd VMINSD %XMM1,%XMM0,%XMM28 |
(226) 0x43ade3 VMOVSD %XMM0,%XMM28,%XMM28{%K1} |
(226) 0x43ade9 MOV %RAX,%R10 |
(226) 0x43adec CMP 0xe0(%RSP),%RAX |
(226) 0x43adf4 MOV 0x58(%RSP),%R12 |
(226) 0x43adf9 MOV 0xe8(%RSP),%R14 |
(226) 0x43ae01 MOV 0x24(%RSP),%R13D |
(226) 0x43ae06 MOV 0x60(%RSP),%RDI |
(226) 0x43ae0b MOV 0x110(%RSP),%R11 |
(226) 0x43ae13 MOV 0x30(%RSP),%R15 |
(226) 0x43ae18 MOV 0x108(%RSP),%R8 |
(226) 0x43ae20 MOV 0x100(%RSP),%RSI |
(226) 0x43ae28 MOV 0xf8(%RSP),%RBX |
(226) 0x43ae30 JE 43a93e |
(226) 0x43ae36 JMP 43ae4d |
0x43ae38 NOPL (%RAX,%RAX,1) |
(226) 0x43ae40 MOV 0x30(%RSP),%R15 |
(226) 0x43ae45 XOR %R10D,%R10D |
(226) 0x43ae48 MOV 0x50(%RSP),%RAX |
(226) 0x43ae4d VBROADCASTSD %XMM28,%ZMM28 |
(226) 0x43ae53 VPBROADCASTQ %R10,%ZMM0 |
(226) 0x43ae59 VMOVDQA64 0x140(%RSP),%ZMM1 |
(226) 0x43ae61 VPSUBQ %ZMM0,%ZMM1,%ZMM0 |
(226) 0x43ae67 VPCMPNLEUQ 0xd088e(%RIP),%ZMM0,%K1 |
(226) 0x43ae72 KORTESTB %K1,%K1 |
(226) 0x43ae76 JE 43a880 |
(226) 0x43ae7c ADD 0x80(%RSP),%R10 |
(226) 0x43ae84 SUB 0x88(%RSP),%R10 |
(226) 0x43ae8c LEA 0x1(%R11),%RCX |
(226) 0x43ae90 MOV %RBX,%RDX |
(226) 0x43ae93 IMUL %RCX,%RDX |
(226) 0x43ae97 MOV %RSI,%R13 |
(226) 0x43ae9a MOV 0x10(%RBP),%RSI |
(226) 0x43ae9e ADD %RSI,%RDX |
(226) 0x43aea1 VMOVUPD (%RDX,%R10,8),%ZMM0{%K1}{z} |
(226) 0x43aea8 VMOVUPD 0x8(%RDX,%R10,8),%ZMM1{%K1}{z} |
(226) 0x43aeb3 IMUL %R11,%RBX |
(226) 0x43aeb7 ADD %RSI,%RBX |
(226) 0x43aeba VMOVUPD (%RBX,%R10,8),%ZMM2{%K1}{z} |
(226) 0x43aec1 VMOVUPD 0x8(%RBX,%R10,8),%ZMM5{%K1}{z} |
(226) 0x43aecc MOV 0x118(%RSP),%RDX |
(226) 0x43aed4 IMUL %R11,%RDX |
(226) 0x43aed8 ADD 0x50(%RBP),%RDX |
(226) 0x43aedc VMOVUPD (%RDX,%R10,8),%ZMM6{%K1}{z} |
(226) 0x43aee3 VMOVUPD 0x8(%RDX,%R10,8),%ZMM7{%K1}{z} |
(226) 0x43aeee MOV 0x120(%RSP),%RDX |
(226) 0x43aef6 IMUL %R11,%RDX |
(226) 0x43aefa ADD 0x30(%RBP),%RDX |
(226) 0x43aefe VMOVUPD (%RDX,%R10,8),%ZMM8{%K1}{z} |
(226) 0x43af05 MOV %R13,%RDX |
(226) 0x43af08 IMUL %R11,%RDX |
(226) 0x43af0c MOV 0x48(%RSP),%RDI |
(226) 0x43af11 ADD %RDI,%RDX |
(226) 0x43af14 VMOVUPD 0x8(%RDX,%R10,8),%ZMM9{%K1}{z} |
(226) 0x43af1f VMOVUPD (%RDX,%R10,8),%ZMM10{%K1}{z} |
(226) 0x43af26 MOV %R8,%RDX |
(226) 0x43af29 IMUL %R11,%RDX |
(226) 0x43af2d MOV 0x48(%RBP),%RSI |
(226) 0x43af31 ADD %RSI,%RDX |
(226) 0x43af34 VMOVUPD (%RDX,%R10,8),%ZMM11{%K1}{z} |
(226) 0x43af3b IMUL %RCX,%R13 |
(226) 0x43af3f ADD %RDI,%R13 |
(226) 0x43af42 VMOVUPD 0x8(%R13,%R10,8),%ZMM12{%K1}{z} |
(226) 0x43af4d VMOVUPD (%R13,%R10,8),%ZMM13{%K1}{z} |
(226) 0x43af55 IMUL %RCX,%R8 |
(226) 0x43af59 ADD %RSI,%R8 |
(226) 0x43af5c VMOVUPD (%R8,%R10,8),%ZMM14{%K1}{z} |
(226) 0x43af63 VMOVAPD 0x340(%RSP),%ZMM16 |
(226) 0x43af6b VMOVAPD %ZMM0,%ZMM16{%K1} |
(226) 0x43af71 VMOVAPD 0x300(%RSP),%ZMM0 |
(226) 0x43af79 VMOVAPD %ZMM2,%ZMM0{%K1} |
(226) 0x43af7f VMOVAPD 0x2c0(%RSP),%ZMM2 |
(226) 0x43af87 VMOVAPD %ZMM6,%ZMM2{%K1} |
(226) 0x43af8d VMOVAPD 0x280(%RSP),%ZMM6 |
(226) 0x43af95 VMOVAPD %ZMM1,%ZMM6{%K1} |
(226) 0x43af9b VMOVAPD 0x240(%RSP),%ZMM1 |
(226) 0x43afa3 VMOVAPD %ZMM5,%ZMM1{%K1} |
(226) 0x43afa9 VMOVAPD 0x200(%RSP),%ZMM5 |
(226) 0x43afb1 VMOVAPD %ZMM7,%ZMM5{%K1} |
(226) 0x43afb7 VMOVAPD %ZMM8,%ZMM15{%K1} |
(226) 0x43afbd VMOVAPD %ZMM16,0x340(%RSP) |
(226) 0x43afc5 VMOVAPD %ZMM0,0x300(%RSP) |
(226) 0x43afcd VADDPD %ZMM0,%ZMM16,%ZMM0 |
(226) 0x43afd3 VMOVAPD %ZMM2,0x2c0(%RSP) |
(226) 0x43afdb VMULPD %ZMM0,%ZMM2,%ZMM31 |
(226) 0x43afe1 VMOVAPD 0x1c0(%RSP),%ZMM7 |
(226) 0x43afe9 VMOVAPD %ZMM9,%ZMM7{%K1} |
(226) 0x43afef VMOVAPD %ZMM6,0x280(%RSP) |
(226) 0x43aff7 VMOVAPD %ZMM1,0x240(%RSP) |
(226) 0x43afff VADDPD %ZMM1,%ZMM6,%ZMM0 |
(226) 0x43b005 VMOVAPD %ZMM5,0x200(%RSP) |
(226) 0x43b00d VMULPD %ZMM5,%ZMM0,%ZMM5 |
(226) 0x43b013 VMOVAPD 0x180(%RSP),%ZMM0 |
(226) 0x43b01b VMOVAPD %ZMM10,%ZMM0{%K1} |
(226) 0x43b021 VADDPD %ZMM15,%ZMM15,%ZMM2 |
(226) 0x43b027 VMOVAPD %ZMM11,%ZMM18{%K1} |
(226) 0x43b02d VMOVAPD %ZMM7,0x1c0(%RSP) |
(226) 0x43b035 VMOVAPD %ZMM0,0x180(%RSP) |
(226) 0x43b03d VADDPD %ZMM0,%ZMM7,%ZMM0 |
(226) 0x43b043 VMULPD %ZMM0,%ZMM18,%ZMM29 |
(226) 0x43b049 VMOVAPD %ZMM12,%ZMM19{%K1} |
(226) 0x43b04f VMOVAPD %ZMM13,%ZMM20{%K1} |
(226) 0x43b055 VADDPD %ZMM20,%ZMM19,%ZMM0 |
(226) 0x43b05b VMOVAPD %ZMM14,%ZMM21{%K1} |
(226) 0x43b061 VMULPD %ZMM21,%ZMM0,%ZMM30 |
(226) 0x43b067 VADDPD %ZMM29,%ZMM31,%ZMM0 |
(226) 0x43b06d VSUBPD %ZMM0,%ZMM5,%ZMM0 |
(226) 0x43b073 VADDPD %ZMM30,%ZMM0,%ZMM0 |
(226) 0x43b079 VDIVPD %ZMM2,%ZMM0,%ZMM0 |
(226) 0x43b07f VBROADCASTSD %XMM27,%ZMM6 |
(226) 0x43b085 VCMPPD $0x5,%ZMM6,%ZMM0,%K0 |
(226) 0x43b08c KTESTB %K0,%K1 |
(226) 0x43b090 JE 43b09a |
(226) 0x43b092 MOV 0x78(%RBP),%RCX |
(226) 0x43b096 VMOVSD (%RCX),%XMM1 |
(226) 0x43b09a VCMPPD $0x1,%ZMM6,%ZMM0,%K2{%K1} |
(226) 0x43b0a1 KORTESTB %K2,%K2 |
(226) 0x43b0a5 VMOVAPD 0x440(%RSP),%ZMM9 |
(226) 0x43b0ad VMOVAPD 0x400(%RSP),%ZMM8 |
(226) 0x43b0b5 VMOVAPD 0x3c0(%RSP),%ZMM7 |
(226) 0x43b0bd VMOVAPD 0x380(%RSP),%ZMM10 |
(226) 0x43b0c5 MOV 0x128(%RSP),%RDX |
(226) 0x43b0cd MOV %R15,%R8 |
(226) 0x43b0d0 MOV 0x130(%RSP),%R15 |
(226) 0x43b0d8 JE 43b0e4 |
(226) 0x43b0da MOV 0x58(%RBP),%RCX |
(226) 0x43b0de VMOVSD (%RCX),%XMM27 |
(226) 0x43b0e4 IMUL %R11,%RDX |
(226) 0x43b0e8 ADD 0x18(%RBP),%RDX |
(226) 0x43b0ec VMOVUPD (%RDX,%R10,8),%ZMM6{%K1}{z} |
(226) 0x43b0f3 VMOVAPD %ZMM6,%ZMM8{%K1} |
(226) 0x43b0f9 IMUL %R11,%R8 |
(226) 0x43b0fd ADD 0x20(%RBP),%R8 |
(226) 0x43b101 VMOVUPD (%R8,%R10,8),%ZMM6{%K1}{z} |
(226) 0x43b108 VMOVAPD %ZMM6,%ZMM7{%K1} |
(226) 0x43b10e VMOVAPD %ZMM7,0x3c0(%RSP) |
(226) 0x43b116 VADDPD %ZMM7,%ZMM7,%ZMM6 |
(226) 0x43b11c IMUL %R11,%R15 |
(226) 0x43b120 ADD 0x28(%RBP),%R15 |
(226) 0x43b124 VMOVUPD (%R15,%R10,8),%ZMM7{%K1}{z} |
(226) 0x43b12b VMOVAPD %ZMM7,%ZMM10{%K1} |
(226) 0x43b131 VMOVAPD %ZMM10,0x380(%RSP) |
(226) 0x43b139 VDIVPD %ZMM10,%ZMM6,%ZMM6 |
(226) 0x43b13f MOV 0x40(%RBP),%RCX |
(226) 0x43b143 VMOVUPD (%RCX,%R10,8),%ZMM7{%K1}{z} |
(226) 0x43b14a VMOVAPD %ZMM8,0x400(%RSP) |
(226) 0x43b152 VFMADD231PD %ZMM8,%ZMM8,%ZMM6 |
(226) 0x43b158 VSQRTPD %ZMM6,%ZMM6 |
(226) 0x43b15e VMOVAPD %ZMM7,%ZMM9{%K1} |
(226) 0x43b164 VBROADCASTSD %XMM26,%ZMM7 |
(226) 0x43b16a VMAXPD %ZMM7,%ZMM6,%ZMM6 |
(226) 0x43b170 VBROADCASTSD %XMM23,%ZMM8 |
(226) 0x43b176 VMOVAPD %ZMM9,0x440(%RSP) |
(226) 0x43b17e VMINPD %ZMM8,%ZMM9,%ZMM8 |
(226) 0x43b184 VBROADCASTSD %XMM24,%ZMM9 |
(226) 0x43b18a VMULPD %ZMM8,%ZMM9,%ZMM8 |
(226) 0x43b190 VDIVPD %ZMM6,%ZMM8,%ZMM6 |
(226) 0x43b196 VBROADCASTSD %XMM25,%ZMM8 |
(226) 0x43b19c VMULPD %ZMM8,%ZMM2,%ZMM8 |
(226) 0x43b1a2 VANDPD %ZMM3,%ZMM31,%ZMM9 |
(226) 0x43b1a8 VANDPD %ZMM3,%ZMM5,%ZMM5 |
(226) 0x43b1ae VMULPD %ZMM7,%ZMM15,%ZMM7 |
(226) 0x43b1b4 VCMPPD $0x2,%ZMM5,%ZMM7,%K3 |
(226) 0x43b1bb VBLENDMPD %ZMM5,%ZMM7,%ZMM5{%K3} |
(226) 0x43b1c1 VCMPPD $0x2,%ZMM9,%ZMM5,%K3 |
(226) 0x43b1c8 VMOVAPD %ZMM9,%ZMM5{%K3} |
(226) 0x43b1ce VDIVPD %ZMM5,%ZMM8,%ZMM5 |
(226) 0x43b1d4 VBROADCASTSD %XMM22,%ZMM8 |
(226) 0x43b1da VMULPD %ZMM8,%ZMM2,%ZMM2 |
(226) 0x43b1e0 VANDPD %ZMM3,%ZMM29,%ZMM8 |
(226) 0x43b1e6 VANDPD %ZMM3,%ZMM30,%ZMM9 |
(226) 0x43b1ec VCMPPD $0x2,%ZMM9,%ZMM7,%K3 |
(226) 0x43b1f3 VMOVAPD %ZMM9,%ZMM7{%K3} |
(226) 0x43b1f9 VCMPPD $0x2,%ZMM8,%ZMM7,%K3 |
(226) 0x43b200 VMOVAPD %ZMM8,%ZMM7{%K3} |
(226) 0x43b206 VDIVPD %ZMM7,%ZMM2,%ZMM2 |
(226) 0x43b20c VBROADCASTSD %XMM27,%ZMM7 |
(226) 0x43b212 VXORPD %ZMM4,%ZMM7,%ZMM7 |
(226) 0x43b218 VBROADCASTSD %XMM1,%ZMM1 |
(226) 0x43b21e VDIVPD %ZMM0,%ZMM7,%ZMM1{%K2} |
(226) 0x43b224 VCMPPD $0x2,%ZMM1,%ZMM2,%K2 |
(226) 0x43b22b VMOVAPD %ZMM2,%ZMM1{%K2} |
(226) 0x43b231 VCMPPD $0x2,%ZMM1,%ZMM5,%K2 |
(226) 0x43b238 VMOVAPD %ZMM5,%ZMM1{%K2} |
(226) 0x43b23e VCMPPD $0x2,%ZMM1,%ZMM6,%K2 |
(226) 0x43b245 VMOVAPD %ZMM6,%ZMM1{%K2} |
(226) 0x43b24b VCMPPD $0x2,%ZMM1,%ZMM28,%K2 |
(226) 0x43b252 VMOVAPD %ZMM28,%ZMM1{%K2} |
(226) 0x43b258 MOV 0x58(%RSP),%R12 |
(226) 0x43b25d MOV 0x24(%RSP),%R13D |
(226) 0x43b262 MOV 0x60(%RSP),%RDI |
(226) 0x43b267 JMP 43a884 |
0x43b26c NOPW %CS:(%RAX,%RAX,1) |
0x43b276 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | calc_dt_kernel.f90:89-133 |
Module | exec |
nb instructions | 187 |
nb uops | 193 |
loop length | 930 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 3 |
nb stack references | 45 |
micro-operation queue | 32.17 cycles |
front end | 32.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 13.50 | 13.40 | 12.33 | 12.33 | 22.50 | 13.40 | 13.30 | 22.50 | 22.50 | 22.50 | 13.40 | 12.33 |
cycles | 13.50 | 13.40 | 12.33 | 12.33 | 22.50 | 13.40 | 13.30 | 22.50 | 22.50 | 22.50 | 13.40 | 12.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 31.32-31.37 |
Stall cycles | 0.00 |
Front-end | 32.17 |
Dispatch | 22.50 |
Overall L1 | 32.17 |
all | 4% |
load | 0% |
store | 3% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 3% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 5% |
all | 12% |
load | 6% |
store | 14% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 10% |
store | 14% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x4c0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x90(%RBP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R14D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVL $0,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 43a652 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x132> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x48(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x4c(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x34(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x30(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74a3d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4045a0 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x2c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R11D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 43a680 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x160> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0xd10e8(%RIP),%XMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM28,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x74a3f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 404190 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x7a3060,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x70(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74a410,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x43a510,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 404780 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 43a652 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x132> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0x68(%RSP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMINSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x7a3060,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x74a430,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404900 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74a450,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404660 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xa0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x20,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $-0x200000000,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
LEA (%R12,%RCX,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RDI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x20,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOVSXD (%RSI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R14D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x2,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %EAX,%EBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7ffffff8,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $-0x1,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNS %RDX,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x1,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %R13,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x200000000,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV %R9,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R12,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RDX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RDI,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x20,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RSI,%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV $-0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SUB %R8,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVG %R13,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R15,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x48(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RCX,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RDX,%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %RBX,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQA64 %ZMM0,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
NEG %R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x8(%RBX,%R12,1),%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RBX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x8(%RSI,%R12,1),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x8(%R10,%R12,1),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RSI,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RDI,%R12,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RDX,%R12,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R8,%R12,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R9,%R12,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0x40(%RBP),%R12 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R12,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0xd0e98(%RIP),%XMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD 0xcc196(%RIP),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xce564(%RIP),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 43a950 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x430> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | calc_dt_kernel.f90:89-133 |
Module | exec |
nb instructions | 187 |
nb uops | 193 |
loop length | 930 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 3 |
nb stack references | 45 |
micro-operation queue | 32.17 cycles |
front end | 32.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 13.50 | 13.40 | 12.33 | 12.33 | 22.50 | 13.40 | 13.30 | 22.50 | 22.50 | 22.50 | 13.40 | 12.33 |
cycles | 13.50 | 13.40 | 12.33 | 12.33 | 22.50 | 13.40 | 13.30 | 22.50 | 22.50 | 22.50 | 13.40 | 12.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 31.32-31.37 |
Stall cycles | 0.00 |
Front-end | 32.17 |
Dispatch | 22.50 |
Overall L1 | 32.17 |
all | 4% |
load | 0% |
store | 3% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 3% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 5% |
all | 12% |
load | 6% |
store | 14% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 10% |
store | 14% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x4c0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x90(%RBP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R14D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVL $0,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 43a652 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x132> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x48(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x4c(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x34(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x30(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74a3d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4045a0 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x2c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R11D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 43a680 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x160> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0xd10e8(%RIP),%XMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM28,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x74a3f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 404190 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x7a3060,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x70(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74a410,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x43a510,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 404780 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 43a652 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x132> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0x68(%RSP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMINSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x7a3060,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x74a430,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404900 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74a450,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404660 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xa0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x20,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $-0x200000000,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
LEA (%R12,%RCX,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RDI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x20,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAR $0x20,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOVSXD (%RSI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R14D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x2,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %EAX,%EBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7ffffff8,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $-0x1,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNS %RDX,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x1,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %R13,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x200000000,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV %R9,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R12,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RDX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RDI,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x20,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RSI,%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV $-0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SUB %R8,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVG %R13,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R15,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x48(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %RCX,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SHR $0x20,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
IMUL %RDX,%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %RBX,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQA64 %ZMM0,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
NEG %R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x8(%RBX,%R12,1),%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RBX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x8(%RSI,%R12,1),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x8(%R10,%R12,1),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RSI,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RDI,%R12,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RDX,%R12,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R8,%R12,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R9,%R12,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0x40(%RBP),%R12 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R12,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0xd0e98(%RIP),%XMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD 0xcc196(%RIP),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xce564(%RIP),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 43a950 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x430> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼calc_dt_kernel_.DIR.OMP.PARALLEL.2– | 3.34 | 2.51 |
▼Loop 226 - calc_dt_kernel.f90:92-129 - exec– | 0 | 0 |
○Loop 227 - calc_dt_kernel.f90:92-129 - exec | 3.34 | 2.5 |