Loop Id: 172 | Module: exec | Source: advec_mom_kernel.f90:81-177 [...] | Coverage: 0.01% |
---|
Loop Id: 172 | Module: exec | Source: advec_mom_kernel.f90:81-177 [...] | Coverage: 0.01% |
---|
0x434dc0 VMOVAPD %ZMM28,%ZMM0{%K3}{z} |
0x434dc6 VSUBPD %ZMM26,%ZMM10,%ZMM6 |
0x434dcc VFMADD213PD %ZMM22,%ZMM0,%ZMM6 |
0x434dd2 VMULPD %ZMM24,%ZMM6,%ZMM0 |
0x434dd8 IMUL 0x30(%RSP),%RAX |
0x434dde ADD 0xd8(%RSP),%RAX |
0x434de6 VMOVUPD %ZMM0,(%RAX,%RSI,8){%K1} |
0x434ded ADD 0x30(%RSP),%R14 |
0x434df2 ADD %RDI,%RDX |
0x434df5 CMP 0x280(%RSP),%RCX |
0x434dfd LEA 0x1(%RCX),%RCX |
0x434e01 JE 431ff2 |
0x434e07 TEST %R8,%R8 |
0x434e0a JE 435040 |
0x434e10 LEA (%R9,%RCX,1),%RAX |
0x434e14 SUB %R12,%RAX |
0x434e17 MOV %R10,%RSI |
0x434e1a IMUL %RAX,%RSI |
0x434e1e IMUL 0x3c0(%RSP),%RAX |
0x434e27 ADD 0xb0(%RSP),%RSI |
0x434e2f ADD 0xf8(%RSP),%RAX |
0x434e37 XOR %R15D,%R15D |
0x434e3a JMP 434e73 |
(173) 0x434e40 VCMPPD $0x1,%ZMM29,%ZMM12,%K1 |
(173) 0x434e47 VMOVAPD %ZMM30,%ZMM0{%K1}{z} |
(173) 0x434e4d VSUBPD %ZMM27,%ZMM10,%ZMM6 |
(173) 0x434e53 VFMADD213PD %ZMM26,%ZMM0,%ZMM6 |
(173) 0x434e59 VMULPD %ZMM25,%ZMM6,%ZMM0 |
(173) 0x434e5f VMOVUPD %ZMM0,(%R14,%R15,8) |
(173) 0x434e66 ADD $0x8,%R15 |
(173) 0x434e6a CMP %R8,%R15 |
(173) 0x434e6d JGE 435000 |
(173) 0x434e73 VMOVUPD (%RDX,%R15,8),%ZMM25 |
(173) 0x434e7a VFPCLASSPD $0x50,%ZMM25,%K1 |
(173) 0x434e81 LEA (%R13,%R15,1),%EBX |
(173) 0x434e86 VPBROADCASTD %EBX,%YMM6 |
(173) 0x434e8c VPADDD %YMM7,%YMM6,%YMM28 |
(173) 0x434e92 VPADDD %YMM16,%YMM6,%YMM8 |
(173) 0x434e98 VPBLENDMD %YMM8,%YMM28,%YMM29{%K1} |
(173) 0x434e9e VMOVDQA32 %YMM28,%YMM8{%K1} |
(173) 0x434ea4 VPMOVSXDQ %YMM8,%ZMM8 |
(173) 0x434eaa VPSUBQ %ZMM2,%ZMM8,%ZMM8 |
(173) 0x434eb0 KXNORW %K0,%K0,%K2 |
(173) 0x434eb4 VXORPD %XMM27,%XMM27,%XMM27 |
(173) 0x434eba VGATHERQPD (%RSI,%ZMM8,8),%ZMM27{%K2} |
(173) 0x434ec1 KXNORW %K0,%K0,%K2 |
(173) 0x434ec5 VXORPD %XMM26,%XMM26,%XMM26 |
(173) 0x434ecb VGATHERQPD (%RAX,%ZMM8,8),%ZMM26{%K2} |
(173) 0x434ed2 VPADDD %YMM6,%YMM15,%YMM8 |
(173) 0x434ed6 VMOVDQA64 %YMM8,%YMM30 |
(173) 0x434edc VPADDD %YMM17,%YMM6,%YMM30{%K1} |
(173) 0x434ee2 VANDPD %ZMM9,%ZMM25,%ZMM6 |
(173) 0x434ee8 VPMOVSXDQ %YMM30,%ZMM30 |
(173) 0x434eee VPSUBQ %ZMM2,%ZMM30,%ZMM30 |
(173) 0x434ef4 KXNORW %K0,%K0,%K2 |
(173) 0x434ef8 VXORPD %XMM31,%XMM31,%XMM31 |
(173) 0x434efe VGATHERQPD (%RAX,%ZMM30,8),%ZMM31{%K2} |
(173) 0x434f05 VDIVPD %ZMM27,%ZMM6,%ZMM27 |
(173) 0x434f0b VPMOVSXDQ %YMM29,%ZMM6 |
(173) 0x434f11 VPSUBQ %ZMM2,%ZMM6,%ZMM6 |
(173) 0x434f17 KXNORW %K0,%K0,%K2 |
(173) 0x434f1b VPXORD %XMM29,%XMM29,%XMM29 |
(173) 0x434f21 VGATHERQPD (%RAX,%ZMM6,8),%ZMM29{%K2} |
(173) 0x434f28 VXORPD %XMM30,%XMM30,%XMM30 |
(173) 0x434f2e VSUBPD %ZMM31,%ZMM26,%ZMM6 |
(173) 0x434f34 VSUBPD %ZMM26,%ZMM29,%ZMM31 |
(173) 0x434f3a VMULPD %ZMM6,%ZMM31,%ZMM29 |
(173) 0x434f40 VCMPPD $0x1,%ZMM29,%ZMM30,%K0 |
(173) 0x434f47 KORTESTB %K0,%K0 |
(173) 0x434f4b JE 434e40 |
(173) 0x434f51 VCMPPD $0x1,%ZMM29,%ZMM12,%K2 |
(173) 0x434f58 VMOVDQA32 %YMM28,%YMM8{%K1} |
(173) 0x434f5e VMOVUPD (%R11,%R15,8),%ZMM28{%K2}{z} |
(173) 0x434f65 VANDPD %ZMM9,%ZMM6,%ZMM6 |
(173) 0x434f6b VANDPD %ZMM9,%ZMM31,%ZMM30 |
(173) 0x434f71 VPMOVSXDQ %YMM8,%ZMM8 |
(173) 0x434f77 VPSUBQ %ZMM2,%ZMM8,%ZMM8 |
(173) 0x434f7d VPXOR %XMM0,%XMM0,%XMM0 |
(173) 0x434f81 MOV 0x38(%RSP),%RBX |
(173) 0x434f86 VGATHERQPD (%RBX,%ZMM8,8),%ZMM0{%K2} |
(173) 0x434f8d VSUBPD %ZMM27,%ZMM11,%ZMM8 |
(173) 0x434f93 VMULPD %ZMM8,%ZMM30,%ZMM8 |
(173) 0x434f99 VDIVPD %ZMM28,%ZMM8,%ZMM8 |
(173) 0x434f9f VCMPPD $0x2,%ZMM30,%ZMM6,%K1 |
(173) 0x434fa6 VMOVAPD %ZMM6,%ZMM30{%K1} |
(173) 0x434fac VFMADD213PD %ZMM6,%ZMM27,%ZMM6 |
(173) 0x434fb2 VDIVPD %ZMM0,%ZMM6,%ZMM0 |
(173) 0x434fb8 VADDPD %ZMM8,%ZMM0,%ZMM0 |
(173) 0x434fbe VMULPD %ZMM13,%ZMM28,%ZMM6 |
(173) 0x434fc4 VMULPD %ZMM0,%ZMM6,%ZMM0 |
(173) 0x434fca VCMPPD $0x2,%ZMM30,%ZMM0,%K1 |
(173) 0x434fd1 VMOVAPD %ZMM0,%ZMM30{%K1} |
(173) 0x434fd7 VFPCLASSPD $0x56,%ZMM31,%K1 |
(173) 0x434fde VXORPD %ZMM14,%ZMM30,%ZMM30{%K1} |
(173) 0x434fe4 JMP 434e40 |
0x435000 MOV %R8,%RSI |
0x435003 CMP %R8,0x340(%RSP) |
0x43500b JE 434ded |
0x435011 JMP 435042 |
0x435040 XOR %ESI,%ESI |
0x435042 VPBROADCASTQ %RSI,%ZMM8 |
0x435048 VPSUBQ %ZMM8,%ZMM3,%ZMM6 |
0x43504e VPCMPNLEUQ 0xd46a7(%RIP),%ZMM6,%K1 |
0x435059 KORTESTB %K1,%K1 |
0x43505d JE 434ded |
0x435063 LEA (%R9,%RCX,1),%RAX |
0x435067 SUB %R12,%RAX |
0x43506a MOV %RDI,%RBX |
0x43506d IMUL %RAX,%RBX |
0x435071 ADD 0x50(%RSP),%RBX |
0x435076 ADD 0x300(%RSP),%RSI |
0x43507e SUB 0x400(%RSP),%RSI |
0x435086 VMOVUPD (%RBX,%RSI,8),%ZMM0{%K1}{z} |
0x43508d VMOVAPD %ZMM0,%ZMM24{%K1} |
0x435093 VFPCLASSPD $0x50,%ZMM24,%K2{%K1} |
0x43509a VPMOVQD %ZMM8,%YMM0 |
0x4350a0 VPADDD %YMM7,%YMM0,%YMM0 |
0x4350a4 VPADDQ %ZMM8,%ZMM4,%ZMM6 |
0x4350aa VPMOVQD %ZMM6,%YMM6 |
0x4350b0 VPCMPEQD %YMM8,%YMM8,%YMM8 |
0x4350b5 VPADDD %YMM6,%YMM8,%YMM6 |
0x4350b9 VPADDD %YMM0,%YMM5,%YMM25 |
0x4350bf VPBLENDMD %YMM6,%YMM25,%YMM8{%K2} |
0x4350c5 VMOVDQA32 %YMM25,%YMM6{%K2} |
0x4350cb MOV %R10,%RBX |
0x4350ce IMUL %RAX,%RBX |
0x4350d2 VPMOVSXDQ %YMM6,%ZMM6 |
0x4350d8 VPSUBQ %ZMM2,%ZMM6,%ZMM6 |
0x4350de ADD 0xb0(%RSP),%RBX |
0x4350e6 KMOVQ %K1,%K3 |
0x4350eb VXORPD %XMM26,%XMM26,%XMM26 |
0x4350f1 VGATHERQPD (%RBX,%ZMM6,8),%ZMM26{%K3} |
0x4350f8 MOV 0x3c0(%RSP),%RBX |
0x435100 IMUL %RAX,%RBX |
0x435104 ADD 0xf8(%RSP),%RBX |
0x43510c KMOVQ %K1,%K3 |
0x435111 VXORPD %XMM29,%XMM29,%XMM29 |
0x435117 VGATHERQPD (%RBX,%ZMM6,8),%ZMM29{%K3} |
0x43511e VPADDD 0x120(%RSP),%YMM0,%YMM27 |
0x435126 VMOVDQA64 %YMM27,%YMM6 |
0x43512c VPADDD %YMM0,%YMM1,%YMM6{%K2} |
0x435132 VPMOVSXDQ %YMM6,%ZMM0 |
0x435138 VPSUBQ %ZMM2,%ZMM0,%ZMM0 |
0x43513e KMOVQ %K1,%K3 |
0x435143 VPXOR %XMM6,%XMM6,%XMM6 |
0x435147 VGATHERQPD (%RBX,%ZMM0,8),%ZMM6{%K3} |
0x43514e VPMOVSXDQ %YMM8,%ZMM0 |
0x435154 VPSUBQ %ZMM2,%ZMM0,%ZMM0 |
0x43515a KMOVQ %K1,%K3 |
0x43515f VXORPD %XMM30,%XMM30,%XMM30 |
0x435165 VGATHERQPD (%RBX,%ZMM0,8),%ZMM30{%K3} |
0x43516c VPXORD %XMM28,%XMM28,%XMM28 |
0x435172 VANDPD %ZMM9,%ZMM24,%ZMM0 |
0x435178 VMOVAPD %ZMM26,%ZMM23{%K1} |
0x43517e VDIVPD %ZMM23,%ZMM0,%ZMM26 |
0x435184 VMOVAPD %ZMM29,%ZMM22{%K1} |
0x43518a VMOVAPD %ZMM6,%ZMM21{%K1} |
0x435190 VSUBPD %ZMM21,%ZMM22,%ZMM8 |
0x435196 VMOVAPD %ZMM30,%ZMM20{%K1} |
0x43519c VSUBPD %ZMM22,%ZMM20,%ZMM29 |
0x4351a2 VMULPD %ZMM8,%ZMM29,%ZMM0 |
0x4351a8 VCMPPD $0x1,%ZMM0,%ZMM28,%K3{%K1} |
0x4351af KORTESTB %K3,%K3 |
0x4351b3 JE 434dc0 |
0x4351b9 MOV 0x38(%RSP),%RBX |
0x4351be VMOVUPD (%RBX,%RSI,8),%ZMM0{%K3}{z} |
0x4351c5 VMOVAPD %ZMM0,%ZMM19{%K3} |
0x4351cb VANDPD %ZMM9,%ZMM29,%ZMM28 |
0x4351d1 VSUBPD %ZMM26,%ZMM11,%ZMM0 |
0x4351d7 VMULPD %ZMM0,%ZMM28,%ZMM0 |
0x4351dd VDIVPD %ZMM19,%ZMM0,%ZMM0 |
0x4351e3 VMOVDQA32 %YMM25,%YMM27{%K2} |
0x4351e9 VANDPD %ZMM9,%ZMM8,%ZMM6 |
0x4351ef VCMPPD $0x2,%ZMM28,%ZMM6,%K2 |
0x4351f6 VMOVAPD %ZMM6,%ZMM28{%K2} |
0x4351fc VPMOVSXDQ %YMM27,%ZMM8 |
0x435202 VPSUBQ %ZMM2,%ZMM8,%ZMM8 |
0x435208 VPXORD %XMM25,%XMM25,%XMM25 |
0x43520e KMOVQ %K3,%K2 |
0x435213 VGATHERQPD (%RBX,%ZMM8,8),%ZMM25{%K2} |
0x43521a VFMADD213PD %ZMM6,%ZMM26,%ZMM6 |
0x435220 VMOVAPD %ZMM25,%ZMM18{%K3} |
0x435226 VDIVPD %ZMM18,%ZMM6,%ZMM6 |
0x43522c VADDPD %ZMM0,%ZMM6,%ZMM0 |
0x435232 VMULPD %ZMM13,%ZMM19,%ZMM6 |
0x435238 VMULPD %ZMM0,%ZMM6,%ZMM0 |
0x43523e VCMPPD $0x2,%ZMM28,%ZMM0,%K2 |
0x435245 VMOVAPD %ZMM0,%ZMM28{%K2} |
0x43524b VFPCLASSPD $0x56,%ZMM29,%K2 |
0x435252 VXORPD %ZMM14,%ZMM28,%ZMM28{%K2} |
0x435258 JMP 434dc0 |
/scratch_na/users/xoserete/qaas_runs/171-215-0463/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 81 - 177 |
-------------------------------------------------------------------------------- |
81: IF(mom_sweep.EQ.1)THEN ! x 1 |
[...] |
150: DO k=y_min,y_max+1 |
151: DO j=x_min-1,x_max+1 |
152: IF(node_flux(j,k).LT.0.0)THEN |
[...] |
158: upwind=j-1 |
159: donor=j |
160: downwind=j+1 |
161: dif=upwind |
162: ENDIF |
163: sigma=ABS(node_flux(j,k))/(node_mass_pre(donor,k)) |
164: width=celldx(j) |
165: vdiffuw=vel1(donor,k)-vel1(upwind,k) |
166: vdiffdw=vel1(downwind,k)-vel1(donor,k) |
167: limiter=0.0 |
168: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
169: auw=ABS(vdiffuw) |
170: adw=ABS(vdiffdw) |
171: wind=1.0_8 |
172: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
173: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldx(dif))/6.0_8,auw,adw) |
174: ENDIF |
175: advec_vel_s=vel1(donor,k)+(1.0-sigma)*limiter |
176: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
177: ENDDO |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.48 |
Bottlenecks | P0, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:150-152,advec_mom_kernel.f90:158-158,advec_mom_kernel.f90:163-170,advec_mom_kernel.f90:173-176 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 48.00 |
CQA cycles if no scalar integer | 48.00 |
CQA cycles if FP arith vectorized | 48.00 |
CQA cycles if fully vectorized | 48.00 |
Front-end cycles | 24.00 |
DIV/SQRT cycles | 32.50 |
P0 cycles | 15.00 |
P1 cycles | 19.33 |
P2 cycles | 19.33 |
P3 cycles | 0.50 |
P4 cycles | 32.50 |
P5 cycles | 10.00 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 10.00 |
P10 cycles | 19.33 |
P11 cycles | 48.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 59.51 - 113.77 |
Stall cycles (UFS) | 36.33 - 90.59 |
Nb insns | 119.00 |
Nb uops | 144.00 |
Nb loads | 24.00 |
Nb stores | 1.00 |
Nb stack references | 12.00 |
FLOP/cycle | 2.83 |
Nb FLOP add-sub | 40.00 |
Nb FLOP mul | 40.00 |
Nb FLOP fma | 16.00 |
Nb FLOP div | 24.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 15.17 |
Bytes prefetched | 0.00 |
Bytes loaded | 664.00 |
Bytes stored | 64.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 91.03 |
Vectorization ratio load | 75.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 88.89 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 89.36 |
Vector-efficiency ratio all | 77.32 |
Vector-efficiency ratio load | 73.96 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 76.39 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 71.41 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.48 |
Bottlenecks | P0, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:150-152,advec_mom_kernel.f90:158-158,advec_mom_kernel.f90:163-170,advec_mom_kernel.f90:173-176 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 48.00 |
CQA cycles if no scalar integer | 48.00 |
CQA cycles if FP arith vectorized | 48.00 |
CQA cycles if fully vectorized | 48.00 |
Front-end cycles | 24.00 |
DIV/SQRT cycles | 32.50 |
P0 cycles | 15.00 |
P1 cycles | 19.33 |
P2 cycles | 19.33 |
P3 cycles | 0.50 |
P4 cycles | 32.50 |
P5 cycles | 10.00 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 10.00 |
P10 cycles | 19.33 |
P11 cycles | 48.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 59.51 - 113.77 |
Stall cycles (UFS) | 36.33 - 90.59 |
Nb insns | 119.00 |
Nb uops | 144.00 |
Nb loads | 24.00 |
Nb stores | 1.00 |
Nb stack references | 12.00 |
FLOP/cycle | 2.83 |
Nb FLOP add-sub | 40.00 |
Nb FLOP mul | 40.00 |
Nb FLOP fma | 16.00 |
Nb FLOP div | 24.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 15.17 |
Bytes prefetched | 0.00 |
Bytes loaded | 664.00 |
Bytes stored | 64.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 91.03 |
Vectorization ratio load | 75.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 88.89 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 89.36 |
Vector-efficiency ratio all | 77.32 |
Vector-efficiency ratio load | 73.96 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 76.39 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 71.41 |
Path / |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-177 |
Module | exec |
nb instructions | 119 |
nb uops | 144 |
loop length | 684 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 8 |
used zmm registers | 23 |
nb stack references | 12 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 24.00 cycles |
front end | 24.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 32.50 | 15.00 | 19.33 | 19.33 | 0.50 | 32.50 | 10.00 | 0.50 | 0.50 | 0.50 | 10.00 | 19.33 |
cycles | 32.50 | 15.00 | 19.33 | 19.33 | 0.50 | 32.50 | 10.00 | 0.50 | 0.50 | 0.50 | 10.00 | 19.33 |
Cycles executing div or sqrt instructions | 48.00 |
FE+BE cycles | 59.51-113.77 |
Stall cycles | 36.33-90.59 |
ROB full (events) | 39.44-94.92 |
Front-end | 24.00 |
Dispatch | 32.50 |
DIV/SQRT | 48.00 |
Overall L1 | 48.00 |
all | 78% |
load | 40% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 84% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 75% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 91% |
load | 75% |
store | 100% |
mul | 100% |
add-sub | 88% |
fma | 100% |
div/sqrt | 100% |
other | 89% |
all | 53% |
load | 37% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 67% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 44% |
all | 95% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 91% |
all | 77% |
load | 73% |
store | 100% |
mul | 100% |
add-sub | 76% |
fma | 100% |
div/sqrt | 100% |
other | 71% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVAPD %ZMM28,%ZMM0{%K3}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VSUBPD %ZMM26,%ZMM10,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213PD %ZMM22,%ZMM0,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM24,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
IMUL 0x30(%RSP),%RAX | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
ADD 0xd8(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVUPD %ZMM0,(%RAX,%RSI,8){%K1} | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD 0x30(%RSP),%R14 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP 0x280(%RSP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x1(%RCX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 431ff2 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x962> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 435040 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x39b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R9,%RCX,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R12,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL 0x3c0(%RSP),%RAX | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
ADD 0xb0(%RSP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD 0xf8(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 434e73 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x37e3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R8,0x340(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 434ded <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x375d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 435042 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x39b2> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ %RSI,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM8,%ZMM3,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPCMPNLEUQ 0xd46a7(%RIP),%ZMM6,%K1 | |||||||||||||||
KORTESTB %K1,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JE 434ded <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x375d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R9,%RCX,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R12,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x50(%RSP),%RBX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD 0x300(%RSP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
SUB 0x400(%RSP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVUPD (%RBX,%RSI,8),%ZMM0{%K1}{z} | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVAPD %ZMM0,%ZMM24{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFPCLASSPD $0x50,%ZMM24,%K2{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVQD %ZMM8,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDD %YMM7,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPADDQ %ZMM8,%ZMM4,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPMOVQD %ZMM6,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPCMPEQD %YMM8,%YMM8,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPADDD %YMM6,%YMM8,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPADDD %YMM0,%YMM5,%YMM25 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPBLENDMD %YMM6,%YMM25,%YMM8{%K2} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVDQA32 %YMM25,%YMM6{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
MOV %R10,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM6,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM2,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
ADD 0xb0(%RSP),%RBX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
KMOVQ %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VXORPD %XMM26,%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%RBX,%ZMM6,8),%ZMM26{%K3} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
MOV 0x3c0(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xf8(%RSP),%RBX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
KMOVQ %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VXORPD %XMM29,%XMM29,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%RBX,%ZMM6,8),%ZMM29{%K3} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPADDD 0x120(%RSP),%YMM0,%YMM27 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQA64 %YMM27,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VPADDD %YMM0,%YMM1,%YMM6{%K2} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPMOVSXDQ %YMM6,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM2,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
KMOVQ %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VPXOR %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%RBX,%ZMM0,8),%ZMM6{%K3} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPMOVSXDQ %YMM8,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM2,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
KMOVQ %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VXORPD %XMM30,%XMM30,%XMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%RBX,%ZMM0,8),%ZMM30{%K3} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPXORD %XMM28,%XMM28,%XMM28 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VANDPD %ZMM9,%ZMM24,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVAPD %ZMM26,%ZMM23{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VDIVPD %ZMM23,%ZMM0,%ZMM26 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VMOVAPD %ZMM29,%ZMM22{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %ZMM6,%ZMM21{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VSUBPD %ZMM21,%ZMM22,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVAPD %ZMM30,%ZMM20{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VSUBPD %ZMM22,%ZMM20,%ZMM29 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %ZMM8,%ZMM29,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%ZMM0,%ZMM28,%K3{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KORTESTB %K3,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JE 434dc0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3730> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x38(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVUPD (%RBX,%RSI,8),%ZMM0{%K3}{z} | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVAPD %ZMM0,%ZMM19{%K3} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VANDPD %ZMM9,%ZMM29,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VSUBPD %ZMM26,%ZMM11,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %ZMM0,%ZMM28,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVPD %ZMM19,%ZMM0,%ZMM0 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VMOVDQA32 %YMM25,%YMM27{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VANDPD %ZMM9,%ZMM8,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCMPPD $0x2,%ZMM28,%ZMM6,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM6,%ZMM28{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VPMOVSXDQ %YMM27,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM2,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPXORD %XMM25,%XMM25,%XMM25 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
KMOVQ %K3,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VGATHERQPD (%RBX,%ZMM8,8),%ZMM25{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VFMADD213PD %ZMM6,%ZMM26,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %ZMM25,%ZMM18{%K3} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VDIVPD %ZMM18,%ZMM6,%ZMM6 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VADDPD %ZMM0,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %ZMM13,%ZMM19,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM0,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x2,%ZMM28,%ZMM0,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM0,%ZMM28{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFPCLASSPD $0x56,%ZMM29,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VXORPD %ZMM14,%ZMM28,%ZMM28{%K2} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
JMP 434dc0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3730> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-177 |
Module | exec |
nb instructions | 119 |
nb uops | 144 |
loop length | 684 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 8 |
used zmm registers | 23 |
nb stack references | 12 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 24.00 cycles |
front end | 24.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 32.50 | 15.00 | 19.33 | 19.33 | 0.50 | 32.50 | 10.00 | 0.50 | 0.50 | 0.50 | 10.00 | 19.33 |
cycles | 32.50 | 15.00 | 19.33 | 19.33 | 0.50 | 32.50 | 10.00 | 0.50 | 0.50 | 0.50 | 10.00 | 19.33 |
Cycles executing div or sqrt instructions | 48.00 |
FE+BE cycles | 59.51-113.77 |
Stall cycles | 36.33-90.59 |
ROB full (events) | 39.44-94.92 |
Front-end | 24.00 |
Dispatch | 32.50 |
DIV/SQRT | 48.00 |
Overall L1 | 48.00 |
all | 78% |
load | 40% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 84% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 75% |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 91% |
load | 75% |
store | 100% |
mul | 100% |
add-sub | 88% |
fma | 100% |
div/sqrt | 100% |
other | 89% |
all | 53% |
load | 37% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 67% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 44% |
all | 95% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 91% |
all | 77% |
load | 73% |
store | 100% |
mul | 100% |
add-sub | 76% |
fma | 100% |
div/sqrt | 100% |
other | 71% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVAPD %ZMM28,%ZMM0{%K3}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VSUBPD %ZMM26,%ZMM10,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213PD %ZMM22,%ZMM0,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM24,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
IMUL 0x30(%RSP),%RAX | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
ADD 0xd8(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVUPD %ZMM0,(%RAX,%RSI,8){%K1} | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD 0x30(%RSP),%R14 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RDI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP 0x280(%RSP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x1(%RCX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 431ff2 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x962> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 435040 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x39b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R9,%RCX,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R12,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL 0x3c0(%RSP),%RAX | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
ADD 0xb0(%RSP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD 0xf8(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 434e73 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x37e3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R8,0x340(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 434ded <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x375d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 435042 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x39b2> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ %RSI,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM8,%ZMM3,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPCMPNLEUQ 0xd46a7(%RIP),%ZMM6,%K1 | |||||||||||||||
KORTESTB %K1,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JE 434ded <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x375d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R9,%RCX,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R12,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x50(%RSP),%RBX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD 0x300(%RSP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
SUB 0x400(%RSP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVUPD (%RBX,%RSI,8),%ZMM0{%K1}{z} | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVAPD %ZMM0,%ZMM24{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFPCLASSPD $0x50,%ZMM24,%K2{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVQD %ZMM8,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDD %YMM7,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPADDQ %ZMM8,%ZMM4,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPMOVQD %ZMM6,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPCMPEQD %YMM8,%YMM8,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPADDD %YMM6,%YMM8,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPADDD %YMM0,%YMM5,%YMM25 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPBLENDMD %YMM6,%YMM25,%YMM8{%K2} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVDQA32 %YMM25,%YMM6{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
MOV %R10,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMOVSXDQ %YMM6,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM2,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
ADD 0xb0(%RSP),%RBX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
KMOVQ %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VXORPD %XMM26,%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%RBX,%ZMM6,8),%ZMM26{%K3} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
MOV 0x3c0(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xf8(%RSP),%RBX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
KMOVQ %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VXORPD %XMM29,%XMM29,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%RBX,%ZMM6,8),%ZMM29{%K3} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPADDD 0x120(%RSP),%YMM0,%YMM27 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVDQA64 %YMM27,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VPADDD %YMM0,%YMM1,%YMM6{%K2} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPMOVSXDQ %YMM6,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM2,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
KMOVQ %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VPXOR %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%RBX,%ZMM0,8),%ZMM6{%K3} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPMOVSXDQ %YMM8,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM2,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
KMOVQ %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VXORPD %XMM30,%XMM30,%XMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%RBX,%ZMM0,8),%ZMM30{%K3} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VPXORD %XMM28,%XMM28,%XMM28 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VANDPD %ZMM9,%ZMM24,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVAPD %ZMM26,%ZMM23{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VDIVPD %ZMM23,%ZMM0,%ZMM26 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VMOVAPD %ZMM29,%ZMM22{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %ZMM6,%ZMM21{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VSUBPD %ZMM21,%ZMM22,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVAPD %ZMM30,%ZMM20{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VSUBPD %ZMM22,%ZMM20,%ZMM29 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %ZMM8,%ZMM29,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%ZMM0,%ZMM28,%K3{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KORTESTB %K3,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JE 434dc0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3730> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x38(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVUPD (%RBX,%RSI,8),%ZMM0{%K3}{z} | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVAPD %ZMM0,%ZMM19{%K3} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VANDPD %ZMM9,%ZMM29,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VSUBPD %ZMM26,%ZMM11,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %ZMM0,%ZMM28,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVPD %ZMM19,%ZMM0,%ZMM0 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VMOVDQA32 %YMM25,%YMM27{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VANDPD %ZMM9,%ZMM8,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCMPPD $0x2,%ZMM28,%ZMM6,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM6,%ZMM28{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VPMOVSXDQ %YMM27,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM2,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPXORD %XMM25,%XMM25,%XMM25 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
KMOVQ %K3,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
VGATHERQPD (%RBX,%ZMM8,8),%ZMM25{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
VFMADD213PD %ZMM6,%ZMM26,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %ZMM25,%ZMM18{%K3} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VDIVPD %ZMM18,%ZMM6,%ZMM6 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VADDPD %ZMM0,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %ZMM13,%ZMM19,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %ZMM0,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x2,%ZMM28,%ZMM0,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM0,%ZMM28{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFPCLASSPD $0x56,%ZMM29,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VXORPD %ZMM14,%ZMM28,%ZMM28{%K2} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
JMP 434dc0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3730> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |