Loop Id: 255 | Module: exec | Source: generate_chunk_kernel.f90:87-163 [...] | Coverage: 0.02% |
---|
Loop Id: 255 | Module: exec | Source: generate_chunk_kernel.f90:87-163 [...] | Coverage: 0.02% |
---|
0x43f000 MOV -0x68(%RBP),%R10D |
0x43f004 INC %R10D |
0x43f007 MOV -0x80(%RBP),%R11 |
0x43f00b INC %R11 |
0x43f00e MOV -0x70(%RBP),%R8 |
0x43f012 INC %R8 |
0x43f015 CMP -0x168(%RBP),%R11 |
0x43f01c MOV -0xf4(%RBP),%EDX |
0x43f022 JE 43ef40 |
0x43f028 MOVSXD %R10D,%RAX |
0x43f02b LEA (,%RAX,8),%RDI |
0x43f033 CMP %RAX,%R8 |
0x43f036 MOV %RAX,%RCX |
0x43f039 CMOVG %R8,%RCX |
0x43f03d SUB %RAX,%RCX |
0x43f040 INC %RCX |
0x43f043 SHR $0x3,%RCX |
0x43f047 NEG %RCX |
0x43f04a MOV %RCX,-0x50(%RBP) |
0x43f04e MOV -0x160(%RBP),%RCX |
0x43f055 LEA (%R11,%RCX,1),%RSI |
0x43f059 CMP -0xf0(%RBP),%EDX |
0x43f05f MOV %R8,-0x70(%RBP) |
0x43f063 MOV %R10D,-0x68(%RBP) |
0x43f067 MOV %R11,-0x80(%RBP) |
0x43f06b JNE 43f200 |
0x43f071 LEA 0x1(%RSI),%RCX |
0x43f075 MOV %RCX,%RDX |
0x43f078 SUB -0x60(%RBP),%RDX |
0x43f07c MOV 0xb8(%RBP),%R8 |
0x43f083 VMOVSD (%R8,%RDX,8),%XMM0 |
0x43f089 MOV 0x50(%RBP),%RDX |
0x43f08d MOV -0x40(%RBP),%R8 |
0x43f091 VUCOMISD -0x8(%RDX,%R8,8),%XMM0 |
0x43f098 JB 43f000 |
0x43f09e SUB -0x60(%RBP),%RSI |
0x43f0a2 MOV 0x48(%RBP),%RDX |
0x43f0a6 MOV -0x40(%RBP),%R8 |
0x43f0aa VMOVSD -0x8(%RDX,%R8,8),%XMM0 |
0x43f0b1 MOV 0xb8(%RBP),%RDX |
0x43f0b8 VUCOMISD (%RDX,%RSI,8),%XMM0 |
0x43f0bd JBE 43f000 |
0x43f0c3 MOV 0xb0(%RBP),%RDX |
0x43f0ca MOV -0x158(%RBP),%R8 |
0x43f0d1 VMOVSD (%RDX,%R8,8),%XMM0 |
0x43f0d7 MOV 0x40(%RBP),%RDX |
0x43f0db MOV -0x40(%RBP),%R8 |
0x43f0df VUCOMISD -0x8(%RDX,%R8,8),%XMM0 |
0x43f0e6 JB 43f000 |
0x43f0ec MOV 0x38(%RBP),%RDX |
0x43f0f0 MOV -0x40(%RBP),%R8 |
0x43f0f4 VMOVSD -0x8(%RDX,%R8,8),%XMM0 |
0x43f0fb MOV 0xb0(%RBP),%RDX |
0x43f102 MOV -0x78(%RBP),%R8 |
0x43f106 VUCOMISD (%RDX,%R8,8),%XMM0 |
0x43f10c JBE 43f000 |
0x43f112 MOV 0xe0(%RBP),%RDX |
0x43f119 MOV (%RDX),%RDX |
0x43f11c MOV -0x78(%RBP),%R11 |
0x43f120 IMUL %R11,%RDX |
0x43f124 ADD 0x90(%RBP),%RDX |
0x43f12b MOV 0x68(%RBP),%R8 |
0x43f12f MOV -0x40(%RBP),%R10 |
0x43f133 VMOVSD -0x8(%R8,%R10,8),%XMM0 |
0x43f13a VMOVSD %XMM0,(%RDX,%RSI,8) |
0x43f13f MOV 0xf0(%RBP),%RDX |
0x43f146 MOV (%RDX),%RDX |
0x43f149 IMUL %R11,%RDX |
0x43f14d ADD 0x98(%RBP),%RDX |
0x43f154 MOV 0x70(%RBP),%R8 |
0x43f158 VMOVSD -0x8(%R8,%R10,8),%XMM0 |
0x43f15f VMOVSD %XMM0,(%RDX,%RSI,8) |
0x43f164 MOV 0x60(%RBP),%RDX |
0x43f168 VMOVSD -0x8(%RDX,%R10,8),%XMM0 |
0x43f16f MOV 0x100(%RBP),%RDX |
0x43f176 MOV (%RDX),%R8 |
0x43f179 MOV 0x58(%RBP),%RDX |
0x43f17d VMOVQ -0x8(%RDX,%R10,8),%XMM1 |
0x43f184 MOV 0x110(%RBP),%RDX |
0x43f18b MOV (%RDX),%R14 |
0x43f18e CMP %RAX,%RCX |
0x43f191 CMOVLE %RAX,%RCX |
0x43f195 SUB %RAX,%RCX |
0x43f198 LEA 0x1(%RCX),%R9 |
0x43f19c MOV %R9,%R10 |
0x43f19f AND $-0x8,%R10 |
0x43f1a3 SUB %R10,%RCX |
0x43f1a6 ADD %RAX,%R10 |
0x43f1a9 SUB -0x60(%RBP),%R10 |
0x43f1ad LEA 0x6(%R10),%RAX |
0x43f1b1 MOV %RAX,-0xd8(%RBP) |
0x43f1b8 MOV -0xc0(%RBP),%RDX |
0x43f1bf MOV %RDX,%RBX |
0x43f1c2 IMUL %R14,%RBX |
0x43f1c6 MOV -0xb8(%RBP),%RAX |
0x43f1cd ADD %RDI,%RAX |
0x43f1d0 ADD %RAX,%RBX |
0x43f1d3 MOV %RDX,%RAX |
0x43f1d6 IMUL %R8,%RAX |
0x43f1da ADD -0xb0(%RBP),%RDI |
0x43f1e1 ADD %RAX,%RDI |
0x43f1e4 XOR %EAX,%EAX |
0x43f1e6 JMP 43f42f |
0x43f200 MOV 0x18(%RBP),%RCX |
0x43f204 CMP (%RCX),%EDX |
0x43f206 JNE 43f880 |
0x43f20c MOV %RSI,%RCX |
0x43f20f SUB -0x60(%RBP),%RCX |
0x43f213 MOV 0xa8(%RBP),%RDX |
0x43f21a VMOVSD (%RDX,%RCX,8),%XMM0 |
0x43f21f MOV -0xd0(%RBP),%RDX |
0x43f226 VSUBSD (%RDX),%XMM0,%XMM0 |
0x43f22a VMULSD %XMM0,%XMM0,%XMM0 |
0x43f22e MOV 0xa0(%RBP),%RDX |
0x43f235 MOV -0x78(%RBP),%R8 |
0x43f239 VMOVSD (%RDX,%R8,8),%XMM1 |
0x43f23f MOV -0xc8(%RBP),%RDX |
0x43f246 VSUBSD (%RDX),%XMM1,%XMM1 |
0x43f24a VFMADD213SD %XMM0,%XMM1,%XMM1 |
0x43f24f VSQRTSD %XMM1,%XMM1,%XMM0 |
0x43f253 MOV 0x30(%RBP),%RDX |
0x43f257 MOV -0x40(%RBP),%R8 |
0x43f25b VMOVSD -0x8(%RDX,%R8,8),%XMM1 |
0x43f262 VUCOMISD %XMM0,%XMM1 |
0x43f266 JB 43f000 |
0x43f26c MOV 0xe0(%RBP),%RDX |
0x43f273 MOV (%RDX),%RDX |
0x43f276 MOV -0x78(%RBP),%R11 |
0x43f27a IMUL %R11,%RDX |
0x43f27e ADD 0x90(%RBP),%RDX |
0x43f285 MOV 0x68(%RBP),%R8 |
0x43f289 MOV -0x40(%RBP),%R10 |
0x43f28d VMOVSD -0x8(%R8,%R10,8),%XMM0 |
0x43f294 VMOVSD %XMM0,(%RDX,%RCX,8) |
0x43f299 MOV 0xf0(%RBP),%RDX |
0x43f2a0 MOV (%RDX),%RDX |
0x43f2a3 IMUL %R11,%RDX |
0x43f2a7 ADD 0x98(%RBP),%RDX |
0x43f2ae MOV 0x70(%RBP),%R8 |
0x43f2b2 VMOVSD -0x8(%R8,%R10,8),%XMM0 |
0x43f2b9 VMOVSD %XMM0,(%RDX,%RCX,8) |
0x43f2be MOV 0x60(%RBP),%RCX |
0x43f2c2 VMOVSD -0x8(%RCX,%R10,8),%XMM0 |
0x43f2c9 MOV 0x100(%RBP),%RCX |
0x43f2d0 MOV (%RCX),%RCX |
0x43f2d3 MOV 0x58(%RBP),%RDX |
0x43f2d7 VMOVQ -0x8(%RDX,%R10,8),%XMM1 |
0x43f2de MOV 0x110(%RBP),%RDX |
0x43f2e5 MOV (%RDX),%R14 |
0x43f2e8 INC %RSI |
0x43f2eb CMP %RAX,%RSI |
0x43f2ee CMOVLE %RAX,%RSI |
0x43f2f2 SUB %RAX,%RSI |
0x43f2f5 LEA 0x1(%RSI),%R9 |
0x43f2f9 MOV %R9,%R12 |
0x43f2fc AND $-0x8,%R12 |
0x43f300 SUB %R12,%RSI |
0x43f303 ADD %RAX,%R12 |
0x43f306 SUB -0x60(%RBP),%R12 |
0x43f30a LEA 0x6(%R12),%RAX |
0x43f30f MOV %RAX,-0xd8(%RBP) |
0x43f316 MOV -0xc0(%RBP),%RDX |
0x43f31d MOV %RDX,%RBX |
0x43f320 IMUL %R14,%RBX |
0x43f324 MOV -0xb8(%RBP),%RAX |
0x43f32b ADD %RDI,%RAX |
0x43f32e ADD %RAX,%RBX |
0x43f331 MOV %RDX,%RAX |
0x43f334 IMUL %RCX,%RAX |
0x43f338 ADD -0xb0(%RBP),%RDI |
0x43f33f ADD %RAX,%RDI |
0x43f342 XOR %EAX,%EAX |
0x43f344 JMP 43f6af |
(260) 0x43f380 MOV -0x38(%RBP),%RDX |
(260) 0x43f384 ADD %RAX,%RDX |
(260) 0x43f387 SUB -0x30(%RBP),%RDX |
(260) 0x43f38b MOV %R8,%RSI |
(260) 0x43f38e IMUL %RDX,%RSI |
(260) 0x43f392 IMUL %R14,%RDX |
(260) 0x43f396 LEA (%R15,%RSI,1),%R11 |
(260) 0x43f39a VMOVSD %XMM0,0x28(%R11,%R10,8) |
(260) 0x43f3a1 LEA (%R13,%RDX,1),%R11 |
(260) 0x43f3a6 VMOVQ %XMM1,0x28(%R11,%R10,8) |
(260) 0x43f3ad LEA (%R15,%RSI,1),%R11 |
(260) 0x43f3b1 VMOVSD %XMM0,0x20(%R11,%R10,8) |
(260) 0x43f3b8 LEA (%R13,%RDX,1),%R11 |
(260) 0x43f3bd VMOVQ %XMM1,0x20(%R11,%R10,8) |
(260) 0x43f3c4 LEA (%R15,%RSI,1),%R11 |
(260) 0x43f3c8 VMOVSD %XMM0,0x18(%R11,%R10,8) |
(260) 0x43f3cf LEA (%R13,%RDX,1),%R11 |
(260) 0x43f3d4 VMOVQ %XMM1,0x18(%R11,%R10,8) |
(260) 0x43f3db LEA (%R15,%RSI,1),%R11 |
(260) 0x43f3df VMOVSD %XMM0,0x10(%R11,%R10,8) |
(260) 0x43f3e6 LEA (%R13,%RDX,1),%R11 |
(260) 0x43f3eb VMOVQ %XMM1,0x10(%R11,%R10,8) |
(260) 0x43f3f2 LEA (%R15,%RSI,1),%R11 |
(260) 0x43f3f6 VMOVSD %XMM0,0x8(%R11,%R10,8) |
(260) 0x43f3fd LEA (%R13,%RDX,1),%R11 |
(260) 0x43f402 VMOVQ %XMM1,0x8(%R11,%R10,8) |
(260) 0x43f409 ADD %R15,%RSI |
(260) 0x43f40c VMOVSD %XMM0,(%RSI,%R10,8) |
(260) 0x43f412 ADD %R13,%RDX |
(260) 0x43f415 VMOVQ %XMM1,(%RDX,%R10,8) |
(260) 0x43f41b ADD %R14,%RBX |
(260) 0x43f41e ADD %R8,%RDI |
(260) 0x43f421 CMP $0x1,%RAX |
(260) 0x43f425 LEA 0x1(%RAX),%RAX |
(260) 0x43f429 JE 43f000 |
(260) 0x43f42f CMP $0x8,%R9 |
(260) 0x43f433 JB 43f4a7 |
(260) 0x43f435 MOV $0x38,%EDX |
(260) 0x43f43a MOV -0x50(%RBP),%RSI |
(260) 0x43f43e XCHG %AX,%AX |
(261) 0x43f440 VMOVSD %XMM0,-0x38(%RDI,%RDX,1) |
(261) 0x43f446 VMOVQ %XMM1,-0x38(%RBX,%RDX,1) |
(261) 0x43f44c VMOVSD %XMM0,-0x30(%RDI,%RDX,1) |
(261) 0x43f452 VMOVQ %XMM1,-0x30(%RBX,%RDX,1) |
(261) 0x43f458 VMOVSD %XMM0,-0x28(%RDI,%RDX,1) |
(261) 0x43f45e VMOVQ %XMM1,-0x28(%RBX,%RDX,1) |
(261) 0x43f464 VMOVSD %XMM0,-0x20(%RDI,%RDX,1) |
(261) 0x43f46a VMOVQ %XMM1,-0x20(%RBX,%RDX,1) |
(261) 0x43f470 VMOVSD %XMM0,-0x18(%RDI,%RDX,1) |
(261) 0x43f476 VMOVQ %XMM1,-0x18(%RBX,%RDX,1) |
(261) 0x43f47c VMOVSD %XMM0,-0x10(%RDI,%RDX,1) |
(261) 0x43f482 VMOVQ %XMM1,-0x10(%RBX,%RDX,1) |
(261) 0x43f488 VMOVSD %XMM0,-0x8(%RDI,%RDX,1) |
(261) 0x43f48e VMOVQ %XMM1,-0x8(%RBX,%RDX,1) |
(261) 0x43f494 VMOVSD %XMM0,(%RDI,%RDX,1) |
(261) 0x43f499 VMOVQ %XMM1,(%RBX,%RDX,1) |
(261) 0x43f49e ADD $0x40,%RDX |
(261) 0x43f4a2 INC %RSI |
(261) 0x43f4a5 JNE 43f440 |
(260) 0x43f4a7 CMP $0x3,%RCX |
(260) 0x43f4ab JGE 43f500 |
(260) 0x43f4ad TEST %RCX,%RCX |
(260) 0x43f4b0 JLE 43f5c0 |
(260) 0x43f4b6 MOV -0x38(%RBP),%RDX |
(260) 0x43f4ba ADD %RAX,%RDX |
(260) 0x43f4bd SUB -0x30(%RBP),%RDX |
(260) 0x43f4c1 MOV %R8,%RSI |
(260) 0x43f4c4 IMUL %RDX,%RSI |
(260) 0x43f4c8 IMUL %R14,%RDX |
(260) 0x43f4cc CMP $0x1,%RCX |
(260) 0x43f4d0 JNE 43f3db |
(260) 0x43f4d6 JMP 43f3f2 |
(260) 0x43f500 CMP $0x5,%RCX |
(260) 0x43f504 JGE 43f540 |
(260) 0x43f506 MOV -0x38(%RBP),%RDX |
(260) 0x43f50a ADD %RAX,%RDX |
(260) 0x43f50d SUB -0x30(%RBP),%RDX |
(260) 0x43f511 MOV %R8,%RSI |
(260) 0x43f514 IMUL %RDX,%RSI |
(260) 0x43f518 IMUL %R14,%RDX |
(260) 0x43f51c CMP $0x4,%RCX |
(260) 0x43f520 JE 43f3ad |
(260) 0x43f526 JMP 43f3c4 |
(260) 0x43f540 JE 43f380 |
(260) 0x43f546 CMP $0x6,%RCX |
(260) 0x43f54a JNE 43f41b |
(260) 0x43f550 MOV -0x38(%RBP),%RDX |
(260) 0x43f554 ADD %RAX,%RDX |
(260) 0x43f557 SUB -0x30(%RBP),%RDX |
(260) 0x43f55b MOV %R8,%RSI |
(260) 0x43f55e IMUL %RDX,%RSI |
(260) 0x43f562 LEA (%R15,%RSI,1),%R11 |
(260) 0x43f566 MOV %R15,%R12 |
(260) 0x43f569 MOV -0xd8(%RBP),%R15 |
(260) 0x43f570 VMOVSD %XMM0,(%R11,%R15,8) |
(260) 0x43f576 IMUL %R14,%RDX |
(260) 0x43f57a LEA (%R13,%RDX,1),%R11 |
(260) 0x43f57f VMOVQ %XMM1,(%R11,%R15,8) |
(260) 0x43f585 MOV %R12,%R15 |
(260) 0x43f588 JMP 43f396 |
(260) 0x43f5c0 JNE 43f41b |
(260) 0x43f5c6 MOV -0x38(%RBP),%RDX |
(260) 0x43f5ca ADD %RAX,%RDX |
(260) 0x43f5cd SUB -0x30(%RBP),%RDX |
(260) 0x43f5d1 MOV %R8,%RSI |
(260) 0x43f5d4 IMUL %RDX,%RSI |
(260) 0x43f5d8 IMUL %R14,%RDX |
(260) 0x43f5dc JMP 43f409 |
(258) 0x43f600 MOV -0x38(%RBP),%RDX |
(258) 0x43f604 ADD %RAX,%RDX |
(258) 0x43f607 SUB -0x30(%RBP),%RDX |
(258) 0x43f60b MOV %RCX,%R8 |
(258) 0x43f60e IMUL %RDX,%R8 |
(258) 0x43f612 IMUL %R14,%RDX |
(258) 0x43f616 LEA (%R15,%R8,1),%R11 |
(258) 0x43f61a VMOVSD %XMM0,0x28(%R11,%R12,8) |
(258) 0x43f621 LEA (%R13,%RDX,1),%R11 |
(258) 0x43f626 VMOVQ %XMM1,0x28(%R11,%R12,8) |
(258) 0x43f62d LEA (%R15,%R8,1),%R11 |
(258) 0x43f631 VMOVSD %XMM0,0x20(%R11,%R12,8) |
(258) 0x43f638 LEA (%R13,%RDX,1),%R11 |
(258) 0x43f63d VMOVQ %XMM1,0x20(%R11,%R12,8) |
(258) 0x43f644 LEA (%R15,%R8,1),%R11 |
(258) 0x43f648 VMOVSD %XMM0,0x18(%R11,%R12,8) |
(258) 0x43f64f LEA (%R13,%RDX,1),%R11 |
(258) 0x43f654 VMOVQ %XMM1,0x18(%R11,%R12,8) |
(258) 0x43f65b LEA (%R15,%R8,1),%R11 |
(258) 0x43f65f VMOVSD %XMM0,0x10(%R11,%R12,8) |
(258) 0x43f666 LEA (%R13,%RDX,1),%R11 |
(258) 0x43f66b VMOVQ %XMM1,0x10(%R11,%R12,8) |
(258) 0x43f672 LEA (%R15,%R8,1),%R11 |
(258) 0x43f676 VMOVSD %XMM0,0x8(%R11,%R12,8) |
(258) 0x43f67d LEA (%R13,%RDX,1),%R11 |
(258) 0x43f682 VMOVQ %XMM1,0x8(%R11,%R12,8) |
(258) 0x43f689 ADD %R15,%R8 |
(258) 0x43f68c VMOVSD %XMM0,(%R8,%R12,8) |
(258) 0x43f692 ADD %R13,%RDX |
(258) 0x43f695 VMOVQ %XMM1,(%RDX,%R12,8) |
(258) 0x43f69b ADD %R14,%RBX |
(258) 0x43f69e ADD %RCX,%RDI |
(258) 0x43f6a1 CMP $0x1,%RAX |
(258) 0x43f6a5 LEA 0x1(%RAX),%RAX |
(258) 0x43f6a9 JE 43f000 |
(258) 0x43f6af CMP $0x8,%R9 |
(258) 0x43f6b3 JB 43f727 |
(258) 0x43f6b5 MOV $0x38,%EDX |
(258) 0x43f6ba MOV -0x50(%RBP),%R8 |
(258) 0x43f6be XCHG %AX,%AX |
(259) 0x43f6c0 VMOVSD %XMM0,-0x38(%RDI,%RDX,1) |
(259) 0x43f6c6 VMOVQ %XMM1,-0x38(%RBX,%RDX,1) |
(259) 0x43f6cc VMOVSD %XMM0,-0x30(%RDI,%RDX,1) |
(259) 0x43f6d2 VMOVQ %XMM1,-0x30(%RBX,%RDX,1) |
(259) 0x43f6d8 VMOVSD %XMM0,-0x28(%RDI,%RDX,1) |
(259) 0x43f6de VMOVQ %XMM1,-0x28(%RBX,%RDX,1) |
(259) 0x43f6e4 VMOVSD %XMM0,-0x20(%RDI,%RDX,1) |
(259) 0x43f6ea VMOVQ %XMM1,-0x20(%RBX,%RDX,1) |
(259) 0x43f6f0 VMOVSD %XMM0,-0x18(%RDI,%RDX,1) |
(259) 0x43f6f6 VMOVQ %XMM1,-0x18(%RBX,%RDX,1) |
(259) 0x43f6fc VMOVSD %XMM0,-0x10(%RDI,%RDX,1) |
(259) 0x43f702 VMOVQ %XMM1,-0x10(%RBX,%RDX,1) |
(259) 0x43f708 VMOVSD %XMM0,-0x8(%RDI,%RDX,1) |
(259) 0x43f70e VMOVQ %XMM1,-0x8(%RBX,%RDX,1) |
(259) 0x43f714 VMOVSD %XMM0,(%RDI,%RDX,1) |
(259) 0x43f719 VMOVQ %XMM1,(%RBX,%RDX,1) |
(259) 0x43f71e ADD $0x40,%RDX |
(259) 0x43f722 INC %R8 |
(259) 0x43f725 JNE 43f6c0 |
(258) 0x43f727 CMP $0x3,%RSI |
(258) 0x43f72b JGE 43f780 |
(258) 0x43f72d TEST %RSI,%RSI |
(258) 0x43f730 JLE 43f840 |
(258) 0x43f736 MOV -0x38(%RBP),%RDX |
(258) 0x43f73a ADD %RAX,%RDX |
(258) 0x43f73d SUB -0x30(%RBP),%RDX |
(258) 0x43f741 MOV %RCX,%R8 |
(258) 0x43f744 IMUL %RDX,%R8 |
(258) 0x43f748 IMUL %R14,%RDX |
(258) 0x43f74c CMP $0x1,%RSI |
(258) 0x43f750 JNE 43f65b |
(258) 0x43f756 JMP 43f672 |
(258) 0x43f780 CMP $0x5,%RSI |
(258) 0x43f784 JGE 43f7c0 |
(258) 0x43f786 MOV -0x38(%RBP),%RDX |
(258) 0x43f78a ADD %RAX,%RDX |
(258) 0x43f78d SUB -0x30(%RBP),%RDX |
(258) 0x43f791 MOV %RCX,%R8 |
(258) 0x43f794 IMUL %RDX,%R8 |
(258) 0x43f798 IMUL %R14,%RDX |
(258) 0x43f79c CMP $0x4,%RSI |
(258) 0x43f7a0 JE 43f62d |
(258) 0x43f7a6 JMP 43f644 |
(258) 0x43f7c0 JE 43f600 |
(258) 0x43f7c6 CMP $0x6,%RSI |
(258) 0x43f7ca JNE 43f69b |
(258) 0x43f7d0 MOV -0x38(%RBP),%RDX |
(258) 0x43f7d4 ADD %RAX,%RDX |
(258) 0x43f7d7 SUB -0x30(%RBP),%RDX |
(258) 0x43f7db MOV %RCX,%R8 |
(258) 0x43f7de IMUL %RDX,%R8 |
(258) 0x43f7e2 LEA (%R15,%R8,1),%R11 |
(258) 0x43f7e6 MOV -0xd8(%RBP),%R10 |
(258) 0x43f7ed VMOVSD %XMM0,(%R11,%R10,8) |
(258) 0x43f7f3 IMUL %R14,%RDX |
(258) 0x43f7f7 LEA (%R13,%RDX,1),%R11 |
(258) 0x43f7fc VMOVQ %XMM1,(%R11,%R10,8) |
(258) 0x43f802 JMP 43f616 |
(258) 0x43f840 JNE 43f69b |
(258) 0x43f846 MOV -0x38(%RBP),%RDX |
(258) 0x43f84a ADD %RAX,%RDX |
(258) 0x43f84d SUB -0x30(%RBP),%RDX |
(258) 0x43f851 MOV %RCX,%R8 |
(258) 0x43f854 IMUL %RDX,%R8 |
(258) 0x43f858 IMUL %R14,%RDX |
(258) 0x43f85c JMP 43f689 |
0x43f880 MOV 0x10(%RBP),%RCX |
0x43f884 CMP (%RCX),%EDX |
0x43f886 JNE 43f000 |
0x43f88c MOV %RSI,%RCX |
0x43f88f SUB -0x60(%RBP),%RCX |
0x43f893 MOV 0xb8(%RBP),%RDX |
0x43f89a VMOVSD (%RDX,%RCX,8),%XMM0 |
0x43f89f MOV -0xd0(%RBP),%RDX |
0x43f8a6 VUCOMISD (%RDX),%XMM0 |
0x43f8aa JNE 43f000 |
0x43f8b0 JP 43f000 |
0x43f8b6 MOV 0xb0(%RBP),%RDX |
0x43f8bd MOV -0x78(%RBP),%R8 |
0x43f8c1 VMOVSD (%RDX,%R8,8),%XMM0 |
0x43f8c7 MOV -0xc8(%RBP),%RDX |
0x43f8ce VUCOMISD (%RDX),%XMM0 |
0x43f8d2 JNE 43f000 |
0x43f8d8 JP 43f000 |
0x43f8de MOV 0xe0(%RBP),%RDX |
0x43f8e5 MOV (%RDX),%RDX |
0x43f8e8 MOV -0x78(%RBP),%R11 |
0x43f8ec IMUL %R11,%RDX |
0x43f8f0 ADD 0x90(%RBP),%RDX |
0x43f8f7 MOV 0x68(%RBP),%R8 |
0x43f8fb MOV -0x40(%RBP),%R10 |
0x43f8ff VMOVSD -0x8(%R8,%R10,8),%XMM0 |
0x43f906 VMOVSD %XMM0,(%RDX,%RCX,8) |
0x43f90b MOV 0xf0(%RBP),%RDX |
0x43f912 MOV (%RDX),%RDX |
0x43f915 IMUL %R11,%RDX |
0x43f919 ADD 0x98(%RBP),%RDX |
0x43f920 MOV 0x70(%RBP),%R8 |
0x43f924 VMOVSD -0x8(%R8,%R10,8),%XMM0 |
0x43f92b VMOVSD %XMM0,(%RDX,%RCX,8) |
0x43f930 MOV 0x60(%RBP),%RCX |
0x43f934 VMOVSD -0x8(%RCX,%R10,8),%XMM0 |
0x43f93b MOV 0x100(%RBP),%RCX |
0x43f942 MOV (%RCX),%RCX |
0x43f945 MOV 0x58(%RBP),%RDX |
0x43f949 VMOVQ -0x8(%RDX,%R10,8),%XMM1 |
0x43f950 MOV 0x110(%RBP),%RDX |
0x43f957 MOV (%RDX),%R14 |
0x43f95a INC %RSI |
0x43f95d CMP %RAX,%RSI |
0x43f960 CMOVLE %RAX,%RSI |
0x43f964 SUB %RAX,%RSI |
0x43f967 LEA 0x1(%RSI),%R10 |
0x43f96b MOV %R10,%R12 |
0x43f96e AND $-0x8,%R12 |
0x43f972 SUB %R12,%RSI |
0x43f975 ADD %RAX,%R12 |
0x43f978 SUB -0x60(%RBP),%R12 |
0x43f97c LEA 0x6(%R12),%R9 |
0x43f981 MOV -0xc0(%RBP),%RDX |
0x43f988 MOV %RDX,%RBX |
0x43f98b IMUL %R14,%RBX |
0x43f98f MOV -0xb8(%RBP),%RAX |
0x43f996 ADD %RDI,%RAX |
0x43f999 ADD %RAX,%RBX |
0x43f99c MOV %RDX,%RAX |
0x43f99f IMUL %RCX,%RAX |
0x43f9a3 ADD -0xb0(%RBP),%RDI |
0x43f9aa ADD %RAX,%RDI |
0x43f9ad XOR %EAX,%EAX |
0x43f9af JMP 43fa6f |
(256) 0x43f9c0 MOV -0x38(%RBP),%RDX |
(256) 0x43f9c4 ADD %RAX,%RDX |
(256) 0x43f9c7 SUB -0x30(%RBP),%RDX |
(256) 0x43f9cb MOV %RCX,%R8 |
(256) 0x43f9ce IMUL %RDX,%R8 |
(256) 0x43f9d2 IMUL %R14,%RDX |
(256) 0x43f9d6 LEA (%R15,%R8,1),%R11 |
(256) 0x43f9da VMOVSD %XMM0,0x28(%R11,%R12,8) |
(256) 0x43f9e1 LEA (%R13,%RDX,1),%R11 |
(256) 0x43f9e6 VMOVQ %XMM1,0x28(%R11,%R12,8) |
(256) 0x43f9ed LEA (%R15,%R8,1),%R11 |
(256) 0x43f9f1 VMOVSD %XMM0,0x20(%R11,%R12,8) |
(256) 0x43f9f8 LEA (%R13,%RDX,1),%R11 |
(256) 0x43f9fd VMOVQ %XMM1,0x20(%R11,%R12,8) |
(256) 0x43fa04 LEA (%R15,%R8,1),%R11 |
(256) 0x43fa08 VMOVSD %XMM0,0x18(%R11,%R12,8) |
(256) 0x43fa0f LEA (%R13,%RDX,1),%R11 |
(256) 0x43fa14 VMOVQ %XMM1,0x18(%R11,%R12,8) |
(256) 0x43fa1b LEA (%R15,%R8,1),%R11 |
(256) 0x43fa1f VMOVSD %XMM0,0x10(%R11,%R12,8) |
(256) 0x43fa26 LEA (%R13,%RDX,1),%R11 |
(256) 0x43fa2b VMOVQ %XMM1,0x10(%R11,%R12,8) |
(256) 0x43fa32 LEA (%R15,%R8,1),%R11 |
(256) 0x43fa36 VMOVSD %XMM0,0x8(%R11,%R12,8) |
(256) 0x43fa3d LEA (%R13,%RDX,1),%R11 |
(256) 0x43fa42 VMOVQ %XMM1,0x8(%R11,%R12,8) |
(256) 0x43fa49 ADD %R15,%R8 |
(256) 0x43fa4c VMOVSD %XMM0,(%R8,%R12,8) |
(256) 0x43fa52 ADD %R13,%RDX |
(256) 0x43fa55 VMOVQ %XMM1,(%RDX,%R12,8) |
(256) 0x43fa5b ADD %R14,%RBX |
(256) 0x43fa5e ADD %RCX,%RDI |
(256) 0x43fa61 CMP $0x1,%RAX |
(256) 0x43fa65 LEA 0x1(%RAX),%RAX |
(256) 0x43fa69 JE 43f000 |
(256) 0x43fa6f CMP $0x8,%R10 |
(256) 0x43fa73 JB 43fae7 |
(256) 0x43fa75 MOV $0x38,%EDX |
(256) 0x43fa7a MOV -0x50(%RBP),%R8 |
(256) 0x43fa7e XCHG %AX,%AX |
(257) 0x43fa80 VMOVSD %XMM0,-0x38(%RDI,%RDX,1) |
(257) 0x43fa86 VMOVQ %XMM1,-0x38(%RBX,%RDX,1) |
(257) 0x43fa8c VMOVSD %XMM0,-0x30(%RDI,%RDX,1) |
(257) 0x43fa92 VMOVQ %XMM1,-0x30(%RBX,%RDX,1) |
(257) 0x43fa98 VMOVSD %XMM0,-0x28(%RDI,%RDX,1) |
(257) 0x43fa9e VMOVQ %XMM1,-0x28(%RBX,%RDX,1) |
(257) 0x43faa4 VMOVSD %XMM0,-0x20(%RDI,%RDX,1) |
(257) 0x43faaa VMOVQ %XMM1,-0x20(%RBX,%RDX,1) |
(257) 0x43fab0 VMOVSD %XMM0,-0x18(%RDI,%RDX,1) |
(257) 0x43fab6 VMOVQ %XMM1,-0x18(%RBX,%RDX,1) |
(257) 0x43fabc VMOVSD %XMM0,-0x10(%RDI,%RDX,1) |
(257) 0x43fac2 VMOVQ %XMM1,-0x10(%RBX,%RDX,1) |
(257) 0x43fac8 VMOVSD %XMM0,-0x8(%RDI,%RDX,1) |
(257) 0x43face VMOVQ %XMM1,-0x8(%RBX,%RDX,1) |
(257) 0x43fad4 VMOVSD %XMM0,(%RDI,%RDX,1) |
(257) 0x43fad9 VMOVQ %XMM1,(%RBX,%RDX,1) |
(257) 0x43fade ADD $0x40,%RDX |
(257) 0x43fae2 INC %R8 |
(257) 0x43fae5 JNE 43fa80 |
(256) 0x43fae7 CMP $0x3,%RSI |
(256) 0x43faeb JGE 43fb40 |
(256) 0x43faed TEST %RSI,%RSI |
(256) 0x43faf0 JLE 43fbc0 |
(256) 0x43faf6 MOV -0x38(%RBP),%RDX |
(256) 0x43fafa ADD %RAX,%RDX |
(256) 0x43fafd SUB -0x30(%RBP),%RDX |
(256) 0x43fb01 MOV %RCX,%R8 |
(256) 0x43fb04 IMUL %RDX,%R8 |
(256) 0x43fb08 IMUL %R14,%RDX |
(256) 0x43fb0c CMP $0x1,%RSI |
(256) 0x43fb10 JNE 43fa1b |
(256) 0x43fb16 JMP 43fa32 |
(256) 0x43fb40 CMP $0x5,%RSI |
(256) 0x43fb44 JGE 43fb80 |
(256) 0x43fb46 MOV -0x38(%RBP),%RDX |
(256) 0x43fb4a ADD %RAX,%RDX |
(256) 0x43fb4d SUB -0x30(%RBP),%RDX |
(256) 0x43fb51 MOV %RCX,%R8 |
(256) 0x43fb54 IMUL %RDX,%R8 |
(256) 0x43fb58 IMUL %R14,%RDX |
(256) 0x43fb5c CMP $0x4,%RSI |
(256) 0x43fb60 JE 43f9ed |
(256) 0x43fb66 JMP 43fa04 |
(256) 0x43fb80 JE 43f9c0 |
(256) 0x43fb86 CMP $0x6,%RSI |
(256) 0x43fb8a JNE 43fa5b |
(256) 0x43fb90 MOV -0x38(%RBP),%RDX |
(256) 0x43fb94 ADD %RAX,%RDX |
(256) 0x43fb97 SUB -0x30(%RBP),%RDX |
(256) 0x43fb9b MOV %RCX,%R8 |
(256) 0x43fb9e IMUL %RDX,%R8 |
(256) 0x43fba2 LEA (%R15,%R8,1),%R11 |
(256) 0x43fba6 VMOVSD %XMM0,(%R11,%R9,8) |
(256) 0x43fbac IMUL %R14,%RDX |
(256) 0x43fbb0 LEA (%R13,%RDX,1),%R11 |
(256) 0x43fbb5 VMOVQ %XMM1,(%R11,%R9,8) |
(256) 0x43fbbb JMP 43f9d6 |
(256) 0x43fbc0 JNE 43fa5b |
(256) 0x43fbc6 MOV -0x38(%RBP),%RDX |
(256) 0x43fbca ADD %RAX,%RDX |
(256) 0x43fbcd SUB -0x30(%RBP),%RDX |
(256) 0x43fbd1 MOV %RCX,%R8 |
(256) 0x43fbd4 IMUL %RDX,%R8 |
(256) 0x43fbd8 IMUL %R14,%RDX |
(256) 0x43fbdc JMP 43fa49 |
/scratch_na/users/xoserete/qaas_runs/171-215-0463/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 87 - 163 |
-------------------------------------------------------------------------------- |
87: DO k=y_min-2,y_max+2 |
[...] |
128: DO j=x_min-2,x_max+2 |
129: IF(state_geometry(state).EQ.g_rect ) THEN |
130: IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN |
131: IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN |
132: energy0(j,k)=state_energy(state) |
133: density0(j,k)=state_density(state) |
134: DO kt=k,k+1 |
135: DO jt=j,j+1 |
136: xvel0(jt,kt)=state_xvel(state) |
137: yvel0(jt,kt)=state_yvel(state) |
138: ENDDO |
139: ENDDO |
140: ENDIF |
141: ENDIF |
142: ELSEIF(state_geometry(state).EQ.g_circ ) THEN |
143: radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent)) |
144: IF(radius.LE.state_radius(state))THEN |
145: energy0(j,k)=state_energy(state) |
146: density0(j,k)=state_density(state) |
147: DO kt=k,k+1 |
148: DO jt=j,j+1 |
149: xvel0(jt,kt)=state_xvel(state) |
150: yvel0(jt,kt)=state_yvel(state) |
151: ENDDO |
152: ENDDO |
153: ENDIF |
154: ELSEIF(state_geometry(state).EQ.g_point) THEN |
155: IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN |
156: energy0(j,k)=state_energy(state) |
157: density0(j,k)=state_density(state) |
158: DO kt=k,k+1 |
159: DO jt=j,j+1 |
160: xvel0(jt,kt)=state_xvel(state) |
161: yvel0(jt,kt)=state_yvel(state) |
162: ENDDO |
163: ENDDO |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 3.25 |
CQA speedup if FP arith vectorized | 2.72 |
CQA speedup if fully vectorized | 12.76 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | P2, P3, P11, |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source | generate_chunk_kernel.f90:87-87,generate_chunk_kernel.f90:128-133,generate_chunk_kernel.f90:136-137,generate_chunk_kernel.f90:142-146,generate_chunk_kernel.f90:149-150,generate_chunk_kernel.f90:154-157,generate_chunk_kernel.f90:160-161 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 43.33 |
CQA cycles if no scalar integer | 13.33 |
CQA cycles if FP arith vectorized | 15.92 |
CQA cycles if fully vectorized | 3.40 |
Front-end cycles | 40.67 |
DIV/SQRT cycles | 18.20 |
P0 cycles | 21.93 |
P1 cycles | 43.33 |
P2 cycles | 43.33 |
P3 cycles | 6.00 |
P4 cycles | 18.20 |
P5 cycles | 18.20 |
P6 cycles | 6.00 |
P7 cycles | 6.00 |
P8 cycles | 6.00 |
P9 cycles | 18.20 |
P10 cycles | 43.33 |
P11 cycles | 4.50 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 49.30 - 49.34 |
Stall cycles (UFS) | 8.38 - 8.37 |
Nb insns | 238.00 |
Nb uops | 244.00 |
Nb loads | 130.00 |
Nb stores | 12.00 |
Nb stack references | 39.00 |
FLOP/cycle | 0.14 |
Nb FLOP add-sub | 2.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 1.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.66 |
Bytes prefetched | 0.00 |
Bytes loaded | 1020.00 |
Bytes stored | 92.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.12 |
Vector-efficiency ratio load | 11.98 |
Vector-efficiency ratio store | 11.98 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 11.46 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 3.25 |
CQA speedup if FP arith vectorized | 2.72 |
CQA speedup if fully vectorized | 12.76 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | P2, P3, P11, |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source | generate_chunk_kernel.f90:87-87,generate_chunk_kernel.f90:128-133,generate_chunk_kernel.f90:136-137,generate_chunk_kernel.f90:142-146,generate_chunk_kernel.f90:149-150,generate_chunk_kernel.f90:154-157,generate_chunk_kernel.f90:160-161 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 43.33 |
CQA cycles if no scalar integer | 13.33 |
CQA cycles if FP arith vectorized | 15.92 |
CQA cycles if fully vectorized | 3.40 |
Front-end cycles | 40.67 |
DIV/SQRT cycles | 18.20 |
P0 cycles | 21.93 |
P1 cycles | 43.33 |
P2 cycles | 43.33 |
P3 cycles | 6.00 |
P4 cycles | 18.20 |
P5 cycles | 18.20 |
P6 cycles | 6.00 |
P7 cycles | 6.00 |
P8 cycles | 6.00 |
P9 cycles | 18.20 |
P10 cycles | 43.33 |
P11 cycles | 4.50 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 49.30 - 49.34 |
Stall cycles (UFS) | 8.38 - 8.37 |
Nb insns | 238.00 |
Nb uops | 244.00 |
Nb loads | 130.00 |
Nb stores | 12.00 |
Nb stack references | 39.00 |
FLOP/cycle | 0.14 |
Nb FLOP add-sub | 2.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 1.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.66 |
Bytes prefetched | 0.00 |
Bytes loaded | 1020.00 |
Bytes stored | 92.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.12 |
Vector-efficiency ratio load | 11.98 |
Vector-efficiency ratio store | 11.98 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 11.46 |
Path / |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | generate_chunk_kernel.f90:87-163 |
Module | exec |
nb instructions | 238 |
nb uops | 244 |
loop length | 1128 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 39 |
ADD-SUB / MUL ratio | 2.00 |
micro-operation queue | 40.67 cycles |
front end | 40.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 18.20 | 18.20 | 43.33 | 43.33 | 6.00 | 18.20 | 18.20 | 6.00 | 6.00 | 6.00 | 18.20 | 43.33 |
cycles | 18.20 | 21.93 | 43.33 | 43.33 | 6.00 | 18.20 | 18.20 | 6.00 | 6.00 | 6.00 | 18.20 | 43.33 |
Cycles executing div or sqrt instructions | 4.50 |
FE+BE cycles | 49.30-49.34 |
Stall cycles | 8.39-8.37 |
LM full (events) | 17.10 |
Front-end | 40.67 |
Dispatch | 43.33 |
DIV/SQRT | 4.50 |
Overall L1 | 43.33 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 11% |
load | 10% |
store | 11% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 12% |
load | 11% |
store | 11% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x68(%RBP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x80(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x70(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0x168(%RBP),%R11 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0xf4(%RBP),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 43ef40 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x590> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R10D,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA (,%RAX,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMOVG %R8,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
INC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x3,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
NEG %RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x160(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R11,%RCX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP -0xf0(%RBP),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R8,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 43f200 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x850> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x1(%RSI),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x60(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%R8,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RDX,%R8,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB -0x60(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RDX,%RSI,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xb0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x158(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RDX,%R8,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x38(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RDX,%R8,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x98(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDX,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ -0x8(%RDX,%R10,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RAX,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RCX),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R10,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x60(%RBP),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%R10),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xc0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R14,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R8,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb0(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43f42f <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xa7f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RCX),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 43f880 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xed0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x60(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xd0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD (%RDX),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULSD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0xa0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX,%R8,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xc8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD (%RDX),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD213SD %XMM0,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSQRTSD %XMM1,%XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
MOV 0x30(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDX,%R8,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD %XMM0,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JB 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x98(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ -0x8(%RDX,%R10,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RAX,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RSI),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x60(%RBP),%R12 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%R12),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xc0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R14,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb0(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43f6af <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xcff> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x10(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RCX),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x60(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xd0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RDX),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JNE 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xb0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xc8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RDX),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JNE 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x98(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ -0x8(%RDX,%R10,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RAX,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RSI),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x60(%RBP),%R12 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%R12),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xc0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R14,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb0(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43fa6f <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x10bf> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | generate_chunk_kernel.f90:87-163 |
Module | exec |
nb instructions | 238 |
nb uops | 244 |
loop length | 1128 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 39 |
ADD-SUB / MUL ratio | 2.00 |
micro-operation queue | 40.67 cycles |
front end | 40.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 18.20 | 18.20 | 43.33 | 43.33 | 6.00 | 18.20 | 18.20 | 6.00 | 6.00 | 6.00 | 18.20 | 43.33 |
cycles | 18.20 | 21.93 | 43.33 | 43.33 | 6.00 | 18.20 | 18.20 | 6.00 | 6.00 | 6.00 | 18.20 | 43.33 |
Cycles executing div or sqrt instructions | 4.50 |
FE+BE cycles | 49.30-49.34 |
Stall cycles | 8.39-8.37 |
LM full (events) | 17.10 |
Front-end | 40.67 |
Dispatch | 43.33 |
DIV/SQRT | 4.50 |
Overall L1 | 43.33 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 11% |
load | 10% |
store | 11% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 12% |
load | 11% |
store | 11% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x68(%RBP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x80(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x70(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0x168(%RBP),%R11 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0xf4(%RBP),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 43ef40 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x590> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R10D,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA (,%RAX,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMOVG %R8,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
INC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x3,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
NEG %RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x160(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R11,%RCX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP -0xf0(%RBP),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R8,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 43f200 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x850> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x1(%RSI),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x60(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%R8,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RDX,%R8,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB -0x60(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RDX,%RSI,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xb0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x158(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RDX,%R8,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x38(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RDX,%R8,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x98(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDX,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ -0x8(%RDX,%R10,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RAX,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RCX),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R10,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x60(%RBP),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%R10),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xc0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R14,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R8,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb0(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43f42f <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xa7f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RCX),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 43f880 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xed0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x60(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xd0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD (%RDX),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULSD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0xa0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX,%R8,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xc8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD (%RDX),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD213SD %XMM0,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSQRTSD %XMM1,%XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
MOV 0x30(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDX,%R8,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD %XMM0,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JB 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x98(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ -0x8(%RDX,%R10,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RAX,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RSI),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x60(%RBP),%R12 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%R12),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0xd8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xc0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R14,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb0(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43f6af <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xcff> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x10(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RCX),%EDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x60(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xd0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RDX),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JNE 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xb0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xc8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RDX),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JNE 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 43f000 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x650> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x98(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDX,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%R10,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ -0x8(%RDX,%R10,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RAX,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RSI),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x60(%RBP),%R12 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%R12),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xc0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R14,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb0(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43fa6f <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x10bf> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |