Loop Id: 368 | Module: exec | Source: revert_kernel.f90:47-48 | Coverage: 2.3% |
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Loop Id: 368 | Module: exec | Source: revert_kernel.f90:47-48 | Coverage: 2.3% |
---|
0x460085 VMOVUPD (%R14,%RAX,1),%ZMM14 [2] |
0x46008c VMOVUPD %ZMM14,(%R15,%RAX,1) [4] |
0x460093 VMOVUPD (%R13,%RAX,1),%ZMM15 [1] |
0x46009b VMOVUPD %ZMM15,(%RBX,%RAX,1) [5] |
0x4600a2 VMOVUPD 0x40(%R14,%RAX,1),%ZMM3 [2] |
0x4600aa VMOVUPD %ZMM3,0x40(%R15,%RAX,1) [4] |
0x4600b2 VMOVUPD 0x40(%R13,%RAX,1),%ZMM4 [1] |
0x4600ba VMOVUPD %ZMM4,0x40(%RBX,%RAX,1) [5] |
0x4600c2 VMOVUPD 0x80(%R14,%RAX,1),%ZMM1 [2] |
0x4600ca VMOVUPD %ZMM1,0x80(%R15,%RAX,1) [4] |
0x4600d2 VMOVUPD 0x80(%R13,%RAX,1),%ZMM2 [1] |
0x4600da VMOVUPD %ZMM2,0x80(%RBX,%RAX,1) [5] |
0x4600e2 VMOVUPD 0xc0(%R14,%RAX,1),%ZMM0 [2] |
0x4600ea VMOVUPD %ZMM0,0xc0(%R15,%RAX,1) [4] |
0x4600f2 VMOVUPD 0xc0(%R13,%RAX,1),%ZMM5 [1] |
0x4600fa VMOVUPD %ZMM5,0xc0(%RBX,%RAX,1) [5] |
0x460102 VMOVUPD 0x100(%R14,%RAX,1),%ZMM6 [2] |
0x46010a VMOVUPD %ZMM6,0x100(%R15,%RAX,1) [4] |
0x460112 VMOVUPD 0x100(%R13,%RAX,1),%ZMM7 [1] |
0x46011a VMOVUPD %ZMM7,0x100(%RBX,%RAX,1) [5] |
0x460122 VMOVUPD 0x140(%R14,%RAX,1),%ZMM8 [2] |
0x46012a VMOVUPD %ZMM8,0x140(%R15,%RAX,1) [4] |
0x460132 VMOVUPD 0x140(%R13,%RAX,1),%ZMM9 [1] |
0x46013a VMOVUPD %ZMM9,0x140(%RBX,%RAX,1) [5] |
0x460142 VMOVUPD 0x180(%R14,%RAX,1),%ZMM10 [2] |
0x46014a VMOVUPD %ZMM10,0x180(%R15,%RAX,1) [4] |
0x460152 VMOVUPD 0x180(%R13,%RAX,1),%ZMM11 [1] |
0x46015a VMOVUPD %ZMM11,0x180(%RBX,%RAX,1) [5] |
0x460162 VMOVUPD 0x1c0(%R14,%RAX,1),%ZMM12 [2] |
0x46016a VMOVUPD %ZMM12,0x1c0(%R15,%RAX,1) [4] |
0x460172 VMOVUPD 0x1c0(%R13,%RAX,1),%ZMM13 [1] |
0x46017a VMOVUPD %ZMM13,0x1c0(%RBX,%RAX,1) [5] |
0x460182 ADD $0x200,%RAX |
0x460188 CMP %RAX,0x70(%RSP) [3] |
0x46018d JNE 460085 |
/scratch_na/users/xoserete/qaas_runs/171-215-0463/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90: 47 - 48 |
-------------------------------------------------------------------------------- |
47: density1(j,k)=density0(j,k) |
48: energy1(j,k)=energy0(j,k) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.41 |
Bottlenecks | P4, P7, P8, P9, |
Function | revert_kernel._omp_fn.0 |
Source | revert_kernel.f90:47-48 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.00 |
CQA cycles if no scalar integer | 8.00 |
CQA cycles if FP arith vectorized | 8.00 |
CQA cycles if fully vectorized | 8.00 |
Front-end cycles | 5.67 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.40 |
P1 cycles | 5.67 |
P2 cycles | 5.67 |
P3 cycles | 8.00 |
P4 cycles | 0.40 |
P5 cycles | 0.50 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.20 |
P10 cycles | 5.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 8.12 |
Stall cycles (UFS) | 2.06 |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 17.00 |
Nb stores | 16.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 257.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 1032.00 |
Bytes stored | 1024.00 |
Stride 0 | 1.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.41 |
Bottlenecks | P4, P7, P8, P9, |
Function | revert_kernel._omp_fn.0 |
Source | revert_kernel.f90:47-48 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.00 |
CQA cycles if no scalar integer | 8.00 |
CQA cycles if FP arith vectorized | 8.00 |
CQA cycles if fully vectorized | 8.00 |
Front-end cycles | 5.67 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.40 |
P1 cycles | 5.67 |
P2 cycles | 5.67 |
P3 cycles | 8.00 |
P4 cycles | 0.40 |
P5 cycles | 0.50 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.20 |
P10 cycles | 5.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 8.12 |
Stall cycles (UFS) | 2.06 |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 17.00 |
Nb stores | 16.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 257.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 1032.00 |
Bytes stored | 1024.00 |
Stride 0 | 1.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | revert_kernel._omp_fn.0 |
Source file and lines | revert_kernel.f90:47-48 |
Module | exec |
nb instructions | 35 |
nb uops | 34 |
loop length | 270 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 1 |
micro-operation queue | 5.67 cycles |
front end | 5.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.40 | 5.67 | 5.67 | 8.00 | 0.40 | 0.50 | 8.00 | 8.00 | 8.00 | 0.20 | 5.67 |
cycles | 0.50 | 0.40 | 5.67 | 5.67 | 8.00 | 0.40 | 0.50 | 8.00 | 8.00 | 8.00 | 0.20 | 5.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 8.12 |
Stall cycles | 2.06 |
RS full (events) | 7.09 |
Front-end | 5.67 |
Dispatch | 8.00 |
Data deps. | 1.00 |
Overall L1 | 8.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R14,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM14,(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD (%R13,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM15,(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%R14,%RAX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM3,0x40(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%R13,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM4,0x40(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%R14,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM1,0x80(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%R13,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM2,0x80(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%R14,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM0,0xc0(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%R13,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM5,0xc0(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x100(%R14,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM6,0x100(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x100(%R13,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM7,0x100(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x140(%R14,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM8,0x140(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x140(%R13,%RAX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM9,0x140(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x180(%R14,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM10,0x180(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x180(%R13,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM11,0x180(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x1c0(%R14,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM12,0x1c0(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x1c0(%R13,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM13,0x1c0(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x200,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RAX,0x70(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 460085 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x2c5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | revert_kernel._omp_fn.0 |
Source file and lines | revert_kernel.f90:47-48 |
Module | exec |
nb instructions | 35 |
nb uops | 34 |
loop length | 270 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 16 |
nb stack references | 1 |
micro-operation queue | 5.67 cycles |
front end | 5.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.40 | 5.67 | 5.67 | 8.00 | 0.40 | 0.50 | 8.00 | 8.00 | 8.00 | 0.20 | 5.67 |
cycles | 0.50 | 0.40 | 5.67 | 5.67 | 8.00 | 0.40 | 0.50 | 8.00 | 8.00 | 8.00 | 0.20 | 5.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 8.12 |
Stall cycles | 2.06 |
RS full (events) | 7.09 |
Front-end | 5.67 |
Dispatch | 8.00 |
Data deps. | 1.00 |
Overall L1 | 8.00 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R14,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM14,(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD (%R13,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM15,(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%R14,%RAX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM3,0x40(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x40(%R13,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM4,0x40(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%R14,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM1,0x80(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x80(%R13,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM2,0x80(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%R14,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM0,0xc0(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0xc0(%R13,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM5,0xc0(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x100(%R14,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM6,0x100(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x100(%R13,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM7,0x100(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x140(%R14,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM8,0x140(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x140(%R13,%RAX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM9,0x140(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x180(%R14,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM10,0x180(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x180(%R13,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM11,0x180(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x1c0(%R14,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM12,0x1c0(%R15,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVUPD 0x1c0(%R13,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD %ZMM13,0x1c0(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD $0x200,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RAX,0x70(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 460085 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x2c5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |