	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/armclang/oneview_results_1785426560 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/armclang/oneview_results_1785426560


+===================================================================================================================+
+                                                   1  -  GLOBAL                                                    +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                            1.1  -  Experiment Summary                                             +
+-------------------------------------------------------------------------------------------------------------------+

  Application:			/home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/orig/exec
  Timestamp:			2026-07-30 15:49:20
  Universal Timestamp:		1785426560
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			ip-172-31-9-132.ec2.internal
  Architecture:			aarch64
  Micro Architecture:		ARM_NEOVERSE_V2
  OS Version:			Linux 6.1.170-213.321.amzn2023.aarch64 #1 SMP Thu May 14 12:18:13 UTC 2026
  Compilation Options:		
		exec: Arm Toolchain for Linux 22.1.0 flang version 22.1.0 (https://github.com/arm/arm-toolchain.git c95792353373404441df364b5a762338e5642230) 
  Number of processes observed:	1
  Number of threads observed:	96
  MAQAO version:		2026.0.1
  MAQAO build:			Build information not available




+-------------------------------------------------------------------------------------------------------------------+
+                                              1.2  -  Global Metrics                                               +
+-------------------------------------------------------------------------------------------------------------------+

  Total Time:				84.17 s
  Max (Thread Active Time):		80.76 s
  Average Active Time:			80.75 s
  Activity Ratio:			99.8 %
  Average number of active threads:	92.089
  Affinity Stability:			99.9 %
  Time spent in analyzed loops:		95.6 %
  Time spent in analyzed innermost loops: 84.3 %
  Time spent in user code:		95.7 %
  Compilation Options Score:		16.67
  Array Access Efficiency:		13.5 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.01
  Perfect OpenMP/MPI/Pthread/TBB:	1.01
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.02
  If No Scalar Integer:
      Potential Speedup:		1.21
      Nb Loops to get 80%:		9
  If FP Vectorized:
      Potential Speedup:		1.07
      Nb Loops to get 80%:		4
  If Fully Vectorized:
      Potential Speedup:		1.11
      Nb Loops to get 80%:		6
  If Only FP Arithmetic:
      Potential Speedup:		1.28
      Nb Loops to get 80%:		13




+-------------------------------------------------------------------------------------------------------------------+
+                                            1.3  -  Potential Speedups                                             +
+-------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 8      | 17     | 25     | 34     | 
      Cumulated Speedup | 1.0320 | 1.1612 | 1.2044 | 1.2072 | 1.2072 | 
  Top 5 loops:
    exec - 161:	1.032
    exec - 154:	1.0644
    exec - 87:	1.0932
    exec - 78:	1.118
    exec - 273:	1.1322

  If FP Vectorized:
      Number of loops   | 1      | 8      | 17     | 25     | 34     | 
      Cumulated Speedup | 1.0198 | 1.0676 | 1.0676 | 1.0676 | 1.0676 | 
  Top 5 loops:
    exec - 161:	1.0198
    exec - 154:	1.0394
    exec - 87:	1.0496
    exec - 273:	1.0589
    exec - 78:	1.0676

  If Fully Vectorized:
      Number of loops   | 1      | 8      | 17     | 25     | 34     | 
      Cumulated Speedup | 1.0198 | 1.0955 | 1.1096 | 1.1109 | 1.1109 | 
  Top 5 loops:
    exec - 161:	1.0198
    exec - 87:	1.0404
    exec - 154:	1.0608
    exec - 78:	1.0776
    exec - 273:	1.0874

  If Only FP Arithmetic:
      Number of loops   | 1      | 8      | 17     | 25     | 34     | 
      Cumulated Speedup | 1.0224 | 1.1708 | 1.2717 | 1.2795 | 1.2795 | 
  Top 5 loops:
    exec - 182:	1.0224
    exec - 302:	1.0434
    exec - 62:	1.0647
    exec - 190:	1.0849
    exec - 162:	1.1057



+===================================================================================================================+
+                                                   2  -  SUMMARY                                                   +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                            2.1  -  EXPERIMENT QUALITY                                             +
+-------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (80.76 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [0 / 3] Most of time spent in analyzed modules comes from functions without source/debug info
Functions without source/debug info (typically not compiled with -g) cumulate 52.36% of the time spent in analyzed
modules. Check that -g is present. Remark: if -g is indeed used, this can also be due to some compiler built-in
functions (typically math) or statically linked libraries. This warning can be ignored in that case.

  [0 / 3] Architecture specific options are unknown for some functions (compilation options info are not available)
Architecture specific options are needed to produce efficient code for a specific processor ( -mcpu=native ).

  [0 / 3] Most of time spent in analyzed modules comes from functions without compilation options informations
Functions without compilation options information cumulate 95.69% of the time spent in analyzed modules. For exec,
check that both -g and -frecord-command-line are present. Remark: if such options are indeed used, this can also be
due to some compiler built-in functions (typically math) or statically linked libraries. This warning can be ignored
in that case.

  [0 / 3] Optimization level is unknown for some functions (compilation options info are not available)
To have better performances, it is advised to help the compiler by using a proper optimization level (-O2 of higher).
Warning, depending on compilers, faster optimization levels can decrease numeric accuracy.

  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.00 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the
execution time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+-------------------------------------------------------------------------------------------------------------------+
+                                               2.2  -  CODE QUALITY                                                +
+-------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (95.58%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 95.93% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.83% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (7.43%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (84.31%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.93%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [3 / 3] Functions mostly use all threads
Functions running on a reduced number of threads (typically sequential code) cover less than 10% of application
walltime (1.44%)

  [3 / 3] Cumulative Outermost/In between loops coverage (11.27%) lower than cumulative innermost loop coverage (84.31%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+-------------------------------------------------------------------------------------------------------------------+
+                                              2.3  -  LOOPS OVERVIEW                                               +
+-------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 43  :
     analysis: Execution Time: 7 % - Vectorization Ratio: 96.77 % - Vector Length Use: 97.58 %
     Loop Computation Issues: 16
        [16] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 4
            issues (= instructions) costing 4 points each.
     Data Access Issues: 56
        [56] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 14 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 56
        [56] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 14 issues ( = indirect data accesses) costing 4 point each.

   + exec - 62  :
     analysis: Execution Time: 6 % - Vectorization Ratio: 91.80 % - Vector Length Use: 95.49 %
     Loop Computation Issues: 4
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
     Data Access Issues: 60
        [60] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 15 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 60
        [60] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 15 issues ( = indirect data accesses) costing 4 point each.

   + exec - 47  :
     analysis: Execution Time: 5 % - Vectorization Ratio: 96.55 % - Vector Length Use: 97.41 %
     Loop Computation Issues: 16
        [16] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 4
            issues (= instructions) costing 4 points each.
     Data Access Issues: 48
        [48] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 12 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 48
        [48] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 12 issues ( = indirect data accesses) costing 4 point each.

   + exec - 392 :
     analysis: Execution Time: 4 % - Vectorization Ratio: 92.31 % - Vector Length Use: 94.23 %
     Loop Computation Issues: 8
        [8] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 2
            issues (= instructions) costing 4 points each.
     Data Access Issues: 16
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 16
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.

   + exec - 155 :
     analysis: Execution Time: 4 % - Vectorization Ratio: 88.89 % - Vector Length Use: 92.59 %
     Loop Computation Issues: 16
        [16] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 4
            issues (= instructions) costing 4 points each.
     Data Access Issues: 10
        [10] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 5 issues ( = data accesses) costing 2
            point each.
     Vectorization Roadblocks: 10
        [10] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 5 issues ( = data accesses) costing 2
            point each.



+===================================================================================================================+
+                                                 3  -  APPLICATION                                                 +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                              3.1  -  Categorization                                               +
+-------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+--------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 95.69  | 1.97    | 0.00   | 0.00   | 0.00   | 0.00  | 0.00  | 2.34  | 0.00    | 0.00  |




+-------------------------------------------------------------------------------------------------------------------+
+                                         3.2  -  Function Based Profiling                                          +
+-------------------------------------------------------------------------------------------------------------------+

   Buckets                   | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ---------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                      | 3                         | 67.68                     | 67.68                     |
   4% to 8%                  | 4                         | 19.22                     | 86.90                     |
   2% to 4%                  | 3                         | 8.30                      | 95.20                     |
   1% to 2%                  | 1                         | 1.75                      | 96.94                     |
   0.5% to 1%                | 2                         | 1.51                      | 98.45                     |
   0.25% to 0.5%             | 3                         | 0.83                      | 99.28                     |
   0.125% to 0.25%           | 0                         | 0.00                      | 99.28                     |
   < 0.125%                  | 50                        | 0.65                      | 99.93                     |




+-------------------------------------------------------------------------------------------------------------------+
+                                           3.3  -  Loop Based Profiling                                            +
+-------------------------------------------------------------------------------------------------------------------+

   Buckets                   | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ---------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                      | 0                         | 0.00                      | 0.00                      |
   4% to 8%                  | 7                         | 37.35                     | 37.35                     |
   2% to 4%                  | 14                        | 39.58                     | 76.94                     |
   1% to 2%                  | 6                         | 6.96                      | 83.90                     |
   0.5% to 1%                | 0                         | 0.00                      | 83.90                     |
   0.25% to 0.5%             | 1                         | 0.31                      | 84.21                     |
   0.125% to 0.25%           | 0                         | 0.00                      | 84.21                     |
   < 0.125%                  | 23                        | 0.09                      | 84.31                     |


+===================================================================================================================+
+                                                  4  -  FUNCTIONS                                                  +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                             4.1  -  Top 10 Functions                                              +
+-------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module               | Coverage (%)  | Time (s)      |
  --------------------------------------------------------+----------------------+---------------+---------------+
   _QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par      | exec                 | 35.81         | 28.91         |
   _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par | exec                 | 18.69         | 15.09         |
   _QMpdv_kernel_modulePpdv_kernel..omp_par               | exec                 | 13.19         | 10.65         |
   _QMaccelerate_kernel_modulePaccelerate_kernel..omp_par | exec                 | 6.17          | 4.98          |
   _QMideal_gas_kernel_modulePideal_gas_kernel..omp_par   | exec                 | 4.55          | 3.68          |
   _QMflux_calc_kernel_modulePflux_calc_kernel..omp_par   | exec                 | 4.42          | 3.57          |
   _QMreset_field_kernel_modulePreset_field_kernel..om... | exec                 | 4.07          | 3.29          |
   _QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par       | exec                 | 3.56          | 2.88          |
   _QMviscosity_kernel_modulePviscosity_kernel..omp_par   | exec                 | 2.69          | 2.17          |
   _QMrevert_kernel_modulePrevert_kernel..omp_par         | exec                 | 2.05          | 1.65          |


+===================================================================================================================+
+                                                    5  -  LOOPS                                                    +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                               5.1  -  Top 10 Loops                                                +
+-------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module               | Source Location                                       | Coverage (%)  |
  ----------------+----------------------+-------------------------------------------------------+---------------+
   43             | exec                 | PdV_kernel.f90:110-123,PdV_kernel.f90:129-135         | 7.43          |
   62             | exec                 | accelerate_kernel.f90:61-63,accelerate_kernel.f90:... | 6.17          |
   47             | exec                 | PdV_kernel.f90:74-87,PdV_kernel.f90:93-99             | 5.75          |
   392            | exec                 | ideal_gas_kernel.f90:48-55                            | 4.55          |
   155            | exec                 | advec_mom_kernel.f90:246-248                          | 4.54          |
   151            | exec                 | advec_mom_kernel.f90:182-184                          | 4.49          |
   302            | exec                 | flux_calc_kernel.f90:55-59                            | 4.42          |
   82             | exec                 | advec_cell_kernel.f90:254-261                         | 3.92          |
   161            | exec                 | advec_mom_kernel.f90:214-215,advec_mom_kernel.f90:... | 3.89          |
   154            | exec                 | advec_mom_kernel.f90:149-154,advec_mom_kernel.f90:... | 3.70          |





+===================================================================================================================+
+                                                     6  -  CQA                                                     +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                   +
+-------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 43 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:110-123,129-135.

The related source loop is unrolled by 2 (including vectorization).

      6.1.1.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (2.65 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
97% of vector register length is used (average across all VPU instructions).


Details
96% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 87% of VPU addition or subtraction instructions are used in vector version.





      6.1.1.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 27.97 to 9.88 cycles (2.83x speedup).


      6.1.1.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 14 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.1.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 74 FP arithmetical operations:
 - 36: addition or subtraction (8 inside FMA instructions)
 - 30: multiply (8 inside FMA instructions)
 - 8: divide
The binary loop does not load or store any data.







      6.1.2  -  Loop 62 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:61-63,69-75.

The related source loop is unrolled by 2 (including vectorization).

      6.1.2.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

22% of peak computational performance is used (7.28 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
95% of vector register length is used (average across all VPU instructions).


Details
91% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 66% of VPU addition or subtraction instructions are used in vector version.
 - 0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.2.1.2  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 22 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.2.1.3  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 15 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.2.1.4  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 74 FP arithmetical operations:
 - 38: addition or subtraction (22 inside FMA instructions)
 - 34: multiply (22 inside FMA instructions)
 - 2: divide
The binary loop does not load or store any data.







      6.1.3  -  Loop 47 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:74-87,93-99.

The related source loop is unrolled by 4 (including vectorization).

      6.1.3.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

9% of peak computational performance is used (2.93 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
97% of vector register length is used (average across all VPU instructions).


Details
96% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 87% of VPU addition or subtraction instructions are used in vector version.





      6.1.3.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 27.97 to 9.75 cycles (2.87x speedup).


      6.1.3.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.3.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 12 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.3.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 82 FP arithmetical operations:
 - 36: addition or subtraction (8 inside FMA instructions)
 - 38: multiply (8 inside FMA instructions)
 - 8: divide
The binary loop does not load or store any data.







      6.1.4  -  Loop 392 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:48-55.

The related source loop is unrolled by 2 (including vectorization).

      6.1.4.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.24 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
94% of vector register length is used (average across all VPU instructions).


Details
92% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of VPU addition or subtraction instructions are used in vector version.





      6.1.4.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 14.51 to 2.50 cycles (5.80x speedup).


      6.1.4.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 2 FMA (fused multiply-add) operations.




      6.1.4.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.4.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 18 FP arithmetical operations:
 - 2: addition or subtraction (all inside FMA instructions)
 - 12: multiply (2 inside FMA instructions)
 - 2: divide
 - 2: square root
The binary loop does not load or store any data.







      6.1.5  -  Loop 155 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:246-248.

The related source loop is unrolled by 8 (including vectorization).

      6.1.5.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.14 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
92% of vector register length is used (average across all VPU instructions).


Details
88% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 57% of VPU addition or subtraction instructions are used in vector version.





      6.1.5.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 27.97 to 4.38 cycles (6.39x speedup).


      6.1.5.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 8 FMA (fused multiply-add) operations.




      6.1.5.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 5 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.5.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 32 FP arithmetical operations:
 - 16: addition or subtraction (8 inside FMA instructions)
 - 8: multiply (all inside FMA instructions)
 - 8: divide
The binary loop does not load or store any data.







      6.1.6  -  Loop 151 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:182-184.

The related source loop is unrolled by 2 (including vectorization).

      6.1.6.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.14 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
86% of vector register length is used (average across all VPU instructions).


Details
81% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 33% of VPU addition or subtraction instructions are used in vector version.





      6.1.6.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 6.99 to 2.38 cycles (2.94x speedup).


      6.1.6.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 2 FMA (fused multiply-add) operations.




      6.1.6.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 5 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.6.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 8 FP arithmetical operations:
 - 4: addition or subtraction (2 inside FMA instructions)
 - 2: multiply (all inside FMA instructions)
 - 2: divide
The binary loop does not load or store any data.







      6.1.7  -  Loop 302 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:55-59.

The related source loop is unrolled by 2 (including vectorization).

      6.1.7.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

13% of peak computational performance is used (4.44 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Code clean check
  ---------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 4.50 to 4.00 cycles (1.12x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
 - For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop



      6.1.7.1.2  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
93% of vector register length is used (average across all VPU instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 4.50 to 4.31 cycles (1.04x speedup).

Details
91% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 75% of VPU addition or subtraction instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.





      6.1.7.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.7.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 8 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.7.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 20 FP arithmetical operations:
 - 12: addition or subtraction
 - 8: multiply
The binary loop does not load or store any data.







      6.1.8  -  Loop 82 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:254-261.

The related source loop is unrolled by 2 (including vectorization).

      6.1.8.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

4% of peak computational performance is used (1.43 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
93% of vector register length is used (average across all VPU instructions).


Details
90% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 71% of VPU addition or subtraction instructions are used in vector version.





      6.1.8.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 13.99 to 4.00 cycles (3.50x speedup).


      6.1.8.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 2 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.8.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 8 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.8.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 20 FP arithmetical operations:
 - 12: addition or subtraction (2 inside FMA instructions)
 - 4: multiply (2 inside FMA instructions)
 - 4: divide
The binary loop does not load or store any data.







      6.1.9  -  Loop 161 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:212-215,227-240.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214-215,227-234,237-240.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Failed to get the number of paths
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths


      6.1.9.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.22 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Code clean check
  ---------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 13.99 to 2.83 cycles (4.94x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
 - For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop



      6.1.9.1.2  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 47% of vector register length is used (average across all VPU instructions).
By vectorizing your loop, you can lower the cost of an iteration from 13.99 to 6.99 cycles (2.00x speedup).

Details
All VPU instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)<<image_col_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)





      6.1.9.1.3  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 13.99 to 9.88 cycles (1.42x speedup).


      6.1.9.1.4  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 17 FP arithmetical operations:
 - 7: addition or subtraction (1 inside FMA instructions)
 - 6: multiply (1 inside FMA instructions)
 - 4: divide
The binary loop does not load or store any data.







      6.1.10  -  Loop 154 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:149-154,160-176.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:149-154,160,163-170,173-176.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Failed to get the number of paths
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths


      6.1.10.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.22 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Code clean check
  ---------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 13.99 to 2.83 cycles (4.94x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
 - For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop



      6.1.10.1.2  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 48% of vector register length is used (average across all VPU instructions).
By vectorizing your loop, you can lower the cost of an iteration from 13.99 to 6.99 cycles (2.00x speedup).

Details
All VPU instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)<<image_col_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)





      6.1.10.1.3  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 13.99 to 9.63 cycles (1.45x speedup).


      6.1.10.1.4  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.10.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 17 FP arithmetical operations:
 - 7: addition or subtraction (1 inside FMA instructions)
 - 6: multiply (1 inside FMA instructions)
 - 4: divide
The binary loop does not load or store any data.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/home/eoseret/qaas/qaas_runs/178-542-6039/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/orig/oneview_run_1785426560"
[MAQAO] Info: 
